CN102034811B - Low-voltage SCR (Silicon Controlled Rectifier) structure for ESD (Electronic Static Discharge) protection of integrated circuit chip - Google Patents

Abstract

A low-voltage SCR structure used for ESD protection of integrated circuit chips belongs to the field of electronic technology. Including two types of low-voltage SCR ESD protection devices, the first type of device integrates 2 N-well diodes and 2 NMOS, where the N-well diode is connected between I/O and VDD, the NMOS is connected between VDD and VSS, and the N The well diode and NMOS form the SCR structure to provide ESD protection between PS, PD mode and VDD-VSS. The second type of device integrates 2 P-well diodes and 2 PMOS, where the P-well diode is connected between I/O and VSS, and the PMOS is connected between VSS and VDD, and the P-well diode and PMOS together form an SCR structure. Provides ESD protection between ND, NS mode and VDD-VSS. The present invention has higher maintenance voltage and anti-latch-up effect when the chip is working normally, and the trigger voltage is lower when ESD occurs, and the trigger speed is faster; it provides multiple modes of ESD protection functions and excellent ESD protection performance At the same time, it can also effectively reduce the relative area of the chip occupied by the protection device and reduce the parasitic capacitance.

Description

A Low Voltage SCR Structure Used for ESD Protection of Integrated Circuit Chips

technical field

The invention belongs to the field of electronic technology, and relates to the design technology of an electrostatic discharge (ESD) protection circuit for a semiconductor integrated circuit chip, in particular to a single control circuit to control a plurality of protection devices, so that the protection devices can be timely and effectively Discharge the ESD current, and at the same time save the silicon chip area occupied by the control circuit.

Background technique

Electrostatic discharge is a common phenomenon in the process of manufacturing, producing, assembling, testing, storing, and transporting semiconductor devices or circuits. The pin is passed into the integrated circuit and destroys the internal circuit of the integrated circuit. In order to solve this problem, a protection circuit is usually placed next to the I/O pin during chip design. The protection circuit must be activated before the electrostatic discharge pulse damages the internal circuit to quickly clamp the excessive voltage. , thereby reducing the damage caused by the ESD phenomenon. However, with the reduction of the feature size of the integrated circuit process, its protection against electrostatic discharge is also reduced, making CMOS devices more sensitive to static electricity, and the damage caused by ESD is more serious. Moreover, under the same electrostatic protection measures, advanced technology (such as lightly doped drain structure, etc.) will easily reduce the ESD protection ability of the device; even if the size of the device is increased, its anti-ESD ability will not be improved. The increase in size leads to an increase in the chip area, and the parasitic effects brought about by it are also more obvious. Therefore, how to improve the anti-ESD capability of the chip and minimize the area used by the ESD protection circuit has become an important issue that must be considered in the design of integrated circuits.

In the CMOS process, the most commonly used I/O port protection circuit is composed of a pair of complementary GGNMOS (Gate-Grounded NMOS) transistors and GDPMOS (Gate-VDD PMOS) transistors, as shown in Figure 1. When a positive ESD pulse occurs at the drain end of the MOS transistor (relative to the source and substrate ends), an avalanche breakdown will occur between the drain region and the substrate region of the MOS transistor, and thus an avalanche current will be generated, which will make the substrate region A potential difference is generated between the source region and the source region. When the potential difference is greater than the turn-on voltage of the diode, the parasitic bipolar transistor (BJT) composed of the drain/substrate/source of the MOS is turned on, and thus discharges the ESD current to To protect the internal circuit of the chip. However, since the MOS tube used for ESD protection often requires a large width, and in order to increase the uniformity of the opening of the multi-finger MOS tube when ESD occurs, the drain end of the MOS is often extended, that is, the drain end contact hole is elongated. The distance to the gate edge (Drain Contact to Gate Spacing, referred to as DCGS) to increase the ballast resistance of the drain, but this will bring a large parasitic capacitance, resulting in an increase in the load capacitance of the I/O port.

In order to reduce the load capacitance and save the chip area, the area occupied by the ESD protection device connected in parallel with the I/O should be reduced, and a higher ESD protection capability can be achieved in a smaller area, as shown in Figure 2 or Figure 3 protection circuit shown.

In Figure 2, two small-area diodes are used for protection, and a large-area power supply clamping circuit is made between VDD-VSS next to the I/O pad, so that it occurs between I/O and VDD, or The ESD current between I/O and VSS can pass through the forward conduction of the diode between I/O and VDD or the diode between I/O and VSS respectively, and discharge through the power clamp circuit at the same time. Although the load capacitance of the I/O port of this circuit is small, it is difficult to obtain a large voltage drop (the sum of the forward conduction voltage of the diode and the maintenance voltage of the power supply clamp circuit) when discharging the ESD current. Higher ESD resistance.

In Figure 3, a deformed structure of SCR (Silicon Controlled Rectifier)—Low-Voltage Trigger SCR (LVTSCR for short)—is used to replace the GGNMOS tube and GDPMOS tube in Figure 1. Due to the positive ESD pulse of LVTSCR (that is, I/O PAD is at positive potential and VSS is at zero potential), the MOS transistor composed of N ⁺ region, P well, and N ⁺ region in the device will undergo avalanche breakdown, and cause the device The internal parasitic PNP and NPN transistors turn on and discharge the ESD current, and under the reverse ESD pulse (that is, I/O PAD is at negative potential and VSS is at zero potential), it behaves as a forward-biased diode. Therefore, for The ESD that occurs between the I/O pin and the VSS pin can be directly discharged in the form of an SCR or a forward-biased diode through the LVTSCR connected between the I/O pin and VSS pin; for the ESD that occurs between the I/O pin and the VDD pin The ESD can be discharged by connecting the LVTSCR (in the form of SCR or forward-biased diode) in series with the LVTSCR (in the form of forward-biased diode or SCR) connected between VDD and VSS. The SCR device can be used to obtain a strong anti-ESD capability, but when the chip is working normally, due to external interference, the SCR may be falsely triggered, causing a latch-up effect (latch-up), resulting in the failure of the chip. In order to avoid this phenomenon, the method of increasing the maintenance voltage of SCR is often used to make the maintenance voltage higher than the power supply voltage, but increasing the maintenance voltage will increase the voltage drop on the LVTSCR when the ESD current is discharged, and then increase the power consumption. Therefore, the anti-ESD ability of the device is often reduced. This is also the design difficulty of using SCR as an ESD protection device.

Contents of the invention

The invention provides a low-voltage SCR structure used for ESD protection of integrated circuit chips, which can provide the protection of PS mode, PD mode, NS mode and ND mode based on the SCR structure for the I/O port of the integrated circuit chip, and at the same time protect the integrated circuit chip Protection based on the NMOS structure and the PMOS structure is provided between the chip power supply rail VDD and VSS; the present invention has a higher maintenance voltage when the integrated circuit chip is working normally, and is resistant to latch-up effects, while the trigger voltage is lower when ESD occurs, The triggering speed is fast; while the present invention provides multiple modes of ESD protection functions and excellent ESD protection performance, it can also effectively reduce the relative area of the chip occupied by the protection device and reduce the parasitic capacitance.

A kind of low-voltage SCR structure that is used for integrated circuit chip ESD protection, as shown in Figure 4, comprises the low-voltage SCR ESD protection device of two types, and the SCR ESD protection device of described two types is integrated with the integrated circuit chip that they protect on the same chip substrate.

The first type of low-voltage SCR ESD protection device includes one N well region, two P well regions, three P ⁺ regions and four N ⁺ regions located on the surface of the substrate, and the N well region is sandwiched between two Between the P well regions; the middle of the top of the first P well region is the first N ⁺ region, the side of the top of the first P well region away from the N well region is the first P ⁺ region; the middle of the top of the second P well region is the second In the N ⁺ region, the top of the second P well region away from the N well region is the second P ⁺ region; the middle of the top of the N well region is the third P ⁺ region; the third N ⁺ region is located on the top of the first P well region and the N The region where the top of the well region is connected, the fourth N ⁺ region is located in the region where the top of the second P well region and the top of the N well region are connected; above the first P well region between the first N ⁺ region and the third N ⁺ region There is a first polysilicon region, an insulating layer is provided between the first polysilicon region and the first P well region; there is a second polysilicon region above the second P well region between the second N ⁺ region and the fourth N ⁺ region. In the crystal silicon region, an insulating layer is provided between the second polysilicon region and the second P well region. The third P ⁺ area is connected to the I/O port of the protected integrated circuit chip through metal wires, the third and fourth N ⁺ areas are connected to the VDD rail in the power supply double rail of the protected integrated circuit chip through metal wires, and the second 1. The second P ⁺ region, the first and second N ⁺ regions and the first and second polysilicon regions are all connected to the VSS rail in the dual power rails of the protected integrated circuit chip through metal wires.

The second type of low-voltage SCR ESD protection device includes one P well region, two N well regions, three N ⁺ regions and four P ⁺ regions located on the surface of the substrate, and the P well regions are sandwiched between two Between the N well regions; the middle of the top of the first N well region is the first P ⁺ region, the side of the top of the first N well region away from the P well region is the first N ⁺ region; the middle of the top of the second N well region is the second In the P ⁺ region, the top of the second N well region away from the P well region is the second N ⁺ region; the middle of the top of the P well region is the third N ⁺ region; the third P ⁺ region is located on the top of the first N well region and the P The region where the top of the well region is connected, the fourth P ⁺ region is located in the region where the top of the second N well region and the top of the P well region are connected; above the first N well region between the first P ⁺ region and the third P ⁺ region There is a first polysilicon region, an insulating layer is provided between the first polysilicon region and the first N well region; there is a second polysilicon region above the second N well region between the second P ⁺ region and the fourth P ⁺ region. In the crystal silicon region, an insulating layer is provided between the second polysilicon region and the second N well region. The third N ⁺ region is connected to the I/O port of the protected integrated circuit chip through metal wires, the third and fourth P ⁺ regions are connected to the VSS rail in the double power rail of the protected integrated circuit chip through metal wires, and the third 1. The second N ⁺ region, the first and second P ⁺ regions, and the first and second polysilicon regions are all connected to the VDD rail in the dual power rails of the protected integrated circuit chip through metal wires.

Above-mentioned technical scheme also can have some deformation schemes:

(1), as shown in Figure 5, on the basis of the technical scheme shown in Figure 4, the third and fourth polysilicon regions are added above the N well region of the low-voltage SCR ESD protection device of the first type; The third polysilicon region is located above the N well region between the third N ⁺ region and the third P ⁺ region, and the fourth polysilicon region is located in the N well region between the fourth N ⁺ region and the third P ⁺ region Above the well region, there is an insulating layer between the third and fourth polysilicon regions and the N well region; the third and fourth polysilicon regions are connected to the I/O port of the protected integrated circuit chip through a metal wire . The third and fourth polysilicon regions are added above the P well region of the second type of low-voltage SCR ESD protection device; the third polysilicon region is located between the third P ⁺ region and the third N ⁺ region Above the P well region, the fourth polysilicon region is located above the P well region between the fourth P ⁺ region and the third N ⁺ region, and there is insulation between the third and fourth polysilicon regions and the P well region layer; the third and fourth polysilicon regions are connected to the I/O port of the protected integrated circuit chip through metal wires.

(2), as shown in Figure 6, on the basis of the technical scheme shown in Figure 4, the third and fourth polysilicon regions are added above the N well region of the low-voltage SCR ESD protection device of the first type; The third polysilicon region is located above the N well region between the third N ⁺ region and the third P ⁺ region, and the fourth polysilicon region is located in the N well region between the fourth N ⁺ region and the third P ⁺ region Above the well region, there is an insulating layer between the third and fourth polysilicon regions and the N well region; the third and fourth polysilicon regions are connected to the VDD in the power double rail of the protected integrated circuit chip through metal wires rail connected. The third and fourth polysilicon regions are added above the P well region of the second type of low-voltage SCR ESD protection device; the third polysilicon region is located between the third P ⁺ region and the third N ⁺ region Above the P well region, the fourth polysilicon region is located above the P well region between the fourth P ⁺ region and the third N ⁺ region, and there is insulation between the third and fourth polysilicon regions and the P well region layer; the third and fourth polysilicon regions are connected to the VSS rail in the dual power rails of the protected integrated circuit chip through metal wires.

(3), as shown in Figure 7, on the basis of the technical scheme shown in Figure 6, the first polysilicon region in the low-voltage SCRESD protection device of the first type and the power supply double rail of the integrated circuit chip of protection A capacitor is added between the VDD rails in the VDD rail, and a resistor is added between the first polysilicon region and the VSS rail in the power supply double rail of the integrated circuit chip to be protected; between the second polysilicon region and the protected integrated circuit A capacitor is added between the VDD rails in the dual power rails of the chip, and a resistor is added between the second polysilicon region and the VSS rail in the dual power rails of the integrated circuit chip to be protected. A capacitor is added between the first polysilicon region in the second type of low-voltage SCR ESD protection device and the VSS rail in the power supply double rail of the integrated circuit chip to be protected, and between the first polysilicon region and the protected Add a resistor between the VDD rails in the power rails of the integrated circuit chip; add a capacitor between the second polysilicon region and the VSS rail in the protected integrated circuit chip power rails, and in the second polysilicon region A resistor is added between the VDD rail and the VDD rail of the protected integrated circuit chip's power rail.

In the above scheme, the first type of low-voltage SCR ESD protection device provides PS mode (I/O pin potential is positive, VSS pin potential is zero, and all other pins are floating) and PD mode (I/O pin potential is positive). Positive, VDD pin potential is zero, other pins are floating) and ESD protection between VDD-VSS. The second type of low-voltage SCR ESD protection device provides ND mode (I/O pin potential is negative, VDD pin potential is zero, and other pins are all floating) and NS mode (I/O pin potential is negative, VSS pin potential is zero, the rest of the pins are floating) and ESD protection between VDD-VSS.

The low-voltage SCR structure used for integrated circuit chip ESD protection provided by the present invention includes two types of low-voltage SCR ESD protection devices, the first type of device integrates 2 N well diode structures and 2 NMOS structures, and wherein 2 N well diodes are connected to Between the I/O port and VDD, two NMOSs are connected between VDD and VSS, and the N-well diode and NMOS together form an SCR structure. The first type of low-voltage SCR ESD protection device provides ESD protection between PS mode, PD mode and VDD-VSS. The second type of device integrates 2 P-well diode structures and 2 PMOS structures, in which 2 P-well diodes are connected between the I/O port and VSS, 2 PMOS are connected between VSS and VDD, and the P-well diodes Together with PMOS to form the SCR structure. The second type of low-voltage SCRESD protection device provides ESD protection between ND mode, NS mode and VDD-VSS.

The low-voltage SCR structure used for integrated circuit chip ESD protection provided by the present invention has the following characteristics:

1. Using the SCR structure as the ESD protection device of the I/O port requires a smaller area than the conventional MOS structure, and the parasitic capacitance it brings will also be reduced.

2. In the protection structure of the I/O port, the parasitic capacitance between the VDD rail and the VSS rail is used through the diode, so that the trigger voltage of the device is lower and the trigger speed is faster when ESD occurs, so the protection effect on the internal circuit better.

3. In the protection structure of the I/O port, the well area where the I/O port is located is directly connected to the VDD rail or the VSS rail, making it difficult for the ESD protection device to trigger when the integrated circuit chip is working normally, so it is not easy to be caused by external interference False triggering and affecting the normal operation of the chip.

4. The MOS device that can be used for ESD protection between the VDD rail and the VSS rail is directly integrated in the protection structure of the I/O port, and the area of the chip is hardly increased, so it will be possible to reduce or save special use Protect the area of the device between the VDD rail and the VSS rail. Moreover, when an ESD discharge occurs at a certain I/O port, the protection device integrated between the VDD rail and the VSS rail in other I/O port protection structures can also provide an auxiliary ESD current discharge channel.

Description of drawings

FIG. 1 is a schematic diagram of one of the commonly used ESD protection circuits for the I/O port of a chip.

FIG. 2 is a schematic diagram of a second ESD protection circuit commonly used at a chip I/O port.

FIG. 3 is a schematic diagram of a third ESD protection circuit commonly used at a chip I/O port.

FIG. 4 is a structural diagram of the first low-voltage SCR used for ESD protection of integrated circuit chips provided by the present invention.

FIG. 5 is a structural diagram of the second low-voltage SCR used for ESD protection of integrated circuit chips provided by the present invention.

FIG. 6 is a structure diagram of a third low-voltage SCR used for ESD protection of integrated circuit chips provided by the present invention.

FIG. 7 is a structure diagram of a fourth low-voltage SCR used for ESD protection of integrated circuit chips provided by the present invention.

8 is a schematic diagram of the current discharge path of the first type of protection device under the PS mode ESD pulse (positive pulse of I/O port to VSS) in the low-voltage SCR structure used for ESD protection of integrated circuit chip provided by the present invention.

FIG. 9 is an equivalent circuit diagram of FIG. 8 .

FIG. 10 is a simulation curve of a common LVTSCR device with a width of 50 microns and the first type of protection device with a width of 50 microns in the present invention when ESD transient occurs.

11 is a schematic diagram of the current discharge path of the first type of protection device in the PD mode ESD pulse (positive pulse of I/O port to VDD) in the low-voltage SCR structure used for ESD protection of integrated circuit chip provided by the present invention.

12 is a schematic diagram of the current discharge path of the second type of protection device in the ND mode ESD pulse (the negative pulse of the I/O port to VDD) in the low-voltage SCR structure used for ESD protection of integrated circuit chips provided by the present invention.

FIG. 13 is an equivalent schematic diagram of FIG. 12 .

14 is a schematic diagram of the current discharge path of the second type of protection device in the NS mode ESD pulse (the negative pulse of the I/O port to VSS) in the low-voltage SCR structure used for ESD protection of integrated circuit chips provided by the present invention.

Detailed ways

In order to make the technical problems, technical solutions and positive effects to be solved by the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings.

Specific implementation mode one

A kind of low-voltage SCR structure that is used for integrated circuit chip ESD protection, as shown in Figure 4, comprises the low-voltage SCR ESD protection device of two types, and the SCR ESD protection device of described two types is integrated with the integrated circuit chip that they protect on the same chip substrate.

The first type of low-voltage SCR ESD protection device includes one N well region, two P well regions, three P ⁺ regions and four N ⁺ regions located on the surface of the substrate, and the N well region is sandwiched between two Between the P well regions; the middle of the top of the first P well region is the first N ⁺ region, the side of the top of the first P well region away from the N well region is the first P ⁺ region; the middle of the top of the second P well region is the second In the N ⁺ region, the top of the second P well region away from the N well region is the second P ⁺ region; the middle of the top of the N well region is the third P ⁺ region; the third N ⁺ region is located on the top of the first P well region and the N The region where the top of the well region is connected, the fourth N ⁺ region is located in the region where the top of the second P well region and the top of the N well region are connected; above the first P well region between the first N ⁺ region and the third N ⁺ region There is a first polysilicon region, an insulating layer is provided between the first polysilicon region and the first P well region; there is a second polysilicon region above the second P well region between the second N ⁺ region and the fourth N ⁺ region. In the crystal silicon region, an insulating layer is provided between the second polysilicon region and the second P well region. The third P ⁺ area is connected to the I/O port of the protected integrated circuit chip through metal wires, the third and fourth N ⁺ areas are connected to the VDD rail in the power supply double rail of the protected integrated circuit chip through metal wires, and the second 1. The second P ⁺ region, the first and second N ⁺ regions and the first and second polysilicon regions are all connected to the VSS rail in the dual power rails of the protected integrated circuit chip through metal wires.

The second type of low-voltage SCR ESD protection device includes one P well region, two N well regions, three N ⁺ regions and four P ⁺ regions located on the surface of the substrate, and the P well regions are sandwiched between two Between the N well regions; the middle of the top of the first N well region is the first P ⁺ region, the side of the top of the first N well region away from the P well region is the first N ⁺ region; the middle of the top of the second N well region is the second In the P ⁺ region, the top of the second N well region away from the P well region is the second N ⁺ region; the middle of the top of the P well region is the third N ⁺ region; the third P ⁺ region is located on the top of the first N well region and the P The region where the top of the well region is connected, the fourth P ⁺ region is located in the region where the top of the second N well region and the top of the P well region are connected; above the first N well region between the first P ⁺ region and the third P ⁺ region There is a first polysilicon region, an insulating layer is provided between the first polysilicon region and the first N well region; there is a second polysilicon region above the second N well region between the second P ⁺ region and the fourth P ⁺ region. In the crystal silicon region, an insulating layer is provided between the second polysilicon region and the second N well region. The third N ⁺ region is connected to the I/O port of the protected integrated circuit chip through metal wires, the third and fourth P ⁺ regions are connected to the VSS rail in the double power rail of the protected integrated circuit chip through metal wires, and the third 1. The second N ⁺ region, the first and second P ⁺ regions, and the first and second polysilicon regions are all connected to the VDD rail in the dual power rails of the protected integrated circuit chip through metal wires.

Specific implementation mode two

As shown in Figure 5, on the basis of the technical scheme shown in Figure 4, the third and fourth polysilicon regions are added above the N well region of the first type of low-voltage SCR ESD protection device; the third polysilicon region the silicon region is above the N well region between the third N ⁺ region and the third P ⁺ region, the fourth polysilicon region is above the N well region between the fourth N ⁺ region and the third P ⁺ region, There is an insulating layer between the third and fourth polysilicon regions and the N well region; the third and fourth polysilicon regions are connected to the I/O port of the protected integrated circuit chip through metal wires. The third and fourth polysilicon regions are added above the P well region of the second type of low-voltage SCR ESD protection device; the third polysilicon region is located between the third P ⁺ region and the third N ⁺ region Above the P well region, the fourth polysilicon region is located above the P well region between the fourth P ⁺ region and the third N ⁺ region, and there is insulation between the third and fourth polysilicon regions and the P well region layer; the third and fourth polysilicon regions are connected to the I/O port of the protected integrated circuit chip through metal wires.

Specific implementation mode three

As shown in Figure 6, on the basis of the technical scheme shown in Figure 4, the third and fourth polysilicon regions are added above the N well region of the first type of low-voltage SCR ESD protection device; the third polysilicon region the silicon region is above the N well region between the third N ⁺ region and the third P ⁺ region, the fourth polysilicon region is above the N well region between the fourth N ⁺ region and the third P ⁺ region, There is an insulating layer between the third and fourth polysilicon regions and the N well region; the third and fourth polysilicon regions are connected to the VDD rail in the dual power rails of the protected integrated circuit chip through metal wires. The third and fourth polysilicon regions are added above the P well region of the second type of low-voltage SCR ESD protection device; the third polysilicon region is located between the third P ⁺ region and the third N ⁺ region Above the P well region, the fourth polysilicon region is located above the P well region between the fourth P ⁺ region and the third N ⁺ region, and there is insulation between the third and fourth polysilicon regions and the P well region layer; the third and fourth polysilicon regions are connected to the VSS rail in the dual power rails of the protected integrated circuit chip through metal wires.

Specific implementation mode four

As shown in Figure 7, on the basis of the technical scheme shown in Figure 6, the first polysilicon region in the first type of low-voltage SCR ESD protection device and the VDD rail in the power supply double rail of the integrated circuit chip to be protected Add a capacitor between the first polysilicon region and the VSS rail in the power supply double rail of the integrated circuit chip to be protected; add a resistor between the second polysilicon region and the power supply double rail of the integrated circuit chip to be protected A capacitor is added between the VDD rails in the circuit, and a resistor is added between the second polysilicon region and the VSS rail in the power dual rails of the integrated circuit chip to be protected. A capacitor is added between the first polysilicon region in the second type of low-voltage SCR ESD protection device and the VSS rail in the power supply double rail of the integrated circuit chip to be protected, and between the first polysilicon region and the protected Add a resistor between the VDD rails in the power rails of the integrated circuit chip; add a capacitor between the second polysilicon region and the VSS rail in the protected integrated circuit chip power rails, and in the second polysilicon region A resistor is added between the VDD rail and the VDD rail of the protected integrated circuit chip's power rail.

In the above scheme, the first type of low-voltage SCR ESD protection device provides PS mode (I/O pin potential is positive, VSS pin potential is zero, and all other pins are floating) and PD mode (I/O pin potential is positive). Positive, VDD pin potential is zero, other pins are floating) and ESD protection between VDD-VSS. The second type of low-voltage SCR ESD protection device provides ND mode (I/O pin potential is negative, VDD pin potential is zero, and other pins are all floating) and NS mode (I/O pin potential is negative, VSS pin potential is zero, the rest of the pins are floating) and ESD protection between VDD-VSS.

Taking the technical solution shown in FIG. 6 as an example, the working principle of the low-voltage SCR structure for integrated circuit chip ESD protection provided by the present invention will be described below (the working principles of other specific embodiments are basically the same).

Under the ESD pulse of PS mode, the current discharge path of the first type of low-voltage SCR ESD protection device is shown in Fig. 8 . Parasitic BJT device Q1 (composed of N well region, third N ⁺ region, first P well region and first N ⁺ region) and Q2 (composed of third P ⁺ region, N well region, third N ⁺ region and A P well area) constitutes the SCR structure, and the capacitor C is the parasitic capacitance between the VDD-VSS rails. Under PS mode ESD conditions, the equivalent schematic diagram of the first type of low-voltage SCR ESD protection device is shown in Figure 9. The NMOS structure in the SCR structure will break down, and the breakdown current will make the base of the BJT device Q1 - The emitter junction (composed of the first P well area and the first N ⁺ area) is forward biased, so that Q1 is turned on; at the same time, since the VDD rail is floating in PS mode, the voltage of the I/O port will be The parasitic capacitance C is charged through the Q2 emitter-base junction (composed of the third P ⁺ region, N well region and the third N ⁺ region) diode, thereby forming the base current of Q2 and turning on Q2. The collector current of Q2 will provide current to the base of Q1, the collector current of Q1 will provide current to the base of Q2, and finally the SCR structure is turned on to discharge the ESD current. The general N-type LVTSCR is only triggered by the conduction of Q1 caused by NMOS breakdown. Therefore, the first type of low-voltage SCR ESD protection device will turn on faster than the ordinary LVTSCR when ESD occurs. Assuming that the width of the device is 50um, in the first type of low-voltage SCR ESD protection device provided by the present invention, a capacitance of 1pF is used to simulate the parasitic capacitance between the VDD rail and the VSS rail (in fact, the parasitic capacitance is much greater than 1pF) , as shown in FIG. 10 , the voltage spike of the first type of low-voltage SCR ESD protection device provided by the present invention is lower than that of the common LVTSCR device, so it can better protect the internal circuit. In addition, unlike the general N-type LVTSCR, Q2 does not lead to the well resistance from the base region to the emitter region, so the injection efficiency of the emitter region of Q2 will be higher, and the clamping voltage of the SCR structure will be lower, and thus achieve better ESD protection effect. After the SCR is turned on, if the ESD voltage between the I/O port and VSS is still high at this time, the ESD current can be connected to VDD through the SCR structure of other I/O ports using the same protection structure in the chip. The NMOS structure and the PMOS structure bleed between the VSS rail and the VSS rail. Specifically in Fig. 9, when there are N I/O ports in the protected integrated circuit chip using the first type of low-voltage SCRESD protection device provided by the present invention, except for the NMOS structure contained in the SCR, such connection The number of additional NMOS structures between the VDD rail and the VSS rail is (N-1), and the number of PMOS structures is N. Therefore, when multiple I/O ports use this protection structure, the anti-ESD capability of the chip will be enhanced. The current paths in Figure 9 are explained as follows:

Path 1: the discharge path through the SCR structure of the first type of low-voltage SCR ESD protection device itself;

Path 2: an additional discharge path through the PMOS structure;

Path 3: an additional discharge path through the NMOS structure;

Path 4: The parasitic capacitance C between the VDD rail and the VSS rail triggers the current path of the SCR.

Under the ESD pulse in PD mode, the current discharge path of the first type of low-voltage SCR ESD protection device provided by the present invention is shown in FIG. 11 . The ESD current is discharged from the I/O port to the VDD rail through the diode (consisting of the third P ⁺ region, the N well region and the third N ⁺ region).

For the ESD phenomenon that occurs between VDD and VSS, it can be discharged through the NMOS structure in the first type of low-voltage SCR ESD protection device. Therefore, the first type of low-voltage SCR ESD protection device provided by the present invention can provide ESD protection between the VDD rail and the VSS rail while providing ESD protection for the I/O port.

When the protected integrated circuit chip works normally, the potential of the VSS rail is zero, the VDD rail is connected to the power supply, and the potential of the I/O port is between the potentials of the VDD rail and the VSS rail. The VSS rail biases the first and second P well regions to zero potential respectively through the first and second P ⁺ regions connected to it, while the N well region is biased by the third and fourth N+ regions connected to the VDD rail. Set at the VDD rail potential, therefore, the first type of low-voltage SCR ESD protection device is equivalent to an NMOS structure connected between the VDD rail and the VSS rail and a P ⁺ connected between the I/O port and the VDD rail /N-well diode. Even if the potential of the I/O port is slightly higher than the VDD rail potential due to noise, the generated current will discharge the VDD rail through the P ⁺ /N well diode, thereby limiting the injection of carriers into the body region, making it normal The triggering of the SCR structure is very difficult during operation, that is, the anti-false triggering effect of the first type of low-voltage SCR ESD protection device will be better than that of ordinary LVTSCR. In addition, for the I/O port, the parasitic capacitance introduced by the first type of low-voltage SCR ESD protection device will only be caused by the diode, so this structure can meet the requirement of small parasitic capacitance like the circuit in Figure 2.

Under the ESD pulse in ND mode, the current discharge path of the second type of low-voltage SCR ESD protection device is shown in Fig. 12 . In the second type of low-voltage SCRESD protection device, parasitic BJT device Q3 (composed of P well region, third P ⁺ region, first N well region and first P ⁺ region) and Q4 (composed of third N ⁺ region, P Well region, the third P ⁺ region and the first N well region) form the SCR structure, and the capacitor C is the parasitic capacitance between the VDD rail and the VSS rail. Under ESD conditions in ND mode, the equivalent schematic diagram of the second type of low-voltage SCR ESD protection device is shown in Figure 13. The PMOS structure in the SCR structure will break down, and the breakdown current will make the emitter-base junction of Q3 (composed of the first P ⁺ region and the first N well region) be forward biased, thereby turning on Q3; at the same time, due to In ND mode, the VSS rail is floating, so the voltage at the I/O port will pass through the Q4 base-emitter junction (composed of the third P ⁺ region, P well region, and third N ⁺ region) diode pair parasitic capacitance C Charge, thereby forming the base current of Q4, so that Q4 is turned on. The collector current of Q4 will provide current to the base of Q3, the collector current of Q3 will provide current to the base of Q4, and finally the SCR structure is turned on to discharge the ESD current. The general P-type LVTSCR is only triggered by the conduction of Q1 caused by the breakdown of the PMOS structure. Therefore, the turn-on speed of this device will be faster than that of ordinary LVTSCR when ESD occurs. In addition, unlike the general P-type LVTSCR, Q4 does not lead to the well resistance from the base region to the emitter region, so the injection efficiency of the emitter region of Q4 will be higher, and the clamping voltage of the SCR structure will be lower, and thus achieve better ESD protection effect. After the SCR is turned on, if the ESD voltage between the VDD rail and the I/O port is still high at this time, the ESD current can pass through the second I/O port of other I/O ports that use the same protection structure in the protected integrated circuit chip. The NMOS structure and the PMOS structure connected between the VDD rail and the VSS rail in this type of low-voltage SCR ESD protection device discharge. Specifically in Figure 13, when there are N I/O ports in the protected integrated circuit chip using the second type of low-voltage SCR ESD protection device, except for the second type of low-voltage SCR ESD protection device itself In addition to the PMOS structure, the number of additional PMOS structures connected between the VDD rail and the VSS rail is (N-1), and the number of NMOS structures is N. Therefore, when the second type of low-voltage SCR ESD protection device is used in multiple I/O ports, the anti-ESD capability of the protected integrated circuit chip will be enhanced. The current paths in Figure 13 are explained as follows:

Path 5: through the second type of low-voltage SCR ESD protection device itself SCR discharge path;

Path 6: an additional discharge path through the PMOS structure;

Path 7: an additional discharge path through the NMOS structure;

Path 8: The trigger current path of the SCR caused by the parasitic capacitance C between the VDD rail and the VSS rail.

Under the ESD pulse in NS mode, the current discharge path of the second type of low-voltage SCR ESD protection device is shown in Fig. 14 . The ESD current is discharged from the VSS rail to the I/O port through the diode (consisting of the third P ⁺ region, P-well region and third N ⁺ region).

For the ESD phenomenon that occurs between VDD and VSS, it can be discharged through the PMOS structure in the second type of low-voltage SCR ESD protection device. Therefore, the second type of low-voltage SCR ESD protection device provides ESD protection between the VDD rail and the VSS rail while providing ESD protection for the I/O ports.

When the protected integrated circuit chip works normally, the potential of the VSS rail is zero, VDD is connected to the power supply, and the potential of the I/O port is between the potentials of the VDD rail and the VSS rail. The VDD rail biases the first and second N well regions to zero potential through the first and second N ⁺ regions connected to it, while the P well region is connected to the VSS rail by the third and fourth P ⁺ regions. Biased at the VSS rail potential, therefore, the second type of low-voltage SCR ESD protection device is equivalent to a PMOS structure connected between the VDD rail and the VSS rail and a PMOS structure connected between the I/O port and the VSS rail. well/N ⁺ diode. Even if the potential of the I/O port is slightly lower than the VSS rail potential due to noise, the generated current will discharge the VSS rail through the P-well/N ⁺ diode, thereby limiting the injection of carriers into the body region, making it normal The triggering of the SCR is very difficult during operation, that is, the second type of low-voltage SCRESD protection device has better anti-false triggering effect than ordinary LVTSCR. In addition, for the I/O port, the parasitic capacitance introduced by the second type of low-voltage SCR ESD protection device will only be caused by the diode, so this structure can meet the requirement of small parasitic capacitance like the circuit in Figure 2.

It should be noted that, since the low-voltage SCR structure used for the ESD protection of integrated circuit chips provided by the present invention is a symmetrical structure, only half of the working principle of the structure is described in the description of the above-mentioned working principle process, and the working principle of the other half of the structure is the same.

In summary, the low-voltage SCR structure used for integrated circuit chip ESD protection provided by the present invention can provide the ESD protection of PS, PD, NS and ND four modes for I/O ports, and can provide protection for VDD rail and VSS rail simultaneously. Provide protection between GGNMOS and GDPMOS. If multiple ports in an integrated circuit chip use the low-voltage SCR structure for integrated circuit chip ESD protection provided by the present invention, then the protected integrated circuit chip can be protected without a special VDD rail and VSS rail protection circuit. Provide relatively strong anti-ESD ability. Therefore, the area utilization ratio of the protection structure is high.

The above is only a specific description of the technical solution shown in FIG. 6 , and the working principles of the other three specific technical solutions are basically the same, and will not be repeated here. The technical solution shown in FIG. 4 lacks two gate control electrodes because there is no third and fourth polysilicon regions. In comparison, the trigger speed of this technical solution is reduced, and other performances are basically not affected. Compared with the technical solution shown in FIG. 5, the technical solution shown in FIG. 5 only changes the connection relationship, and its ESD protection capability is basically the same. The technical solution shown in Figure 7 adds an RC circuit between the VDD rail and the VSS rail, and improves the trigger speed of the MOS structure through the voltage coupling effect of the RC circuit, so it has a faster trigger speed, and other performances are basically No effect.

Claims (5)

1. a low pressure SCR structure that is used for the IC chip esd protection comprises two types low pressure SCR esd protection device, and the IC chip that said two types SCR esd protection device and they are protected is integrated on the same chip substrate;

First type low pressure SCR esd protection device comprises a N well region that is positioned at substrate surface, two P well regions, three P ⁺District and four N ⁺The district, said N well region is sandwiched between two P well regions; The one P well region crown center is a N ⁺The district, a P well region top is a P away from a side of N well region ⁺The district; The 2nd P well region crown center is the 2nd N ⁺The district, the 2nd P well region top is the 2nd P away from a side of N well region ⁺The district; N well region crown center is the 3rd P ⁺The district; The 3rd N ⁺The district is positioned at the zone that the first P well region top is connected with N well region top, the 4th N ⁺The district is positioned at the zone that the second P well region top is connected with N well region top; The one N ⁺District and the 3rd N ⁺P well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the P well region; The 2nd N ⁺District and the 4th N ⁺The 2nd P well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd P well region;

The 3rd P ⁺The district links to each other with the I/O port of the IC chip of being protected through plain conductor, the 3rd, the 4th N ⁺The district links to each other first, second P through the VDD rail in the power supply double track of plain conductor and the IC chip of being protected ⁺District and first, second N ⁺District and first, second multi-crystal silicon area all link to each other through the VSS rail in the power supply double track of plain conductor and the IC chip of being protected;

Second type low pressure SCR esd protection device comprises a P well region that is positioned at substrate surface, two N well regions, three N ⁺District and four P ⁺The district, said P well region is sandwiched between two N well regions; The one N well region crown center is a P ⁺The district, a N well region top is a N away from a side of P well region ⁺The district; The 2nd N well region crown center is the 2nd P ⁺The district, the 2nd N well region top is the 2nd N away from a side of P well region ⁺The district; P well region crown center is the 3rd N ⁺The district; The 3rd P ⁺The district is positioned at the zone that the first N well region top is connected with P well region top, the 4th P ⁺The district is positioned at the zone that the second N well region top is connected with P well region top; The one P ⁺District and the 3rd P ⁺N well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the N well region; The 2nd P ⁺District and the 4th P ⁺The 2nd N well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd N well region;

The 3rd N ⁺The district links to each other with the I/O port of the IC chip of being protected through plain conductor, the 3rd, the 4th P ⁺The district links to each other first, second N through the VSS rail in the power supply double track of plain conductor and the IC chip of being protected ⁺District and first, second P ⁺District and first, second multi-crystal silicon area all link to each other through the VDD rail in the power supply double track of plain conductor and the IC chip of being protected.

2. the low pressure SCR structure that is used for the IC chip esd protection according to claim 1 is characterized in that: said first type low pressure SCR esd protection device also has the 3rd, the 4th multi-crystal silicon area: said the 3rd multi-crystal silicon area is positioned at the 3rd N ⁺District and the 3rd P ⁺N well region top between the district, said the 4th multi-crystal silicon area is positioned at the 4th N ⁺District and the 3rd P ⁺N well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the N well region; Said the 3rd, the 4th multi-crystal silicon area links to each other with the I/O port of the IC chip of being protected through plain conductor;

Said second type low pressure SCR esd protection device also has the 3rd, the 4th multi-crystal silicon area: said the 3rd multi-crystal silicon area is positioned at the 3rd P ⁺District and the 3rd N ⁺P well region top between the district, said the 4th multi-crystal silicon area is positioned at the 4th P ⁺District and the 3rd N ⁺P well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the P well region; Said the 3rd, the 4th multi-crystal silicon area links to each other with the I/O port of the IC chip of being protected through plain conductor.

3. the low pressure SCR structure that is used for the IC chip esd protection according to claim 1 is characterized in that: said first type low pressure SCR esd protection device also has the 3rd, the 4th multi-crystal silicon area: said the 3rd multi-crystal silicon area is positioned at the 3rd N ⁺District and the 3rd P ⁺N well region top between the district, said the 4th multi-crystal silicon area is positioned at the 4th N ⁺District and the 3rd P ⁺N well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the N well region; Said the 3rd, the 4th multi-crystal silicon area links to each other through the VDD rail in the power supply double track of plain conductor and the IC chip of being protected;

Said second type low pressure SCRESD protection device also has the 3rd, the 4th multi-crystal silicon area: said the 3rd multi-crystal silicon area is positioned at the 3rd P ⁺District and the 3rd N ⁺P well region top between the district, said the 4th multi-crystal silicon area is positioned at the 4th P ⁺District and the 3rd N ⁺P well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the P well region; Said the 3rd, the 4th multi-crystal silicon area links to each other through the VSS rail in the power supply double track of plain conductor and the IC chip of being protected.

4. the low pressure SCR structure that is used for the IC chip esd protection according to claim 3; It is characterized in that: in the said first type low pressure SCR esd protection device; Also have an electric capacity between the VDD rail in the power supply double track of first multi-crystal silicon area and the IC chip protected, also have a resistance between the VSS rail in the power supply double track of first multi-crystal silicon area and the IC chip protected; Also have an electric capacity between the VDD rail in the power supply double track of second multi-crystal silicon area and the IC chip protected, also have a resistance between the VSS rail in the power supply double track of second multi-crystal silicon area and the IC chip protected;

In the said second type low pressure SCR esd protection device; Also have an electric capacity between the VSS rail in the power supply double track of first multi-crystal silicon area and the IC chip protected, also have a resistance between the VDD rail in the power supply double track of first multi-crystal silicon area and the IC chip protected; Also have an electric capacity between the VSS rail in the power supply double track of second multi-crystal silicon area and the IC chip protected, also have a resistance between the VDD rail in the power supply double track of second multi-crystal silicon area and the IC chip protected.

5. according to the arbitrary low pressure SCR structure that is used for the IC chip esd protection of claim 1-4, it is characterized in that said substrate is P type substrate, N type substrate or SOI substrate.

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