CN102208412B - SCR structure used for ESD protection of integrated circuit output stage - Google Patents
SCR structure used for ESD protection of integrated circuit output stage Download PDFInfo
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Abstract
The invention, which belongs to the electronics technology field, provides a silicon controlled rectifier (SCR) structure used for electrostatic discharge (ESD) protection of an integrated circuit output stage. The SCR structure comprises SCR structures of two types. One SCR structure of a first type integrates two equivalent PMOSs and two equivalent NMOSs; and EDS protection of a PS mode and a PD mode as well as between VDD and VSS is provided by the SCR structure of the first type. The PMOSs are connected between an outlet of an integrated circuit and the VDD, and grids are controlled by a circuit superior drive; and thus a PMOS tube of pair transistors of an integrated circuit output stage is constructed. Besides, the NMOSs are connected between the VDD and the VSS. The other SCR structure of a second type integrates two equivalent NMOSs and two equivalent PMOSs and an EDS protection of an ND mode and an NS mode as well as between the VDD and the VSS is provided by the SCR structure of the second type. The NMOSs are connected between the outlet and the VSS, and grids are controlled by the circuit superior drive; and thus an NMOS tube of the pair transistors of the integrated circuit output stage is constructed. Besides, the PMOSs are connected between the VDD and the VSS. According to the invention, the ESD protection of different modes is provided for the integrated circuit output stage; moreover, the maintaining voltage is high and an anti-latch up effect is allowed. When the ESD occurs, a trigger voltage is low and a trigger speed is fast. Furthermore, the pair transistors of the integrated circuit output stage is integrated, so that a utilization rate of an integrated circuit chip area is higher.
Description
Technical field
The invention belongs to electronic technology field; The static that relates to semiconductor integrated circuit chip discharges (ElectroStatic Discharge; Abbreviate ESD as) the protective circuit designing technique, refer to a kind of SCR (Silicon Controlled Rectifier) structure that is used for integrated circuit output level esd protection especially.
Background technology
Static discharge (Electrostatic Discharge is called for short ESD) phenomenon tends to make integrated circuit (Integrated Circuits is called for short ICs) to receive permanent damage, and therefore causes heavy losses.In order to address this problem, chip generally can connect a protective circuit on each pin side when designing, and this protective circuit should be worked esd pulse causes damage to internal circuit before, to eliminate the damage that the ESD high voltage causes internal circuit.The reducing of device size in the As IC, the junction depth of device is more and more shallow, and gate oxide is more and more thinner, and has lightly doped drain (LDD) structure, and these change all makes the damage voltage of device reduce, and integrated circuit is damaged by static discharge more easily.Add that current esd protection circuit area ratio/occupancy ratio is generally higher, and the problem of the parasitic capacitance of thereupon bringing makes the performance of protective circuit can not be satisfactory.Therefore, must add the excellent more protective circuit of performance in the chip is damaged by ESD to prevent among the IC circuit or device.
In CMOS technology, the output of circuit has several kinds of protective circuits commonly used at present:
The one, do the esd protection between delivery outlet and the power line with GGNMOS (Gate-Grounded NMOS), the GDPMOS (Gate-VDD PMOS) of a pair of complementation, do the esd clamp system circuit between power line VDD and the VSS with a GGNMOS, as shown in Figure 1.With GGNMOS is example, and when positive esd pulse (with respect to source and substrate terminal) takes place the drain terminal of NMOS pipe, avalanche breakdown will take place for the drain region and the substrate zone of NMOS pipe; Therefore and produce avalanche current; This electric current will make between substrate zone and the source region and produce potential difference, when this potential difference during greater than the cut-in voltage of diode, opened by the parasitic bipolar transistor (BJT) that leakage/substrate/source of NMOS is formed; And the ESD electric current of releasing thus, to play protective effect to the chip internal circuit.GGNMOS in this esd protection circuit and GDPMOS are that the BJT through parasitism carries out leakage current; But because there is the problem of inhomogeneous openability in the MOS device of many finger; Even device area very greatly often also is difficult to obtain good protection effect, cause the grid width of required metal-oxide-semiconductor in the structure often bigger, can bring very big parasitic capacitance; This will cause the load capacitance of efferent duct to increase, and output frequency descends.
The 2nd, protect with efferent duct self; Like Fig. 2; But in order to reach the requirement of ESD protection, must carry out special optimization, like the drain terminal contact hole that strengthens metal-oxide-semiconductor distance (Drain Contact to Gate Spacing to the grid edge to the output mos pipe; Be called for short DCGS) etc., and strengthen the increase that DCGS will cause the output resistance and the area occupied of efferent duct.But because this method still is to protect with the MOS device, therefore also exist with before a kind of method similar problem, promote the ESD ability with the wide method of increase mos gate simply and often can not well deal with problems.
Three are to use a kind of distressed structure of SCR as shown in Figure 3 (Silicon Controlled Rectifier), and--SCR that low pressure triggers (Low-Voltage Trigger SCR is called for short LVTSCR)--replaces GGNMOS pipe and GDPMOS pipe among Fig. 1.Because LVTSCR is under forward esd pulse (be that I/O PAD is a positive potential, VSS is a zero potential), in the device by N
+District, P trap, N
+Avalanche breakdown can take place in the metal-oxide-semiconductor that the district forms; And cause entozoic PNP of device and NPN transistor to be opened and the ESD electric current of releasing, and under reverse esd pulse (be that I/O PAD is a negative potential, VSS is a zero potential); It shows as the character of a forward-biased diode; Therefore, for the ESD that occurs between I/O pin and the VSS pin, can directly release with the mode of SCR or forward-biased diode through the LVTSCR that is connected between I/O and VSS; For the ESD that occurs between I/O pin and the VDD pin, then can and be connected in the mode that the LVTSCR (with the mode of forward-biased diode or SCR) between VDD and the VSS is in series through this LVTSCR (with the mode of SCR or forward-biased diode) and release.Use the SCR structure can obtain very strong anti-ESD ability, but when the chip operate as normal, because outside interference, false triggering may appear in SCR, causes latch-up (latch-up), causes the inefficacy of chip.
It is a kind of universal architecture that low pressure shown in Figure 3 triggers the SCR structure; It can be used for the esd protection between all I/O PAD of integrated circuit and the power supply double track; When this low pressure triggering SCR structure is used for the esd protection of integrated circuit output level; The output of integrated circuit output level must be made on the chip substrate separately to pipe and occupy certain chip area separately, causes the lower problem of chip area utilance.
Summary of the invention
The present invention provides a kind of SCR structure that is used for integrated circuit output level esd protection; The protection of PS pattern, PD pattern, NS pattern and ND pattern based on the SCR structure can be provided, simultaneously to the protection based on NMOS structure and PMOS structure is provided between IC chip power rail VDD and the VSS to the output stage of integrated circuit; The present invention has the higher voltage of keeping when the IC chip operate as normal, anti-latch-up, and the trigger voltage when ESD takes place is lower, triggers rapid speed; The present invention is in the esd protection function that is provided for integrated circuit output level various modes and excellent esd protection performance, and the output stage of also integrated integrated circuit circuit is to managing, so the area of chip utilance is higher.
Technical scheme of the present invention is following:
A kind of SCR structure that is used for integrated circuit output level esd protection, as shown in Figure 4, comprise two types SCR structure, the IC chip that this SCR structure of two types and they are protected is integrated on the same chip substrate.
Said first type SCR structure comprises a N well region that is positioned at substrate surface, two P well regions, five P
+District and four N
+The district, said N well region is sandwiched between two P well regions; The one P well region crown center is a N
+The district, a P well region top is a P away from a side of N well region
+The district; The 2nd P well region crown center is the 2nd N
+The district, the 2nd P well region top is the 2nd P away from a side of N well region
+The district; N well region crown center is the 3rd P
+The district; The 3rd N
+The district is positioned at the zone that the first P well region top is connected with N well region top, the 4th N
+The district is positioned at the zone that the second P well region top is connected with N well region top; The 4th P
+The district is positioned at N well region top near the 3rd N
+Distinguish a side; The 5th P
+The district is positioned at N well region top near the 4th N
+Distinguish a side; The one N
+District and the 3rd N
+P well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the P well region; The 2nd N
+District and the 4th N
+The 2nd P well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd P well region; The 4th P
+District and the 3rd P
+N well region top between the district has the 3rd multi-crystal silicon area, has insulating barrier between the 3rd multi-crystal silicon area and the N well region; The 5th P
+District and the 3rd P
+N well region top between the district has the 4th multi-crystal silicon area, has insulating barrier between the 4th multi-crystal silicon area and the N well region.The 3rd P
+The district links to each other through the output port of plain conductor with the integrated circuit of being protected, the 3rd N
+District, the 4th N
+District, the 4th P
+District, the 5th P
+The district links to each other through the VDD rail in the power supply double track of plain conductor and the IC chip of being protected; First, second P
+District and first, second N
+District and first, second multi-crystal silicon area all link to each other through the VSS rail in the power supply double track of plain conductor and the IC chip of being protected; Three, the 4th multi-crystal silicon area drives with the prime of circuit through plain conductor and links to each other.
Said second type SCR structure comprises a P well region that is positioned at substrate surface, two N well regions, five N
+District and four P
+The district, said P well region is sandwiched between two N well regions; The one N well region crown center is a P
+The district, a N well region top is a N away from a side of P well region
+The district; The 2nd N well region crown center is the 2nd P
+The district, the 2nd N well region top is the 2nd N away from a side of P well region
+The district; P well region crown center is the 3rd N
+The district; The 3rd P
+The district is positioned at the zone that the first N well region top is connected with P well region top, the 4th P
+The district is positioned at the zone that the second N well region top is connected with P well region top; The 4th N
+The district is positioned at P well region top near the 3rd P
+Distinguish a side; The 5th N
+The district is positioned at P well region top near the 4th P
+Distinguish a side; The one P
+District and the 3rd P
+N well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the N well region; The 2nd P
+District and the 4th P
+The 2nd N well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd N well region; The 4th N
+District and the 3rd N
+P well region top between the district has the 3rd multi-crystal silicon area, has insulating barrier between the 3rd multi-crystal silicon area and the P well region; The 5th N
+District and the 3rd N
+P well region top between the district has the 4th multi-crystal silicon area, has insulation between the 4th multi-crystal silicon area and the P well region.The 3rd N
+The district links to each other through the output port of plain conductor with the IC chip of being protected, the 3rd P
+District, the 4th P
+District, the 4th N
+District, the 5th N
+The district links to each other through the VSS rail in the power supply double track of plain conductor and the IC chip of being protected; First, second N
+District and first, second P
+District and first, second multi-crystal silicon area all link to each other through the VDD rail in the power supply double track of plain conductor and the IC chip of being protected; Three, the 4th multi-crystal silicon area drives with the prime of circuit through plain conductor and links to each other.
In the such scheme; Said first type SCR protection structure provides PS pattern (output pin current potential for just, VSS pin current potential is zero, all floating sky of all the other pins) and PD pattern, and (the output pin current potential is for just; VDD pin current potential is zero, and all the other pins are all floating empty) and VDD-VSS between the ESD protection.Said second type SCR protection structure provides the ND pattern, and (the output pin current potential is for negative; VDD pin current potential is zero; All the other pins are all floating empty) protect with ESD between NS pattern (the output pin current potential is for negative, and VSS pin current potential is zero, and all the other pins are all floating empty) and the VDD-VSS.
The SCR structure that is used for the integrated output stage of chip delivery outlet esd protection provided by the invention comprises two types SCR structure; The PMOS structure of 2 equivalences that first type SCR is integrated and the NMOS structure of 2 equivalences; Wherein 2 PMOS are connected between delivery outlet and the VDD, and its grid is connected to prime and drives, and constitute integrated circuit output level to the pipe of the PMOS in the pipe; 2 NMOS are connected between VDD and the VSS, and PMOS and NMOS form the SCR structure jointly.First type SCR structure provides the ESD between PS pattern, PD pattern and the VDD-VSS protection.The NMOS structure of 2 equivalences that second type SCR is integrated and the PMOS structure of 2 equivalences; Wherein 2 NMOS are connected between delivery outlet and the VSS; And its grid is connected to prime and drives; Constitute integrated circuit output level to the pipe of the NMOS in the pipe, 2 PMOS are connected between VSS and the VDD, and NMOS and PMOS form the SCR structure jointly.Second type SCR structure provides the ESD between ND pattern, NS pattern and the VDD-VSS protection.
The SCR structure that is used for integrated circuit output level esd protection provided by the invention has following characteristics:
1, use the SCR structure as esd protection structure, anti-ESD ability is strong, and shared chip area is little, and the parasitic capacitance of bringing is little.
2, the integrated NMOS and the PMOS structure of integrated circuit circuit output stage further improved the chip area utilance.
3, directly integratedly in the protection structure of delivery outlet can be used for the MOS device of esd protection between VDD rail and the VSS rail, and increase area of chip hardly, therefore can reduce or save special area as protection device between VDD rail and the VSS rail.
4, utilize the parasitic capacitance between VDD and the VSS rail to do triggering, the trigger voltage of structure under the ESD condition is lower, and speed is faster.
Description of drawings
Fig. 1 is one of chip output esd protection circuit commonly used, the sketch map of GGNMOS and GDPMOS protection structure.
Fig. 2 is two of chip output esd protection circuit commonly used, the sketch map of efferent duct self-protection structure.
Fig. 3 is three of chip output esd protection circuit commonly used, uses the sketch map of LVTSCR structure.
Fig. 4 is the SCR structural representation that is used for integrated circuit output level esd protection provided by the invention.
Fig. 5 is first type the conducting principle schematic of SCR structure under PS pattern (the output pin current potential is for just, and VSS pin current potential is zero, and all the other pins are all floating empty) esd pulse.
Fig. 6 is the schematic equivalent circuit of Fig. 5.
Fig. 7 is the simulation curve of first type of SCR structure and common LVTSCR.
Fig. 8 is first type the conducting principle schematic of SCR structure under PD pattern (the output pin current potential is for just, and VDD pin current potential is zero, and all the other pins are all floating empty) esd pulse.
Fig. 9 is second type the conducting principle schematic of SCR structure under ND pattern (the output pin current potential is for negative, and VDD pin current potential is zero, and all the other pins are all floating empty) esd pulse.
Figure 10 is the schematic equivalent circuit of Fig. 9.
Figure 11 is second type the conducting principle schematic of SCR structure under NS pattern (the output pin current potential is for negative, and VSS pin current potential is zero, and all the other pins are all floating empty) esd pulse.
Embodiment
In order to make technical problem to be solved by this invention, technical scheme and good effect clearer, the present invention is further elaborated below in conjunction with accompanying drawing.
Embodiment:
A kind of SCR structure that is used for integrated circuit output level esd protection, as shown in Figure 4, comprise two types SCR structure, the IC chip that this SCR structure of two types and they are protected is integrated on the same chip substrate.
Said first type SCR structure comprises a N well region that is positioned at substrate surface, two P well regions, five P
+District and four N
+The district, said N well region is sandwiched between two P well regions; The one P well region crown center is a N
+The district, a P well region top is a P away from a side of N well region
+The district; The 2nd P well region crown center is the 2nd N
+The district, the 2nd P well region top is the 2nd P away from a side of N well region
+The district; N well region crown center is the 3rd P
+The district; The 3rd N
+The district is positioned at the zone that the first P well region top is connected with N well region top, the 4th N
+The district is positioned at the zone that the second P well region top is connected with N well region top; The 4th P
+The district is positioned at N well region top near the 3rd N
+Distinguish a side; The 5th P
+The district is positioned at N well region top near the 4th N
+Distinguish a side; The one N
+District and the 3rd N
+P well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the P well region; The 2nd N
+District and the 4th N
+The 2nd P well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd P well region; The 4th P
+District and the 3rd P
+N well region top between the district has the 3rd multi-crystal silicon area, has insulating barrier between the 3rd multi-crystal silicon area and the N well region; The 5th P
+District and the 3rd P
+N well region top between the district has the 4th multi-crystal silicon area, has insulating barrier between the 4th multi-crystal silicon area and the N well region.The 3rd P
+The district links to each other through the output port of plain conductor with the integrated circuit of being protected, the 3rd N
+District, the 4th N
+District, the 4th P
+District, the 5th P
+The district links to each other through the VDD rail in the power supply double track of plain conductor and the IC chip of being protected; First, second P
+District and first, second N
+District and first, second multi-crystal silicon area all link to each other through the VSS rail in the power supply double track of plain conductor and the IC chip of being protected; Three, the 4th multi-crystal silicon area drives with the prime of circuit through plain conductor and links to each other.
Said second type SCR structure comprises a P well region that is positioned at substrate surface, two N well regions, five N
+District and four P
+The district, said P well region is sandwiched between two N well regions; The one N well region crown center is a P
+The district, a N well region top is a N away from a side of P well region
+The district; The 2nd N well region crown center is the 2nd P
+The district, the 2nd N well region top is the 2nd N away from a side of P well region
+The district; P well region crown center is the 3rd N
+The district; The 3rd P
+The district is positioned at the zone that the first N well region top is connected with P well region top, the 4th P
+The district is positioned at the zone that the second N well region top is connected with P well region top; The 4th N
+The district is positioned at P well region top near the 3rd P
+Distinguish a side; The 5th N
+The district is positioned at P well region top near the 4th P
+Distinguish a side; The one P
+District and the 3rd P
+N well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the N well region; The 2nd P
+District and the 4th P
+The 2nd N well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd N well region; The 4th N
+District and the 3rd N
+P well region top between the district has the 3rd multi-crystal silicon area, has insulating barrier between the 3rd multi-crystal silicon area and the P well region; The 5th N
+District and the 3rd N
+P well region top between the district has the 4th multi-crystal silicon area, has insulation between the 4th multi-crystal silicon area and the P well region.The 3rd N
+The district links to each other through the output port of plain conductor with the IC chip of being protected, the 3rd P
+District, the 4th P
+District, the 4th N
+District, the 5th N
+The district links to each other through the VSS rail in the power supply double track of plain conductor and the IC chip of being protected; First, second N
+District and first, second P
+District and first, second multi-crystal silicon area all link to each other through the VDD rail in the power supply double track of plain conductor and the IC chip of being protected; Three, the 4th multi-crystal silicon area drives with the prime of circuit through plain conductor and links to each other.In the such scheme; Said first type SCR protection structure provides PS pattern (output pin current potential for just, VSS pin current potential is zero, all floating sky of all the other pins) and PD pattern, and (the output pin current potential is for just; VDD pin current potential is zero, and all the other pins are all floating empty) and VDD-VSS between the ESD protection.Said second type SCR protection structure provides the ND pattern, and (the output pin current potential is for negative; VDD pin current potential is zero; All the other pins are all floating empty) protect with ESD between NS pattern (the output pin current potential is for negative, and VSS pin current potential is zero, and all the other pins are all floating empty) and the VDD-VSS.
Below in conjunction with accompanying drawing the SCR structure that is used for the integrated output stage of chip delivery outlet esd protection provided by the invention is carried out the operation principle explanation.
Under the esd pulse of PS pattern, the current drain path of first type SCR structure is as shown in Figure 5.Parasitic BJT device Q1 is (by N well region, the 3rd N
+District, a P well region and a N
+The district forms) with Q2 (by the 3rd P
+District, N well region, the 3rd N
+A district and a P well region) composition SCR structure.Under the ESD of PS pattern condition, the equivalent schematic diagram of first type SCR structure is as shown in Figure 6, and the NMOS structure in the SCR structure can puncture, breakdown potential fail to be convened for lack of a quorum make BJT device Q1 base-emitter junction (by a P well region and a N
+The district forms) positively biased, thus make the Q1 conducting.And the collector current of Q1 will provide electric current for the base stage of Q2, and the collector current of Q2 will provide electric current for the base stage of Q1, and final SCR structure conducting is with the ESD electric current of releasing.And before the conducting of SCR structure; Because the parasitic capacitance C that exists between VDD rail and the VSS rail can be through emission-Ji junction diode charging of Q2; This charging current will make Q2 conducting faster; Therefore the conducting of SCR structure will not exclusively depend on the puncture of nmos device, and promptly the opening speed of SCR structure can be faster.Its simulation result is as shown in Figure 7; Capacitance simulation VDD and the parasitic capacitance between the VSS (generally the parasitic capacitance between VDD and the VSS is worth much larger than this) with 50pF; Can find out; Compare with common LVTSCR structure, the trigger voltage of SCR structure provided by the invention drops to about 4.6V from about 11.7V.In addition, different with general LVTSCR structure is, because Q2 does not draw the trap resistance from the base to the emitter region, so the emitter region injection efficiency of Q2 can be higher, and the clamp voltage of SCR structure can be lower, and therefore reach better esd protection effect.Current path among Fig. 6 is explained as follows:
Path 1: through the current drain path of first type SCR structure;
Path 2: the charging current path of triggering Q2 through parasitic capacitance between VDD rail and the VSS rail.
Under the esd pulse of PD pattern, the current drain path of SCR structure provided by the present invention first type is as shown in Figure 8.The ESD electric current from delivery outlet through diode (by the 3rd P
+District, N well region and the 3rd N
+The district forms) release to the VDD rail.
For the ESD phenomenon that betides between VDD and the VSS, all can release through the NMOS structure in first type the SCR structure.Therefore, SCR structure provided by the present invention first type also can be for providing ESD protection when the ESD protection is provided for delivery outlet between VDD rail and the VSS rail.
When the chip operate as normal, the current potential of VDD is high, through the N that is attached thereto
+Make the N trap be biased to high potential, the P trap then is biased in zero potential by VSS, and therefore, this moment, first type of SCR structural equivalents provided by the invention was a NMOS and a PMOS who is connected between delivery outlet and the VDD who is connected between VDD and the VSS; And wherein the grid of PMOS owing to drive with the prime of integrated circuit links to each other, so this PMOS is exactly an efferent duct of integrated circuit, and has been integrated by first type of SCR structure provided by the invention.
Under the esd pulse of ND pattern, the current drain path of second type SCR structure is as shown in Figure 9.Parasitic BJT device Q3 is (by P well region, the 3rd P
+District, a N well region and a P
+The district forms) with Q4 (by the 3rd N
+District, P well region, the 3rd P
+A district and a N well region) composition SCR structure.Under the ESD of ND pattern condition, the equivalent schematic diagram of second type SCR structure is shown in figure 10, and the PMOS structure in the SCR structure can puncture, breakdown potential fail to be convened for lack of a quorum make BJT device Q3 base-emitter junction (by a N well region and a P
+The district forms) positively biased, thus make the Q3 conducting.And the collector current of Q3 will provide electric current for the base stage of Q4, and the collector current of Q4 will provide electric current for the base stage of Q3, and final SCR structure conducting is with the ESD electric current of releasing.And before the conducting of SCR structure; Because the parasitic capacitance C that exists between VDD rail and the VSS rail can be through emission-Ji junction diode charging of Q4; This charging current will make Q4 conducting faster; Therefore the conducting of SCR structure will not exclusively depend on the puncture of PMOS device, and promptly the opening speed of SCR can be faster.In addition, different with general LVTSCR structure is, Q4 does not draw the trap resistance from the base to the emitter region, so the emitter region injection efficiency of Q4 can be higher, and the clamp voltage of SCR structure can be lower, and therefore reaches better esd protection effect.Current path among Figure 10 is explained as follows:
Path 3: through the current drain path of second type SCR structure;
Path 4: the charging current path of triggering Q4 through parasitic capacitance between VDD rail and the VSS rail.
Under the esd pulse of NS pattern, the current drain path of SCR structure provided by the present invention second type is shown in figure 11.The ESD electric current from delivery outlet through diode (by the 3rd N
+District, P well region and the 3rd P
+The district forms) release to the VSS rail.
For the ESD phenomenon that betides between VDD and the VSS, all can release through the PMOS structure in second type the SCR structure.Therefore, SCR structure provided by the present invention second type also can be for providing ESD protection when the ESD protection is provided for delivery outlet between VDD rail and the VSS rail.
When the chip operate as normal, the current potential of VSS is zero, through the P that is attached thereto
+Make the P trap be biased to zero potential; The N trap then is biased in the VDD current potential by VDD; Therefore, this moment, second type of SCR structural equivalents provided by the invention was a PMOS and a NMOS who is connected between delivery outlet and the VSS who is connected between VDD and the VSS, and wherein the grid of NMOS links to each other owing to driving with the prime of integrated circuit; Therefore this NMOS another efferent duct that is exactly integrated circuit, and integrated by second type of SCR structure provided by the invention.
What need to specify is, because the SCR structure that is used for the integrated circuit esd protection provided by the invention is a symmetrical structure, in the description of above-mentioned operation principle process, has only described the operation principle of half structure, and the operation principle of second half structure is the same.
The present invention provides a kind of SCR structure that is used for integrated circuit output level esd protection; The protection of PS pattern, PD pattern, NS pattern and ND pattern based on the SCR structure can be provided, simultaneously to the protection based on NMOS structure and PMOS structure is provided between IC chip power rail VDD and the VSS to the output stage of integrated circuit; The present invention has the higher voltage of keeping when the IC chip operate as normal, anti-latch-up, and the trigger voltage when ESD takes place is lower, triggers rapid speed; The present invention is in the esd protection function that is provided for integrated circuit output level various modes and excellent esd protection performance, and the output stage of also integrated integrated circuit circuit is to managing, so the area of chip utilance is higher.
Claims (1)
1. a SCR structure that is used for integrated circuit output level esd protection comprises two types SCR structure, and the IC chip that this SCR structure of two types and they are protected is integrated on the same chip substrate;
Said first type SCR structure comprises a N well region that is positioned at substrate surface, two P well regions, five P
+District and four N
+The district, said N well region is sandwiched between two P well regions; The one P well region crown center is a N
+The district, a P well region top is a P away from a side of N well region
+The district; The 2nd P well region crown center is the 2nd N
+The district, the 2nd P well region top is the 2nd P away from a side of N well region
+The district; N well region crown center is the 3rd P
+The district; The 3rd N
+The district is positioned at the zone that the first P well region top is connected with N well region top, the 4th N
+The district is positioned at the zone that the second P well region top is connected with N well region top; The 4th P
+The district is positioned at N well region top near the 3rd N
+Distinguish a side; The 5th P
+The district is positioned at N well region top near the 4th N
+Distinguish a side; The one N
+District and the 3rd N
+P well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the P well region; The 2nd N
+District and the 4th N
+The 2nd P well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd P well region; The 4th P
+District and the 3rd P
+N well region top between the district has the 3rd multi-crystal silicon area, has insulating barrier between the 3rd multi-crystal silicon area and the N well region; The 5th P
+District and the 3rd P
+N well region top between the district has the 4th multi-crystal silicon area, has insulating barrier between the 4th multi-crystal silicon area and the N well region; The 3rd P
+The district links to each other through the output port of plain conductor with the integrated circuit of being protected, the 3rd N
+District, the 4th N
+District, the 4th P
+District, the 5th P
+The district links to each other through the VDD rail in the power supply double track of plain conductor and the IC chip of being protected; First, second P
+District and first, second N
+District and first, second multi-crystal silicon area all link to each other through the VSS rail in the power supply double track of plain conductor and the IC chip of being protected; Three, the 4th multi-crystal silicon area drives with the prime of circuit through plain conductor and links to each other;
Said second type SCR structure comprises a P well region that is positioned at substrate surface, two N well regions, five N
+District and four P
+The district, said P well region is sandwiched between two N well regions; The one N well region crown center is a P
+The district, a N well region top is a N away from a side of P well region
+The district; The 2nd N well region crown center is the 2nd P
+The district, the 2nd N well region top is the 2nd N away from a side of P well region
+The district; P well region crown center is the 3rd N
+The district; The 3rd P
+The district is positioned at the zone that the first N well region top is connected with P well region top, the 4th P
+The district is positioned at the zone that the second N well region top is connected with P well region top; The 4th N
+The district is positioned at P well region top near the 3rd P
+Distinguish a side; The 5th N
+The district is positioned at P well region top near the 4th P
+Distinguish a side; The one P
+District and the 3rd P
+N well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the N well region; The 2nd P
+District and the 4th P
+The 2nd N well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd N well region; The 4th N
+District and the 3rd N
+P well region top between the district has the 3rd multi-crystal silicon area, has insulating barrier between the 3rd multi-crystal silicon area and the P well region; The 5th N
+District and the 3rd N
+P well region top between the district has the 4th multi-crystal silicon area, has insulation between the 4th multi-crystal silicon area and the P well region; The 3rd N
+The district links to each other through the output port of plain conductor with the IC chip of being protected, the 3rd P
+District, the 4th P
+District, the 4th N
+District, the 5th N
+The district links to each other through the VSS rail in the power supply double track of plain conductor and the IC chip of being protected; First, second N
+District and first, second P
+District and first, second multi-crystal silicon area all link to each other through the VDD rail in the power supply double track of plain conductor and the IC chip of being protected; Three, the 4th multi-crystal silicon area drives with the prime of circuit through plain conductor and links to each other.
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| CN2011101310590A CN102208412B (en) | 2011-05-19 | 2011-05-19 | SCR structure used for ESD protection of integrated circuit output stage |
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| CN2011101310590A CN102208412B (en) | 2011-05-19 | 2011-05-19 | SCR structure used for ESD protection of integrated circuit output stage |
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| CN102208412B true CN102208412B (en) | 2012-11-07 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102544115B (en) * | 2012-03-15 | 2013-12-11 | 电子科技大学 | ESD (Electro-Static discharge) protection device with low trigger voltage and high balllast resistance for SCR (Silicon Controlled Rectifier) |
| CN102544001B (en) * | 2012-03-15 | 2014-04-09 | 电子科技大学 | SCR (Silicon Controlled Rectifier) structure for providing ESD ( Electro-Static discharge) protection for I/O (Input/Output) port of integrated circuit under all modes |
| CN103839942B (en) * | 2014-02-20 | 2016-07-06 | 无锡市晶源微电子有限公司 | High pressure esd protection structure |
| CN103915433A (en) * | 2014-03-28 | 2014-07-09 | 中国科学院上海技术物理研究所 | Radiation resistant SCR electrostatic protection device with annular grid MOSFET embedded |
| CN107658295B (en) * | 2017-11-10 | 2023-09-29 | 江南大学 | A bidirectional ESD protection anti-latch-up device with a fully symmetrical double-gate-controlled diode triggered SCR structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6605493B1 (en) * | 2001-08-29 | 2003-08-12 | Taiwan Semiconductor Manufacturing Company | Silicon controlled rectifier ESD structures with trench isolation |
| CN101207121A (en) * | 2006-12-15 | 2008-06-25 | 旺宏电子股份有限公司 | Electrostatic discharge protection circuit |
| CN101826523A (en) * | 2010-04-14 | 2010-09-08 | 电子科技大学 | Silicon controlled rectifier electrostatic discharge protection circuit structure triggered by grid controlled diode |
| CN102034811A (en) * | 2010-09-21 | 2011-04-27 | 电子科技大学 | Low-voltage SCR (Silicon Controlled Rectifier) structure for ESD (Electronic Static Discharge) protection of integrated circuit chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6756642B2 (en) * | 2002-11-07 | 2004-06-29 | Taiwan Semiconductor Manufacturing Co., Ltd | Integrated circuit having improved ESD protection |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6605493B1 (en) * | 2001-08-29 | 2003-08-12 | Taiwan Semiconductor Manufacturing Company | Silicon controlled rectifier ESD structures with trench isolation |
| CN101207121A (en) * | 2006-12-15 | 2008-06-25 | 旺宏电子股份有限公司 | Electrostatic discharge protection circuit |
| CN101826523A (en) * | 2010-04-14 | 2010-09-08 | 电子科技大学 | Silicon controlled rectifier electrostatic discharge protection circuit structure triggered by grid controlled diode |
| CN102034811A (en) * | 2010-09-21 | 2011-04-27 | 电子科技大学 | Low-voltage SCR (Silicon Controlled Rectifier) structure for ESD (Electronic Static Discharge) protection of integrated circuit chip |
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| CN102208412A (en) | 2011-10-05 |
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