CN204695069U - A kind of control circuit preventing remote control mistrip for specially becoming acquisition terminal - Google Patents
A kind of control circuit preventing remote control mistrip for specially becoming acquisition terminal Download PDFInfo
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- CN204695069U CN204695069U CN201520405255.6U CN201520405255U CN204695069U CN 204695069 U CN204695069 U CN 204695069U CN 201520405255 U CN201520405255 U CN 201520405255U CN 204695069 U CN204695069 U CN 204695069U
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- sheffer stroke
- stroke gate
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Abstract
The utility model relates to a kind of control circuit preventing remote control mistrip for specially becoming acquisition terminal.Reset chip is welding system CPU and the first Sheffer stroke gate respectively, and the first Sheffer stroke gate connects the second Sheffer stroke gate, and the second Sheffer stroke gate connects rest-set flip-flop circuit, and rest-set flip-flop circuit connects the 5th Sheffer stroke gate, and the 5th Sheffer stroke gate connects d type flip flop; The I/O mouth First Line YK_EN1 of CPU connects the first Sheffer stroke gate and meets GND through pull down resistor R4; The I/O mouth second line YK_EN2 of CPU connects the 4th Sheffer stroke gate and meets VCC through pull-up resistor R3; The remote control that d type flip flop meets CPU exports control pin, and d type flip flop connects photoelectric isolating circuit, and photoelectric isolating circuit connects relay through driving circuit.Reset chip is only used in that system voltage is normal, system program normal operation time could export high level, so can determine that inerrancy trip signal sends.
Description
Technical field
The utility model relates to a kind of control circuit preventing remote control mistrip for specially becoming acquisition terminal.
Background technology
Special change acquisition terminal can realize the monitoring of load to Electricity customers and electric flux, and electric company realizes the ordered electric of power customer and the adjustment of network load by remote control tripping operation.According to existing remote control trip method, special change acquisition terminal is directly by MCU(micro-control unit) I/O port line drive and realize remote control tripping operation, its major defect is: main control MCU occurs that unexpected race flies, in system electrification and MCU initialization procedure, easily cause remote control misoperation, and then send error tripping order.
Utility model content
Technical problem to be solved in the utility model is, a kind of control circuit preventing remote control mistrip for specially becoming acquisition terminal is provided, reset chip is only used in that system voltage is normal, system program normal operation time could export high level, in order to guarantee that inerrancy trip signal sends.
The technical solution of the utility model is as follows:
A kind of control circuit preventing remote control mistrip for specially becoming acquisition terminal, it comprises CPU, reset chip and d type flip flop, it is characterized in that: also comprise the first Sheffer stroke gate D2C, the second Sheffer stroke gate D4B, the 3rd Sheffer stroke gate D2A, the 4th Sheffer stroke gate D2D and the 5th Sheffer stroke gate D2B, the 3rd Sheffer stroke gate D2A and the 4th Sheffer stroke gate D2D forms rest-set flip-flop circuit; Wherein, the RST pin of reset chip connects the reseting pin of CPU and an input pin of the first Sheffer stroke gate D2C respectively, first Sheffer stroke gate D2C output pin connects two input pins of the second Sheffer stroke gate D4B, the output pin of the second Sheffer stroke gate D4B connects the input pin of rest-set flip-flop circuit, the output pin of rest-set flip-flop circuit connects two input pins of the 5th Sheffer stroke gate D2B, and the output pin of the 5th Sheffer stroke gate D2B connects the CLR pin of d type flip flop; The I/O mouth First Line YK_EN1 of CPU connects another input pin of the first Sheffer stroke gate D2C and meets GND through pull down resistor R4; The I/O mouth second line YK_EN2 of CPU connects an input pin of the 4th Sheffer stroke gate D2D and meets VCC through pull-up resistor R3; The remote control that data in pin D1 to the D8 pin of d type flip flop and CLK pin meet CPU respectively exports control pin, and output pin Q1 to the Q8 of d type flip flop connects photoelectric isolating circuit respectively, and photoelectric isolating circuit connects relay through driving circuit.
Good effect of the present utility model is: just must send trip signal by relay by a complicated logical order when terminal is determined to send trip signal by relay.And with reset chip export high level signal be the necessary condition sending trip signal.Reset chip is only used in that system voltage is normal, system program normal operation time could export high level, so can determine that inerrancy trip signal sends.
Accompanying drawing explanation
Fig. 1 is circuit theory diagrams of the present utility model.
Embodiment
The utility model is further illustrated below in conjunction with drawings and Examples.
As shown in Figure 1, the present embodiment comprises CPU1, reset chip 7 and the d type flip flop 2 that model is SAM9260, also comprise the first Sheffer stroke gate D2C, the second Sheffer stroke gate D4B, the 3rd Sheffer stroke gate D2A, the 4th Sheffer stroke gate D2D and the 5th Sheffer stroke gate D2B, the 3rd Sheffer stroke gate D2A and the 4th Sheffer stroke gate D2D forms rest-set flip-flop circuit 3.
Wherein, the RST pin of reset chip 7 connects the reseting pin of CPU1 and an input pin of the first Sheffer stroke gate D2C respectively, first Sheffer stroke gate D2C output pin connects two input pins of the second Sheffer stroke gate D4B, the output pin of the second Sheffer stroke gate D4B connects an input pin R(i.e. input pin of the 3rd Sheffer stroke gate D2A of rest-set flip-flop circuit 3), the output pin of rest-set flip-flop circuit 3 connects two input pins of the 5th Sheffer stroke gate D2B, the output pin of the 5th Sheffer stroke gate D2B connects the CLR pin of d type flip flop 2, ensure only in the normal situation of system state, just can send trip signal.
The I/O mouth First Line YK_EN1 of CPU1 connects another input pin of the first Sheffer stroke gate D2C and meets GND through pull down resistor R4; The I/O mouth second line YK_EN2 of CPU1 connects an input pin of the 4th Sheffer stroke gate D2D and meets VCC through pull-up resistor R3.Thus ensure that, in system electrification process, when the I/O mouth of CPU is unstable, trip signal cannot send.
The present embodiment also comprises photoelectric isolating circuit 4, driving circuit 6 and relay.The remote control that data in pin D1 to the D8 pin of d type flip flop 2 and CLK pin meet CPU1 respectively exports control pin, it is omissive representation that output pin Q1 to the Q8 of d type flip flop 2 connects in photoelectric isolating circuit 4(Fig. 1 respectively, only illustrate Q1 to connect), photoelectric isolating circuit 4 connects relay 5 through driving circuit 6.
Control method of the present utility model comprises following measures:
1), adopt d type flip flop to do the input of prime remote signal, prevent the I/O mouth of CPU from shaking and cause relay misoperation to do.
2), adopt multiple control signal to carry out the final output of pilot relay: to only have when reset signal completes, namely reset signal be high level and YK_EN1 connects high level, YK_EN2 connects low level time d type flip flop can effectively export.
3), adopt multiple control signal according to the final output trip signal of correct sequencing change ability pilot relay.First YK_EN1 is connect high level when reset signal is stablized, YK_EN2 connects low level, then the D of d type flip flop is connect high level, the CLK finally by d type flip flop sends a rising edge just can send trip signal.The wrong any step of above three orders all can not send out trip signal.
In the utility model, basic logic is all realize by Sheffer stroke gate, and wherein D2A and D2D realizes rest-set flip-flop function, and the S input end of rest-set flip-flop is expanded by D2C and D4B, and the output terminal that D2B realizes rest-set flip-flop is anti-phase.Above five Sheffer stroke gates combine the main logic realized in the utility model.The output terminal of above logic receives the clear terminal of d type flip flop, and only have when RST signal and YK_EN1 signal are high level by truth table is known, when YK_EN2 is low level, the clear terminal side of d type flip flop is invalid, and trip signal can export.D input and the CLK input of YK_EN1, YK_EN2 and d type flip flop are controlled by system CPU, first YK_EN1 should be connect high level, YK_EN2 connects low level, then the D of d type flip flop is connect high level, the CLK finally by d type flip flop sends a rising edge finally could send trip signal.YK_EN1 meets GND, YK_EN2 through pull down resistor R4 and meets VCC through pull-up resistor R3 and ensure that the clear terminal (CLR) of the d type flip flop when system one powers on is low level, and trip signal cannot send.When reset chip action, reset signal is low level, and be low level by the clear terminal (CLR) of the known now d type flip flop of truth table, trip signal cannot send.System electrification, if I/O port sets high in CPU initialization procedure, when YK_EN1, YK_EN2 set high simultaneously, data keep, and the clear terminal (CLR) of d type flip flop is low level, and trip signal cannot send; If I/O port sets low in CPU initialization procedure, zeros data when YK_EN1, YK_EN set low simultaneously, the clear terminal (CLR) of d type flip flop is low level, and trip signal cannot send.
When in operational process, system power supply suffers accidental destruction abnormal, reset chip action exports reset signal, and be low level by the clear terminal (CLR) of the known now d type flip flop of truth table, trip signal cannot send.
In a case where, circuit of the present utility model all forbids tripping operation:
1, when powering on, YK_EN1 meets GND, YK_EN2 through pull down resistor R4 and meets VCC through pull-up resistor R3, and be low level by the clear terminal (CLR) of the known d type flip flop of the truth table in upper figure, trip signal is forbidden sending.
2, when reset chip action, reset signal is low level, and be low level by the clear terminal (CLR) of the known now d type flip flop of truth table, trip signal cannot send.Can avoid so electrification reset and system power supply abnormal time, send error tripping signal.
3, system initialization IO may be floating input (high-impedance state), may be set high, also may be set low.If floating input is then as [15], trip signal is forbidden sending; If set high, when YK_EN1, YK_EN2 all set high, data keep, and the clear terminal (CLR) of d type flip flop is still low level, and trip signal is forbidden sending; If set low, zeros data when YK_EN1, YK_EN2 all set low, the clear terminal (CLR) of d type flip flop is low level, and trip signal also cannot send.
When cancelling trip signal, first being set low by YK_EN1, then set high by YK_EN2, is low level by the clear terminal (CLR) of the known d type flip flop of truth table, and relay normally open contact disconnects, and trip signal is cancelled.Meanwhile the output register of d type flip flop is cleared, and when again sending out trip signal, again must operate according to original order completely, prevent trip signal cumulative error.
Claims (1)
1. one kind prevents the control circuit of remote control mistrip for specially becoming acquisition terminal, it comprises CPU(1), reset chip (7) and d type flip flop (2), it is characterized in that: also comprise the first Sheffer stroke gate D2C, the second Sheffer stroke gate D4B, the 3rd Sheffer stroke gate D2A, the 4th Sheffer stroke gate D2D and the 5th Sheffer stroke gate D2B, the 3rd Sheffer stroke gate D2A and the 4th Sheffer stroke gate D2D forms rest-set flip-flop circuit (3); Wherein, the RST pin of reset chip (7) meets CPU(1 respectively) reseting pin and the input pin of the first Sheffer stroke gate D2C, first Sheffer stroke gate D2C output pin connects two input pins of the second Sheffer stroke gate D4B, the output pin of the second Sheffer stroke gate D4B connects the input pin (R) of rest-set flip-flop circuit (3), the output pin of rest-set flip-flop circuit (3) connects two input pins of the 5th Sheffer stroke gate D2B, and the output pin of the 5th Sheffer stroke gate D2B connects the CLR pin of d type flip flop (2); CPU(1) I/O mouth First Line YK_EN1 connects another input pin of the first Sheffer stroke gate D2C and meets GND through pull down resistor R4; CPU(1) I/O mouth second line YK_EN2 connects an input pin of the 4th Sheffer stroke gate D2D and meets VCC through pull-up resistor R3; Data in pin D1 to D8 pin and the CLK pin of d type flip flop (2) meet CPU(1 respectively) remote control export control pin, output pin Q1 to the Q8 of d type flip flop (2) connects photoelectric isolating circuit (4) respectively, and photoelectric isolating circuit (4) connects relay (5) through driving circuit (6).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520405255.6U CN204695069U (en) | 2015-06-13 | 2015-06-13 | A kind of control circuit preventing remote control mistrip for specially becoming acquisition terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520405255.6U CN204695069U (en) | 2015-06-13 | 2015-06-13 | A kind of control circuit preventing remote control mistrip for specially becoming acquisition terminal |
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| CN204695069U true CN204695069U (en) | 2015-10-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201520405255.6U Withdrawn - After Issue CN204695069U (en) | 2015-06-13 | 2015-06-13 | A kind of control circuit preventing remote control mistrip for specially becoming acquisition terminal |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104932378A (en) * | 2015-06-13 | 2015-09-23 | 烟台东方威思顿电气股份有限公司(中国) | Control method and circuit for special transformer acquisition terminal to prevent remote control false tripping |
| CN110323712A (en) * | 2019-07-31 | 2019-10-11 | 西安天和防务技术股份有限公司 | Current potential keeps control method and overcurrent protection control method |
| CN113300701A (en) * | 2021-06-21 | 2021-08-24 | 深圳市誉娇诚科技有限公司 | Hardware anti-shake self-locking circuit capable of preventing malfunction of high-voltage relay |
-
2015
- 2015-06-13 CN CN201520405255.6U patent/CN204695069U/en not_active Withdrawn - After Issue
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104932378A (en) * | 2015-06-13 | 2015-09-23 | 烟台东方威思顿电气股份有限公司(中国) | Control method and circuit for special transformer acquisition terminal to prevent remote control false tripping |
| CN104932378B (en) * | 2015-06-13 | 2017-05-17 | 烟台东方威思顿电气有限公司 | Control method and circuit for special transformer acquisition terminal to prevent remote control false tripping |
| CN110323712A (en) * | 2019-07-31 | 2019-10-11 | 西安天和防务技术股份有限公司 | Current potential keeps control method and overcurrent protection control method |
| CN110323712B (en) * | 2019-07-31 | 2021-10-08 | 西安天和防务技术股份有限公司 | Potential holding control method and overcurrent protection control method |
| CN113300701A (en) * | 2021-06-21 | 2021-08-24 | 深圳市誉娇诚科技有限公司 | Hardware anti-shake self-locking circuit capable of preventing malfunction of high-voltage relay |
| CN113300701B (en) * | 2021-06-21 | 2024-05-28 | 深圳市誉娇诚科技有限公司 | Hardware anti-shake self-locking circuit capable of preventing misoperation of high-voltage relay |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20151007 Effective date of abandoning: 20170517 |