CN113300701A - Hardware anti-shake self-locking circuit capable of preventing malfunction of high-voltage relay - Google Patents
Hardware anti-shake self-locking circuit capable of preventing malfunction of high-voltage relay Download PDFInfo
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Abstract
The invention relates to the technical field of new energy automobile electric control, and discloses a hardware anti-shake self-locking circuit capable of preventing the malfunction of a high-voltage relay aiming at the defects of a logic control circuit used for a coil driving circuit of the high-voltage relay at present, which is characterized in that a RESET (RESET) pin and a bootstrap loader (BOOTLOADER) pin in a CPU (central processing unit) of a controller are incorporated into control sequence logic, an enable pin of a bus driving chip is not directly controlled by an I/O pin of the CPU, but is jointly output and controlled by the RESET pin, the bootstrap loader pin and the control enable pin in the CPU, a truth table is established to list a logic expression of an effective control signal, a logic gate circuit is designed, the potential safety hazard that the malfunction of the relay is possibly caused by the uncertain random state of the I/O pin level of the CPU during the initial power-on, RESET and bootstrap loader is thoroughly eliminated, the high-voltage relay can complete the specified action strictly according to the preset assumption and instruction under any condition.
Description
Technical Field
The invention relates to the technical field of new energy automobile electric control and the field of electric power system automation, in particular to a hardware anti-shake self-locking circuit capable of preventing misoperation of a high-voltage relay.
Background
At present, high-voltage relays are widely applied to high-voltage direct-current fields such as electric vehicles, hybrid electric vehicles, fuel cell vehicles, photovoltaic power generation, wind power generation, cloud server power supplies, battery charging and discharging systems, direct-current voltage power supply control and heavy-duty mechanical equipment. The working principle of the high-voltage relay is that a small voltage and a small current are used for controlling a large voltage and a large current, the inside of the high-voltage relay is divided into a coil control end and a load end, when a controller applies a driving voltage to the coil control end, the load end can be closed or disconnected, the load end of the high-voltage relay generally needs to bear the high voltage and the large current, the high-voltage relay plays the roles of breaking a circuit and penetrating the circuit in an electrical system, and the high-voltage relay belongs to an important safety device.
Whether a high voltage relay can perform a given action as intended depends primarily on the control logic of the controller and the drive circuit for the relay coil. At present, in the field of new energy electric automobiles, a high-voltage relay is generally driven by a special IC, the IC is divided into a high-side switch and a low-side switch, the high-side switch is positioned between a power supply and a load and belongs to positive control, the low-side switch is positioned between the load and the ground and belongs to negative control, and when high and low levels are applied to a control pin of the driving IC, the high-voltage relay can be driven to be switched on and off, as shown in figure 1; in the field of power system automation, a high-voltage relay is generally driven by a photoelectric coupler and a power relay, the driving circuit has strong loading capacity and can realize electrical isolation, and the driving circuit form of a high-side switch and a low-side switch can also be realized by performing different connection combinations on an output end A, an output end B, an output end C and an output end D outside, as shown in fig. 2.
However, both the high-side switch and the low-side switch driving IC, and the coil driving circuit of the photocoupler and the power relay, require the controller to issue control commands and "high" and "low" logic levels, fig. 3 illustrates a currently used logic control circuit by using a CPU chip STM32F107VCT6 of a semiconductor express (ST) and a bus driver chip SN74HC245NSR of a Texas Instrument (TI), wherein the bus driver chip SN74HC245NSR is used for improving the driving capability of I/O pins and lines of a CPU, the transmission direction of a control level signal is determined by a "DIR" pin, when the DIR pin is connected with high level, the transmission direction of the level signal is controlled from A0-A7 to B0-B7, the enable pin OE on the chip can control the transmission path of the level signal, the level signal can pass through when the low level is effective, and the output of the chip is in a high resistance state when the high level is effective.
Control pins GP-YK 0- "GP-YK 7" of a CPU chip STM32F107VCT6 are respectively connected TO input ends A0-A7 of a bus driving chip SN74HC245NSR, output level signals TO-YK 0- "TO-YK 7" of the bus driving chip SN74HC245NSR directly control input stages of coil driving circuits shown in the figures 1 and 2, an enable pin OE of the bus driving chip SN74HC245NSR is directly controlled by a control pin GP-EN of the CPU chip STM32F107VCT6, when a certain high-voltage relay needs TO be controlled, the level of the GP-EN pin is firstly horizontally lowered TO enable the bus driving chip, an I/O pin level signal corresponding TO the relay coil driving circuit is output, and the CPU outputs an 8-way logic level signal GP-YK 0- "GP-YK 7" TO control the 8-way high-voltage relay.
However, in practical applications, the logic control circuit has a significant potential safety hazard: during initial POWER-ON RESET, RESET and BOOTLOADER (POWER ON RESET), because the I/O pin level of the CPU is in an uncertain state, it can randomly present "high", "low", "high" and various combination level timing sequences thereof, such random level timing sequence signal will cause the high-voltage relay to be out of control and malfunction, the high-voltage relay will randomly generate the sound of continuous actuation and disconnection of the "snap" armature under these several states, and may cause the POWER and electrical safety accident in severe cases.
Disclosure of Invention
The invention mainly aims to provide a hardware anti-shake self-locking circuit capable of preventing the misoperation of a high-voltage relay, aiming at avoiding the misoperation of the high-voltage relay triggered when a CPU sends an error instruction during the initial power-on, reset and boot loading of a program, so that the high-voltage relay can strictly complete the specified actions according to the preset assumption and instruction under any condition.
In order TO achieve the above purpose, the hardware anti-shake self-locking circuit capable of preventing malfunction of a high-voltage relay provided by the invention comprises a controller CPU chip U2, a bus driving chip U3, a NAND gate logic chip U4A, a NAND gate logic chip U4B, a NAND gate logic chip U4C and a NAND gate logic chip U4D, wherein the controller CPU chip U2 is provided with a RESET pin RESET, a BOOT loader pin BOOT0, a control pin GP-EN and control pins GP-YK 0-GP-YK 7, the bus driving chip U3 is provided with an enable pin YK-EN, input pins A0-A7 and output pins TO-YK 0-TO-YK 7, the control pins GP-YK 0-GP-YK 7 of the controller CPU chip U2 are respectively and electrically connected with input pins A0-A7 of the bus driving chip U3, the output pins TO-YK 5953-TO-YK 7 of the bus driving chip U3 are respectively and electrically connected with an input stage circuit of the TO-YK driving circuit 868427, the RESET pin RESET and the control pin GP-EN of the controller CPU chip U2 are electrically connected to two input terminals of the nand gate logic chip U4A, two input terminals of the nand gate logic chip U4B are electrically connected to an output terminal of the nand gate logic chip U4A, two input terminals of the nand gate logic chip U4D are electrically connected to output terminals of the nand gate logic chip U4B and the nand gate logic chip U4C, the BOOT loader pin BOOT0 of the controller CPU chip U2 is electrically connected to two input terminals of the nand gate logic chip U4C, an output terminal of the nand gate logic chip U4D is electrically connected to the enable pin YK-EN of the bus driver chip U3, the control pin GP-EN is at a high level to allow the controller CPU chip U2 to output a control level signal, the controller CPU chip U2 enters a BOOT loader state when the BOOT loader pin BOOT loader 0 is at a high level, when the RESET pin RESET is at a low level, the controller CPU chip U2 enters a RESET state, and when the enable pin YK-EN is at a low level, the control level signal of the controller CPU chip U2 is allowed to be transmitted to the input stage of the relay coil driving circuit through the bus driving chip U3.
Further, the logic expression of the active control signals of the enable pin YK-EN, the control pin GP-EN, the RESET pin RESET, the BOOT loader pin BOOT0, and the enable pin YK-EN is in a low level state only when the control pin GP-EN, the RESET pin RESET, and the BOOT loader pin BOOT0 are in a high level state, and a low level state, respectively:
further, the nand gate logic chip U4A, the nand gate logic chip U4B, the nand gate logic chip U4C and the nand gate logic chip U4D all adopt a texas instrument SN74HC00DR nand gate logic chip.
Further, the controller CPU chip U2 employs an STM32F107VCT6 chip.
Further, the bus driver chip U3 adopts an SN74HC245NSR chip.
By adopting the technical scheme of the invention, the invention has the following beneficial effects:
1. the hardware anti-shake self-locking circuit provided by the invention brings a reset pin and a guide loading program pin in a CPU (central processing unit) of a controller into a control sequential logic, an enable pin of a bus driving chip is not directly controlled by an I/O (input/output) pin of the CPU, but is jointly output and controlled by the reset pin, the guide loading program pin and the control enable pin of the CPU, a truth table is established to list a logic expression of an effective control signal, a logic gate circuit is designed, the potential safety hazard that the relay possibly malfunctions due to the uncertain random state of the level of the I/O pin of the CPU during initial power-on, reset and guide loading programs is completely eliminated, and the high-voltage relay can strictly complete specified actions according to preset assumption and instructions under any condition;
2. the hardware anti-shake self-locking circuit provided by the invention has the advantages of simple circuit structure, low cost and high reliability.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic diagram of a coil driving circuit of a high-voltage relay commonly used in the field of new energy electric vehicles;
FIG. 2 is a schematic diagram of a coil driving circuit of a high-voltage relay commonly used in the field of power system automation;
FIG. 3 is a schematic diagram of a logic control circuit for controlling the coil driving circuit, which is schematically illustrated by the CPU chip STM32F107VCT6 and the bus driving chip SN74HC245 NSR;
FIG. 4 is a schematic circuit diagram of a hardware anti-shake self-locking circuit capable of preventing malfunction of a high-voltage relay according to the present invention;
FIG. 5 is a truth table of a hardware anti-shake self-locking circuit for preventing malfunction of a high-voltage relay according to the present invention;
fig. 6 is a logic diagram of a hardware anti-shake self-locking circuit capable of preventing malfunction of a high-voltage relay according to the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides a hardware anti-shake self-locking circuit capable of preventing misoperation of a high-voltage relay.
As shown in fig. 4 TO 6, in an embodiment of the present invention, the hardware anti-shake self-locking circuit capable of preventing malfunction of a high-voltage relay includes a controller CPU chip U2, a bus driver chip U3, a nand gate logic chip U4A, a nand gate logic chip U4B, a nand gate logic chip U4C, and a nand gate logic chip U4D, the controller CPU chip U2 includes a RESET pin RESET, a BOOT loader pin BOOT0, a control pin GP-EN, and control pins GP-YK 0-GP-YK 7, the bus driver chip U3 includes an enable pin YK-EN, input pins a 0-a 7, and output pins TO-YK 0-TO-YK 7, the control pins GP-YK 0-GP-YK 7 of the controller CPU chip U2 are respectively electrically connected TO input pins a 0-a 2 of the bus driver chip U3, and the output pins TO-YK 3 are respectively electrically connected TO input stage relay circuits of the input stage relay U-YK driving circuit through the input stage relay circuit through the input stage circuit through 0 The RESET pin RESET and the control pin GP-EN of the controller CPU chip U2 are electrically connected to two input terminals of the nand gate logic chip U4A, two input terminals of the nand gate logic chip U4B are electrically connected to an output terminal of the nand gate logic chip U4A, two input terminals of the nand gate logic chip U4D are electrically connected to output terminals of the nand gate logic chip U4B and the nand gate logic chip U4C, the BOOT loader pin BOOT0 of the controller CPU chip U2 is electrically connected to two input terminals of the nand gate logic chip U4C, an output terminal of the nand gate logic chip U4D is electrically connected to the enable pin YK-EN of the bus driver chip U3, the control pin GP-EN is high, the controller CPU chip U2 is allowed to output a control level signal, the controller CPU chip U2 enters a BOOT loader state when the BOOT loader pin BOOT loader 0 is high, when the RESET pin RESET is at a low level, the controller CPU chip U2 enters a RESET state, and when the enable pin YK-EN is at a low level, the control level signal of the controller CPU chip U2 is allowed to be transmitted to the input stage of the relay coil driving circuit through the bus driving chip U3.
Specifically, the logic control circuit of the controller may cause the action of false triggering of the high-voltage relay, mainly because the level state of the I/O pin of the controller CPU is an uncertain random state during the initial power-on, reset and boot loading procedures, and therefore, to ensure the reliable action of the high-voltage relay, the logic control circuit needs to shield the input of the I/O level of the controller CPU during the initial power-on, reset and boot loading procedures, and invalidate the I/O level during the period.
As shown in the truth table of fig. 5, three pin level states of a control pin GP-EN, a RESET pin RESET and a BOOT loader pin BOOT0 on the controller CPU chip U2 are drawn as inputs, and a level state of an enable pin YK-EN on the bus driver chip U3 is drawn as an output, because the control pin GP-EN and the BOOT loader pin BOOT0 on the controller CPU chip U2 are active at a high level, the RESET pin RESET is active at a low level, i.e., the CPU is allowed to output a control level when the control pin GP-EN is at a high level, the CPU enters the BOOT loader state when the BOOT loader pin BOOT0 is at a high level, and the CPU enters the RESET state when the RESET pin RESET is at a low level; and the enable pin YK-EN on the bus driver chip U3 is active low, i.e., the control level signal is allowed to pass and pass when the enable pin YK-EN is active low.
By enumerating all possible states between the input and the output, only when the level states of the control pin GP-EN, the RESET pin RESET and the BOOT loader pin BOOT0 are respectively high, high and low, the enable pin YK-EN is allowed to be effective, so that the control level of the CPU is output to the high-voltage relay coil driving circuit.
Therefore, the control pins GP-EN and the reset tube are listed according to the truth tableLogical expressions of the active control signals of the pin RESET, the BOOT loader pin BOOT0, and the enable pin YK-EN:
according to a logic expression, a NAND gate logic chip SN74HC00DR of a Texas Instrument (TI) is selected to design a hardware anti-shake self-locking circuit as shown in fig. 6, and the circuit output enable pin YK-EN is adopted to control a high-voltage relay coil driving circuit, so that the safety accident that the high-voltage relay is mistakenly triggered and mistakenly operated can be thoroughly avoided.
The hardware anti-shake self-locking circuit capable of avoiding the misoperation of the high-voltage relay is designed and considered according to the effective levels of the reset pin and the bootstrap loader pin of a specifically selected CPU chip and the effective level of the enable pin of a bus driving chip in the practical application process.
Specifically, the invention provides a hardware anti-shake self-locking circuit capable of avoiding the misoperation of a high-voltage relay aiming at the defects of the logic control circuit used for the coil driving circuit of the high-voltage relay at present, the circuit brings a RESET pin RESET and a guide loading program pin BOOTLOADER in a CPU into control sequential logic, an enable pin of a bus driving chip is not directly controlled by an I/O pin of the CPU, but is jointly output and controlled by a control pin GP-EN, the RESET pin RESET and a guide loading program pin BOOT0 in the CPU, effective control signal logic expressions of the control pin GP-EN, the RESET pin RESET, the guide loading program pin BOOT0 and the enable pin YK-EN are listed by establishing a truth table, and the logic gate circuit design thoroughly eliminates the possibility of leading the CPU chip of the I/O pin level of the controller due to uncertain random state of the I/O pin level during the initial power-on, RESET and guide loading program The high-voltage relay can complete the specified actions strictly according to the preset assumption and instructions under any condition due to the potential safety hazard of misoperation of the high-voltage relay, and the hardware anti-shake self-locking circuit provided by the invention has the advantages of simple circuit structure, low cost and high reliability, and has great practical value.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (5)
1. A hardware anti-shake self-locking circuit capable of preventing malfunction of a high-voltage relay is characterized by comprising a controller CPU chip U2, a bus driving chip U3, an NAND gate logic chip U4A, an NAND gate logic chip U4B, an NAND gate logic chip U4C and an NAND gate logic chip U4D, wherein the controller CPU chip U2 is provided with a RESET pin RESET, a BOOT loader pin BOOT0, a control pin GP-EN and control pins GP-YK 0-GP-YK 7, the bus driving chip U3 is provided with an enable pin YK-EN, input pins A0-A7 and output pins TO-YK 0-TO-YK 7, the control pins GP-YK 0-GP-YK 7 of the controller CPU chip U2 are respectively and electrically connected with the input pins A0-A7 of the bus driving chip U3, the output pins TO-YK 0-YK 8427 of the controller CPU chip U3 are respectively and electrically connected with an input stage of the high-voltage relay drive coil 7, the RESET pin RESET and the control pin GP-EN of the controller CPU chip U2 are electrically connected to two input terminals of the nand gate logic chip U4A, two input terminals of the nand gate logic chip U4B are electrically connected to an output terminal of the nand gate logic chip U4A, two input terminals of the nand gate logic chip U4D are electrically connected to output terminals of the nand gate logic chip U4B and the nand gate logic chip U4C, the BOOT loader pin BOOT0 of the controller CPU chip U2 is electrically connected to two input terminals of the nand gate logic chip U4C, an output terminal of the nand gate logic chip U4D is electrically connected to the enable pin YK-EN of the bus driver chip U3, the control pin GP-EN is at a high level to allow the controller CPU chip U2 to output a control level signal, the controller CPU chip U2 enters a BOOT loader state when the BOOT loader pin BOOT loader 0 is at a high level, when the RESET pin RESET is at a low level, the controller CPU chip U2 enters a RESET state, and when the enable pin YK-EN is at a low level, the control level signal of the controller CPU chip U2 is allowed to be transmitted to the input stage of the relay coil driving circuit through the bus driving chip U3.
2. The hardware anti-shake self-locking circuit capable of preventing malfunction of a high-voltage relay according to claim 1, wherein the enable pin YK-EN is in a low state only when the control pin GP-EN, the RESET pin RESET, and the BOOT loader pin BOOT0 are in a high state, and a low state, respectively, and the effective control signal logic expressions of the control pin GP-EN, the RESET pin RESET, the BOOT loader pin BOOT0, and the enable pin YK-EN are as follows:
3. the hardware anti-shake self-locking circuit capable of preventing malfunction of a high-voltage relay according to claim 1, wherein the nand gate logic chip U4A, the nand gate logic chip U4B, the nand gate logic chip U4C and the nand gate logic chip U4D are respectively SN74HC00DR nand gate logic chips of texas instruments.
4. The hardware anti-shake self-locking circuit capable of preventing the malfunction of the high-voltage relay according to claim 1, wherein the controller CPU chip U2 is STM32F107VCT6 chip.
5. The hardware anti-shake self-locking circuit capable of preventing malfunction of a high-voltage relay according to claim 1, wherein the bus driver chip U3 is SN74HC245NSR chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110689690.6A CN113300701B (en) | 2021-06-21 | 2021-06-21 | Hardware anti-shake self-locking circuit capable of preventing misoperation of high-voltage relay |
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| CN202110689690.6A CN113300701B (en) | 2021-06-21 | 2021-06-21 | Hardware anti-shake self-locking circuit capable of preventing misoperation of high-voltage relay |
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| CN113300701B CN113300701B (en) | 2024-05-28 |
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| US6172519B1 (en) * | 1997-12-18 | 2001-01-09 | Xilinx, Inc. | Bus-hold circuit having a defined state during set-up of an in-system programmable device |
| US20020075060A1 (en) * | 2000-12-15 | 2002-06-20 | Trenor Goodell | Translating switch circuit with disabling option |
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| CN209341951U (en) * | 2018-12-21 | 2019-09-03 | 西安北方捷瑞光电科技有限公司 | A kind of blasting bolt initiation control circuit |
| CN110389552A (en) * | 2019-07-25 | 2019-10-29 | 中国科学院西安光学精密机械研究所 | A scaling and power control circuit that eliminates power-up risks |
| CN217063697U (en) * | 2021-06-21 | 2022-07-26 | 深圳市誉娇诚科技有限公司 | Hardware anti-shake self-locking circuit capable of preventing malfunction of high-voltage relay |
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2021
- 2021-06-21 CN CN202110689690.6A patent/CN113300701B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4433357A (en) * | 1980-10-13 | 1984-02-21 | Matsushita Electric Works Ltd. | Drive circuit for a latching relay |
| US6172519B1 (en) * | 1997-12-18 | 2001-01-09 | Xilinx, Inc. | Bus-hold circuit having a defined state during set-up of an in-system programmable device |
| US20020075060A1 (en) * | 2000-12-15 | 2002-06-20 | Trenor Goodell | Translating switch circuit with disabling option |
| CN204695069U (en) * | 2015-06-13 | 2015-10-07 | 烟台东方威思顿电气股份有限公司 | A kind of control circuit preventing remote control mistrip for specially becoming acquisition terminal |
| CN205354958U (en) * | 2015-12-31 | 2016-06-29 | 东软集团股份有限公司 | Control signal protection device and control system of relay |
| CN209341951U (en) * | 2018-12-21 | 2019-09-03 | 西安北方捷瑞光电科技有限公司 | A kind of blasting bolt initiation control circuit |
| CN110389552A (en) * | 2019-07-25 | 2019-10-29 | 中国科学院西安光学精密机械研究所 | A scaling and power control circuit that eliminates power-up risks |
| CN217063697U (en) * | 2021-06-21 | 2022-07-26 | 深圳市誉娇诚科技有限公司 | Hardware anti-shake self-locking circuit capable of preventing malfunction of high-voltage relay |
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| CN113300701B (en) | 2024-05-28 |
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