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CN204650569U - 无线通信标签 - Google Patents

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Publication number
CN204650569U
CN204650569U CN201420873389.6U CN201420873389U CN204650569U CN 204650569 U CN204650569 U CN 204650569U CN 201420873389 U CN201420873389 U CN 201420873389U CN 204650569 U CN204650569 U CN 204650569U
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rfic element
wireless communication
antenna conductor
rfic
communication tag
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斋藤阳一
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G06K19/07752—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna using an interposer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07722—Physical layout of the record carrier the record carrier being multilayered, e.g. laminated sheets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07786—Antenna details the antenna being of the HF type, such as a dipole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy

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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Manufacturing & Machinery (AREA)
  • Details Of Aerials (AREA)

Abstract

本实用新型提供了一种无线通信标签。在具有挠性的基材膜(14)的上表面和下表面，分别形成天线导体(16)和补强层(18)。RFIC元件(12)被安装在基材膜(14)的上表面中央。这时，RFIC元件(12)上设置的2个I/O端子分别与形成天线导体(16)的蛇形图案(MP1和MP2)连接。俯视时，补强层(18)的轮廓呈圆形，RFIC元件(12)由补强层(18)的轮廓包围。另外，在RFIC元件(12)设置的2个I/O端子从基材膜(14)的上表面侧露出。RFIC元件(12)和天线导体(16)的连接部的破损能得到抑制，并且能容易地发现发生了破损。

Description

无线通信标签
技术领域
本实用新型涉及无线通信标签，无线通信标签包括：形成有天线导体的基材片材；以及具有与天线导体连接的连接端子、并搭载在基材片材上的RFIC元件。
背景技术
为了对制服或床单等的亚麻布进行管理，将RFID标签(无线通信标签)安装在亚麻布里。因此，例如特开2012-18629号公报中，公开了RFIC芯片被树脂覆盖的方法。通过该方法，能保护RFIC芯片不受清洗时的应力和溶剂的影响。
实用新型内容
实用新型所要解决的技术问题
然而，特开2012-18629号公报的方法中，由于覆盖部的高度高，手指对RFID标签触摸时容易产生异样感。另外，根据溶剂的种类不同，清洗时覆盖部可能会膨胀，这时RFIC芯片和天线的连接部恐怕发生破损。
因此，本实用新型的主要目的为提供一种无线通信标签，对连接部的状态能容易地进行确认的同时，连接部的破损能得到抑制。
解决技术问题所采用的技术方案
本实用新型的无线通信标签，包括：基材片材，该基材片材具有挠性；天线导体，该天线导体设置在基材片材上；补强层，该补强层设置在基材片材的一个主面上；以及RFIC元件，该RFIC元件具有与天线导体连接的连接端子，被搭载在基材片材的另一个主面上，补强层的轮廓在俯视下呈圆形，RFIC元件在俯视下被补强层的轮廓包围，连接端子从基材片材的另一个主面侧露出。
优选地，RFIC元件以UHF频带为通信频率，天线导体为偶极子型。
优选地，天线导体具有：在远离RFIC元件的方向上蛇行延伸的蛇形图案；以及与蛇形图案连接并朝向RFIC元件延伸的折返图案。
优选地，天线导体具有在俯视下将RFIC元件包围的环路图案。
优选地，补强层形成平板。
优选地，RFIC元件具有：RFIC芯片、搭载RFIC芯片的基板、以及将RFIC芯片密封的密封层。
优选地，无线通信标签被安装于亚麻布。
实用新型效果
由于RFIC元件在俯视下被补强层的轮廓包围，向RFIC元件和天线导体的连接部集中的应力被缓和。由此，连接部的破损被抑制。另外，由于补强层的轮廓在俯视下呈圆形，沿着基材片材的一个主面的外力在被施加到补强层上时，补强层对该外力的应力被分散。由此，补强层难以被剥离。进一步的，补强层形成在基材片材的一个主面上，RFIC元件的连接端子在另一个主面露出，因此能容易地发现连接部的破损。
本实用新型的上述目的、其他目的、特征和优点，通过参照附图进行的对以下实施例的详细说明能更加清楚。
附图说明
图1(A)是示出了该实施例的RFID标签从上方观察到的状态的一例的上表面图，图1(B)是示出了该实施例的RFID标签的I-I剖面的剖面图，图1(C)是示出了该实施例的RFID标签从下方观察到的状态的一例的下表面图。
图2是示出了图1所示的RFID标签适用的RFIC元件的构造的一例的图解图。
图3是示出了该实施例的RFID标签的等效电路的电路图。
图4(A)是示出了在基材膜形成天线导体的工序的图解图，图4(B)示出了在基材膜形成补强层的工序的图解图，图4(C)示出了在基材膜安装RFIC元件的工序的图解图。
图5(A)是示出了另一实施例的RFID标签从上方观察到的状态的一例的上表面图，图5(B)是示出了另一实施例的RFID标签的Ⅱ-Ⅱ剖面的剖面图，图5(C)是示出了另一实施例的RFID标签从下方观察到的状态的一例的下表面图。
图6是示出了另一实施例的RFID标签从上方观察到的状态的一例的上表面图。
图7是示出了再另一实施例的RFID标签的等效电路的电路图。
具体实施方式
本实用新型的无线通信标签，典型的是以UHF带为通信频率的RFID(Radio Frequency IDentification:无线射频识别技术)标签，被安装在需要清洗的制服或床单等的亚麻布中。
参照图1(A)～图1(C)、图2和图3，该实施例的RFID标签10包括长方体状的RFIC(Radio Frequency Integration Circuit:射频集成电路)元件12和带状的基材膜14。天线导体16和补强层18分别形成在基材膜14的上表面和下表面。为了使天线导体16发挥偶极子型天线的功能，RFIC元件12被安装在基材膜14的上表面中央。
另外，基材膜14是以基酰亚胺等树脂为材料，具有耐热性和挠性。另外，天线导体16是以Cu等金属为材料，具有耐热性和挠性。进一步的，补强层18优选比基材膜的弹性率更高(具体是杨氏弹性模量小)，并且和基材膜的紧密结合性高(基材膜为树脂则补强层也为树脂)，例如，以硅等树脂为材料，具有耐热性。
该实施例中，将基材膜14的长度方向、宽度方向和厚度方向分别设为X轴、Y轴和Z轴。以下，将朝向Z轴正方向的面设为“上表面”，将朝向Z轴负方向的面设为“下表面”，且将朝向与Z轴正交方向的面设为“侧面”。
由图2可知，RFIC元件12包括处理RFID信号的RFIC芯片12e和安装RFIC芯片12e的供电电路基板12c而构成。在RFIC元件12的下表面，设置有沿着X轴排列的2个I/O端子12a和12b。I/O端子12a和12b经由在供电电路基板12c上设置的供电电路12fct(参照图3)，与RFIC芯片12e的I/O端子12h和12i分别连接。
天线导体16具有蛇形图案MP1和蛇形图案MP2，蛇形图案MP1以比上表面中央略靠X轴正方向一侧的位置为基端向X轴正方向蛇行延伸，蛇形图案MP2以比上表面中央略靠X轴负方向一侧的位置为基端向X轴负方向蛇行延伸。蛇形图案MP1的前端到达X轴正方向端部附近的位置并且到达Y轴负方向端部附近的位置。另外，蛇形图案MP2的前端到达X轴负方向端部附近的位置并且到达Y轴负方向端部附近的位置。
天线导体16进一步具有折返图案RP1和折返图案RP2，折返图案RP1以蛇形图案MP1的前端的位置为基端向Y轴负方向延伸，折返图案RP2以蛇形图案MP2的前端的位置为基端向Y轴正方向延伸。折返图案RP1和RP2各自的前端为开放端。
补强层18在基材膜14的下表面的中央位置处形成为平板状。俯视时，补强层18的轮廓呈正圆。如上文所述，RFIC元件12被安装在基材膜14的上表面中央。补强层18的轮廓所形成的正圆的直径比RFIC元件12的宽度和长度都要大。由此，俯视时，RFIC元件12被补强层18的轮廓包围。
由图2可知，RFIC元件12的I/O端子12a和12b分别与蛇形图案MP1的基端和蛇形图案MP2的基端连接。I/O端子12a和蛇形图案MP1的连接是采用导电性的结合材料22，I/O端子12b和蛇形图案MP2的连接是采用导电性的结合材料24。另外，结合材料22和24以Ag或焊材为材料。
天线导体16还具有环状延伸的环路图案LP1，以连结蛇形图案MP1的基端的附近的位置和蛇形图案MP2的基端的附近的位置。俯视时，RFIC元件12由环路图案LP1包围。
参照图2，RFIC元件12的供电电路基板12c以陶瓷或树脂为材料形成为板状。安装在供电电路基板12c的上表面的RFIC芯片12e由树脂制的密封层12d密封。供电电路基板12c的侧面分别与X轴和Y轴正交，密封层12d的侧面与供电电路基板12c的侧面共面。
所述的I/O端子12a和12b在供电电路基板12c的下表面形成。另外，在供电电路基板12c的上表面形成I/O端子12f和12g。在RFIC芯片12e的下表面形成I/O端子12h和12i。I/O端子12h和12i分别通过未图示的导电性结合材料与I/O端子12f和12g连接。
RFID标签10的等效电路如图3所示。供电电路12fct设置在供电电路基板12c上。电容C1的一端与I/O端子12a连接，电容C1的另一端不仅与I/O端子12f还与I/O端子12h连接。另外，电容C2的一端与I/O端子12b连接，电容C2的另一端与电感L2的一端连接。电感L2的另一端不仅与I/O端子12g还和I/O端子12i连接。电感L1的一端与电容C1的另一端连接，电感L1的另一端与电容C2的另一端连接。
另外，电感L0是环路图案LP1的电感成分，电感L1和L2磁力结合。由此，可在宽频带下进行匹配。
接着，参照图4(A)～图4(C)，对RFIC元件12的制造方法进行说明。首先，在基材膜14的上表面，形成具有环路图案LP1、蛇形图案MP1～MP2和折返图案RP1～RP2的天线导体16。具体为，在基材膜14的上表面粘贴Cu箔等金属箔，基于薄膜加工对该金属箔进行图案化。
接着，在基材膜14的下表面的中央，封装具有耐热性的硅系树脂，由平板夹具压接。由此，平板状的补强层18被形成。形成的补强层18在俯视下有正圆形的轮廓。另外，轮廓的直径比RFIC元件12的宽度和长度都要大。
补强层18的形成结束后，由回流焊法在基材膜14的上表面中央安装RFIC元件12。具体为，将结合材料22和24印刷在I/O端子12a和12b上，将RFIC元件12装载在基材膜14的上表面中央，使得I/O端子12a和12b与蛇形图案MP1和MP2连接，并且用回流焊炉加热装载了RFIC元件12的基材膜14。这样，RFID标签10完成。
另外，将RFIC元件12装载在基材膜14的上表面中央时，在基材膜14的下表面中央形成的补强层18起到缓冲材料的作用。
从上述说明可知，在具有挠性的基材膜14的上表面和下表面，分别形成天线导体16和补强层18。RFIC元件12安装在基材膜14的上表面。这时，RFIC元件12的I/O端子12a和12b分别与形成天线导体16的蛇形图案MP1和MP2连接。俯视时，补强层18的轮廓呈圆形，RFIC元件12由补强层18的轮廓包围。另外，RFIC元件12的I/O端子12a和12b从基材膜14的上表面侧露出。
由于RFIC元件12在俯视下被补强层18的轮廓包围，向RFIC元件12和天线导体16的连接部集中的应力(清洗时产生的应力集中)被缓和。由此，连接部的破损被抑制。另外，由于补强层18的轮廓在俯视下呈圆形，沿着基材膜14的下表面的外力施加在补强层18上时，补强层18对该外力的应力被分散。由此，补强层18难以被剥离。进一步的，补强层18在基材膜14的下表面上形成，RFIC元件12的I/O端子12a和12b在基材膜14的上表面侧露出，因此能容易地发现连接部的破损。
另外，由于补强层18形成平板状，特别是其高度(厚度)比RFIC元件的高度小，所以手指触摸补强层18也难以产生异样感，并且从基材膜难以剥离。进一步地，在天线导体16的部分形成折返图案RP1和RP2，因此即使施加将基材膜14向X轴周向扭曲的外力，蛇形图案MP1或MP2也不会轻易被切断。另外，以俯视下包围RFIC元件12的方式形成环路图案LP1，从而向RFIC元件12和天线导体16的连接部集中的应力被缓和。
另外，供电电路基板12c以陶瓷或树脂为材料，RFIC芯片12e由密封层12d密封。因此，RFIC元件12虽小却牢固，能够充分耐受清洗等时产生的应力。
另外，该实施例中，俯视时的补强层18的轮廓呈正圆形状。然而，俯视时的补强层18的轮廓为椭圆形状也可。这种情况下，优选如图5(A)～图5(C)所示，椭圆的长轴沿X轴延伸。
另外，该实施例中，与蛇形图案MP1连续地形成了单个折返图案RP1，与蛇形图案MP2连续地形成了单个折返图案RP2。然而，也可以如图6所示，形成在Y轴方向包夹蛇形图案MP11的2个折返图案RP11和RP12，形成在Y轴方向包夹蛇形图案MP21的2个折返图案RP21和RP22。由此，会进一步增强相对于基材膜14在X轴周向扭曲的外力的耐受性。
进一步，本实施例中，在供电电路基板12c设置如图3所示的供电电路12fct,但也可省略供电电路fct。这种情况下，RFIC芯片和天线导体的阻抗也可由在天线导体侧的环路图案进行匹配，等效电路以如图7所示的方式构成。
虽然针对本实用新型的实施方式进行了说明，但应认为本次公开的实施方式在所有技术点上都仅仅只是举例说明而已，并不构成任何限制。本实用新型的范围以权利要求范围为准，包括与权利要求范围等同的意思和范围内的全部变更。
标号说明
10…RFID标签(无线通信标签)
12…RFIC元件
12a、12b…I/O端子(连接端子)
12c…供电电路基板(基板)
12d…密封层
12e…RFIC芯片
12fct…供电电路
14…基材膜(基材片材)
16…天线导体
18…补强层
MP1、MP2、MP11、MP21…蛇形图案
RP1、RP2、RP11、RP12、RP21、RP22…折返图案
LP1…环路图案

Claims (7)

1.无线通信标签，包括：
基材片材，该基材片材具有挠性；
天线导体，该天线导体设置在所述基材片材上；
补强层，该补强层设置在所述基材片材的一个主面上；以及
RFIC元件，该RFIC元件具有与所述天线导体连接的连接端子，被搭载在所述基材片材的另一主面上，
其特征在于，
所述补强层的轮廓在俯视下呈圆形，
所述RFIC元件在俯视下被所述补强层的轮廓包围，
所述连接端子从所述基材片层的另一主面侧露出。
2.如权利要求1所述的无线通信标签，其特征在于，所述RFIC元件以UHF频带为通信频率，所述天线导体为偶极子型。
3.如权利要求1或2所述的无线通信标签，其特征在于，所述天线导体具有：在远离所述RFIC元件的方向上蛇行延伸的蛇形图案；以及与所述蛇形图案连接并朝向所述RFIC元件延伸的折返图案。
4.如权利要求1或2所述的无线通信标签，其特征在于，所述天线导体具有在俯视下将所述RFIC元件包围的环路图案。
5.如权利要求1或2所述的无线通信标签，其特征在于，所述补强层形成平板。
6.如权利要求1或2所述的无线通信标签，其特征在于，所述RFIC元件具有：RFIC芯片、搭载所述RFIC芯片的基板、以及密封所述RFIC芯片的密封层。
7.如权利要求1或2所述的无线通信标签，其特征在于，所述无线通信标签被安装于亚麻布。
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