CN204424242U - The chip package structure of belt edge buffering and wafer level chip encapsulating structure - Google Patents
The chip package structure of belt edge buffering and wafer level chip encapsulating structure Download PDFInfo
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- CN204424242U CN204424242U CN201520096218.1U CN201520096218U CN204424242U CN 204424242 U CN204424242 U CN 204424242U CN 201520096218 U CN201520096218 U CN 201520096218U CN 204424242 U CN204424242 U CN 204424242U
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- chip
- package structure
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- belt edge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The utility model discloses chip package structure and the wafer level chip encapsulating structure of a kind of belt edge buffering, in this chip package structure, on the surface of substrate, the position of corresponding wafer predetermined cuts line defines groove, and in groove, be filled with the insulating material having and alleviate cutting effect of stress, because insulating material is positioned at wafer egress access site place, it can alleviate cutting stress when wafer cuts into single chips, therefore, the utility model chip can be avoided to produce at edge burst apart, warpage or crackle; And being separated of the wafer level chip encapsulating structure formed by the cutting of this chip package structure metal level that can effectively avoid thermal cycling test to cause and its underlying materials, improve the reliability of chip.
Description
Technical field
The utility model relates to a kind of semiconductor package structure, particularly relates to chip package structure and the wafer level chip encapsulating structure of a kind of belt edge buffering.
Background technology
At wafer level chip TSV (Through Silicon Via; silicon through hole) technology encapsulation in; usually a glass substrate or silicon substrate is bonded at the upper surface of chip and functional surfaces; injury-free or the pollution with functional section; do opening at the lower surface of chip and the lower surface of substrate again and expose weld pad, with metallic circuit, weld pad is electrically guided to chip lower surface.As depicted in figs. 1 and 2, known wafer level chip encapsulation process is: first, wafer and substrate 2 that one has multiple chip 1 are provided, chip usually has element region 10 and is positioned at the weld pad 4 of element region periphery, weld pad is positioned at the oxide layer 11 of chip, and be electrically connected with element region, substrate 2 is bonded in the upper surface of wafer by tack coat 9; Then, do the opening extended to upper surface at the lower surface of wafer, opening exposes weld pad 4; Then, in opening, do insulating barrier 5, metal wiring layer 6, overcoat 7, solder bump 8 etc., by the lower surface electrically guiding to wafer of weld pad, form chip package structure, as shown in Figure 1; Finally, along the predetermined cuts Linear cut of chip package structure, the multiple single chips of discrete one-tenth, namely forms wafer level chip encapsulating structure.
In above-mentioned encapsulation process, when chip package structure cutting forms single chips the most at last, the mode of usual employing machine cuts, namely by base material part and the substrate portion of machine cuts mode cut crystal, and when cutting substrate material is as silicon and glass, can stress be produced near cutting knife 12 feed, cause and collapse limit; Or causing warpage or micro-crack 13 (as shown in Figure 2), this warpage or micro-crack 13 are when subsequent thermal cyclic test, and deformation degree can be aggravated, and cause being separated of metal wiring layer and substrate the most at last, cause losing efficacy, have impact on the reliability of packaged chip.
Summary of the invention
In order to solve the problems of the technologies described above, the utility model proposes chip package structure and the wafer level chip encapsulating structure thereof of a kind of belt edge buffering, this chip package structure can alleviate cutting stress, avoid chip to produce in cut edge bursting apart, warpage or crackle, the layering of the metal level that the wafer level chip encapsulating structure formed by the cutting of this chip package structure can effectively avoid thermal cycling test to cause and its underlying materials, improves the reliability of chip.
The technical solution of the utility model is achieved in that
A kind of chip package structure of belt edge buffering, comprise the wafer with some chips, form predetermined cuts line between adjacent chips, the upper surface of each chip includes element region and is positioned at some weld pads of described element region periphery, and described weld pad is electrically connected described element region; Also comprise a substrate, described base plate bonding is in the upper surface of described wafer; Position relative with described predetermined cuts line on described substrate is formed with groove, is filled with the insulating material having and alleviate cutting effect of stress in described groove; The periphery of each chip is formed with the step of corresponding described weld pad, and described step connects the lower surface of this chip and described insulating material, and the bottom of described step enters described insulating material, and the surface of described step exposes described weld pad; Described step is formed with metal wiring layer, and weld pad is electrically guided to the lower surface of described chip by this metal wiring layer along the surface of step.
As further improvement of the utility model, described step comprises the first stage and the second stage, described second stage is lower than described first stage, first stage comprises bottom the first side wall and first, second stage comprises bottom the second sidewall and second, connect in turn bottom described the first side wall, described first, bottom described second sidewall, described second, and described the first side wall connects the lower surface of described chip, bottom described second, enter described insulating material.
As further improvement of the utility model, described groove is run through the strip groove of described substrate or be formed at square groove, the arc groove of substrate local.
As further improvement of the utility model, described groove be square groove or arc groove time, a weld pad of its corresponding described chip or multiple adjacent welding-pad.
As further improvement of the utility model, described insulating material is negative photoresist.
As further improvement of the utility model, the sidewall of described groove or described step vertical with the upper surface of described chip or have certain angle.
As further improvement of the utility model, between the base material of described metal wiring layer and described chip, be equipped with insulating barrier.
As further improvement of the utility model, described metal wiring layer is provided with overcoat, this overcoat is formed with opening in the default pad locations of metal wiring layer, is implanted with solder bump in described opening.
As further improvement of the utility model, the metal wiring layer bottom described step does not extend to the edge of corresponding chip, and described insulating material and the described overcoat of edge combine.
A wafer level chip encapsulating structure for belt edge buffering, described wafer level chip encapsulating structure is the encapsulating structure of arbitrary single chips that the chip package structure of described belt edge buffering is formed after predetermined cuts Linear cut.
The beneficial effects of the utility model are: the chip package structure that the utility model provides a kind of belt edge to cushion and wafer level chip encapsulating structure, in this chip package structure, at the edge of substrate, the position of corresponding wafer predetermined cuts line defines groove, and in groove, be filled with the insulating material having and alleviate cutting effect of stress, because insulating material is positioned at wafer egress access site place, it can alleviate cutting stress when wafer cuts into single chips, therefore, the utility model chip can be avoided to produce at edge burst apart, warpage or crackle; And being separated of the wafer level chip encapsulating structure formed by the cutting of this chip package structure metal level that can effectively avoid thermal cycling test to cause and its underlying materials, improve the reliability of chip.Preferably, metal wiring layer along chip edge step by weld pad electrically guide to substrate lower surface while, metal wiring layer extends to insulating material, and not extending to the edge of corresponding chip, insulating material and the overcoat of edge combine, like this, relative to the combination of overcoat and baseplate material, it has better in conjunction with effect, can avoid the layering of overcoat further, improves the reliability of chip.
Accompanying drawing explanation
Fig. 1 is known chip package structure cutting position schematic diagram;
Fig. 2 is A place structure for amplifying schematic diagram in Fig. 1;
Fig. 3 is cutting position schematic diagram after upper wafer surface adhesive base plate in the utility model encapsulation process;
Fig. 4 is that in the utility model encapsulation process, wafer forms cutting position schematic diagram after step;
Fig. 5 is cutting position schematic diagram after the utility model formation chip package structure;
Fig. 6 is B place structure for amplifying schematic diagram in Fig. 5;
Fig. 7 is a structural representation of wafer level chip encapsulating structure in the utility model;
Fig. 8 is another structural representation of wafer level chip encapsulating structure in the utility model;
Fig. 9 is the another structural representation of wafer level chip encapsulating structure in the utility model;
Figure 10 is a structural representation of utility model further groove;
Figure 11 is another structural representation of utility model further groove;
Figure 12 is the another structural representation of utility model further groove.
By reference to the accompanying drawings, make the following instructions:
1---chip 2---substrate
3---insulating material 4---weld pad
5---insulating barrier 6---metal wiring layer
7---overcoat 8---solder bump
9---tack coat 10---element region
11---oxide layer 12---blade
13---micro-crack 14---step
141---the first side walls 142---are bottom first
143---second sidewalls 144---are bottom second
15---predetermined cuts line
Embodiment
For enabling the utility model more become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.For convenience of description, in the structure of embodiment accompanying drawing, each part does not press normal rates convergent-divergent, therefore does not represent the actual relative size of each structure in embodiment.
As shown in Fig. 3, Fig. 4, Fig. 5 and Fig. 6, a kind of chip package structure of belt edge buffering, comprise the wafer with some chips 1, predetermined cuts line 15 is formed between adjacent chips, the upper surface of each chip includes element region 10 and is positioned at some weld pads 4 of described element region periphery, described weld pad is electrically connected described element region, and be specially the upper surface that element region is positioned at the substrate of chip, weld pad is positioned at the oxide layer of chip; Also comprise a substrate 2, described base plate bonding is in the upper surface of described wafer; Position relative with described predetermined cuts line on described substrate is formed with groove, is filled with the insulating material 3 having and alleviate cutting effect of stress in described groove; The periphery of each chip is formed with the step 14 of corresponding described weld pad, and described step connects the lower surface of this chip and described insulating material, and the bottom of described step enters described insulating material, and the surface of described step exposes described weld pad; Described step is formed with metal wiring layer 6, weld pad is electrically guided to the lower surface of described chip by this metal wiring layer along the surface of step.Wherein, chip can be MEMS (micro electro mechanical system) (Micro ElectroMechanical System, MEMS), physics sensing device (Physical Sensor) etc., but chip type is not limited thereto, the substrate of chip can be silicon base, the GaAs based end etc.Substrate can be silicon substrate or glass substrate.
If MEMS chip, substrate and substrate also can be formed with cavity body structure in element region position, for simplifying, not shown in FIG..
In above-mentioned chip package structure, form groove by the position of wafer predetermined cuts line corresponding at the edge of substrate, and in groove, fill the insulating material having and alleviate cutting effect of stress, chip can be avoided to produce at edge burst apart, warpage or crackle; This is because arrange insulating material at the position being positioned at the feed of wafer egress, by the alleviation cutting effect of stress that insulating material has, cutting stress when wafer cuts into single chips can be alleviated, thus reach and avoid chip to produce at Waffer edge bursting apart or the object of crackle.Preferably, described insulating material is negative photoresist, and negative photoresist is by photoetching process, and fill and enter in the groove of substrate, negative photoresist can fill up groove, also extends to recessed circumferential surface.
The position of insulating material is determined by the shape of groove, the formation method of groove comprises dry etching or machine cuts or sandblasting, optionally, see Figure 10,11,12, described groove is run through the strip groove of described substrate or be formed at square groove, the arc groove of substrate local.As the first preferred groove structure, groove is the strip groove running through substrate, and strip groove can all weld pads at simultaneously corresponding adjacent die edge place, see Figure 10.As the preferred groove structure of the second, groove is the multiple square grooves being formed at substrate local, and the corresponding one or more adjacent weld pad of each square groove, see Figure 11.As the third preferred groove structure, groove is the circular groove being formed at substrate local, and the corresponding one or more adjacent weld pad of each circular groove, see Figure 12.
Optionally, substrate is bonded in the upper surface of wafer by tack coat 9; Namely the one side of substrate contacts with the upper surface (oxide layer) of chip, as shown in Figure 3.
Preferably, described step comprises the first stage and the second stage, described second stage is lower than described first stage, first stage to comprise bottom the first side wall 141 and first 142, second stage to comprise bottom the second sidewall 143 and second 144, connect in turn, and described the first side wall connects the lower surface of described chip bottom described the first side wall, described first, bottom described second sidewall, described second, described insulating material is entered, as shown in Figure 4 bottom described second.In wafer package process, the method forming step 14 is: form opening in dry etching mode in the position of parallel Cutting Road, this opening extends from wafer lower surface to its upper surface.The insulating material 3 below weld pad 4 sidewall of open bottom and weld pad is exposed by machine cuts mode, follow-up along line of cut cutting, form the ledge structure of chip edge.
Optionally, the sidewall of described groove or described step vertical with the upper surface of described chip or have certain angle.As a kind of preferred embodiment, see Fig. 7, mesa sidewall and substrate surface have certain angle, the vertical upper surface of substrate of recess sidewall; As another kind of preferred embodiment, see Fig. 8, the sidewall of step and half groove all has certain angle with substrate surface.
Optionally, insulating barrier 5 is equipped with between the base material of described metal wiring layer and described chip.
Optionally, described metal wiring layer is provided with overcoat 7, this overcoat is formed with opening in the default pad locations of metal wiring layer, is implanted with solder bump 8 in described opening.
Optionally, see Fig. 9, the metal wiring layer bottom described step does not extend to the edge of corresponding chip, and described insulating material and the described overcoat of edge combine.
A wafer level chip encapsulating structure for belt edge buffering, the encapsulating structure of its arbitrary single chips formed after predetermined cuts Linear cut for the chip package structure of belt edge buffering.See Fig. 7, Fig. 8 and Fig. 9, the wafer level chip encapsulating structure of this belt edge buffering comprises chip, and the upper surface of chip includes element region and is positioned at some weld pads of element region periphery, and weld pad electrical connection element district; Also comprise substrate (being formed by monoblock substrate cut), base plate bonding is in the upper surface of chip; Substrate is formed with half groove (being formed by the cutting of whole groove), in half groove, is filled with the insulating material (being formed by the monoblock insulating material be filled in groove cutting) having and alleviate cutting effect of stress; The periphery edge place of chip is formed with step, and step connects lower surface and the insulating material of chip, and the bottom of step extends into insulating material, and the surface of step exposes part of solder pads; Step is formed with metal wiring layer, weld pad is electrically guided to the lower surface of chip by this metal wiring layer along the surface of step, insulating barrier 5 is equipped with between the base material of metal wiring layer and described chip, described metal wiring layer is provided with overcoat 7, this overcoat is formed with opening in the default pad locations of metal wiring layer, is implanted with solder bump in described opening; Preferably, see Fig. 9, the metal wiring layer bottom step does not extend to the edge of chip, and insulating material and the overcoat of edge combine.
The wafer level chip encapsulating structure cushioned due to this belt edge is that the chip package structure cutting cushioned by belt edge is formed, therefore, the position that in wafer level chip encapsulating structure, distance metal wiring layer is nearer can not produce burst apart, warpage or crackle, deformation degree aggravation when also would not cause subsequent thermal cyclic test, can avoid causing being separated of metal wiring layer and substrate, improve the reliability of packaged chip.Preferably, metal wiring layer along chip edge step by weld pad electrically guide to substrate lower surface while, metal wiring layer extends to insulating material, and not extending to the edge of corresponding chip, insulating material and the overcoat of edge combine, like this, relative to the combination of overcoat and baseplate material, it has better in conjunction with effect, can avoid the layering of overcoat further, improves the reliability of chip.
Above embodiment is with reference to accompanying drawing, is described in detail to preferred embodiment of the present utility model.Those skilled in the art by carrying out amendment on various forms or change to above-described embodiment, but when not deviating from essence of the present utility model, drops within protection range of the present utility model.
Claims (10)
1. the chip package structure of a belt edge buffering, comprise the wafer with some chips (1), predetermined cuts line (15) is formed between adjacent chips, the upper surface of each chip includes element region (10) and is positioned at some weld pads (4) of described element region periphery, and described weld pad is electrically connected described element region; It is characterized in that, also comprise a substrate (2), described base plate bonding is in the upper surface of described wafer; Position relative with described predetermined cuts line on described substrate is formed with groove, is filled with the insulating material (3) having and alleviate cutting effect of stress in described groove; The periphery of each chip is formed with the step (14) of corresponding described weld pad, and described step connects the lower surface of this chip and described insulating material, and the bottom of described step enters described insulating material, and the surface of described step exposes described weld pad; Described step is formed with metal wiring layer (6), weld pad is electrically guided to the lower surface of described chip by this metal wiring layer along the surface of step.
2. the chip package structure of belt edge buffering according to claim 1, it is characterized in that: described step comprises the first stage and the second stage, described second stage is lower than described first stage, first stage comprises bottom the first side wall (141) and first (142), second stage comprises bottom the second sidewall (143) and second (144), described the first side wall, bottom described first, described second sidewall, connect in turn bottom described second, and described the first side wall connects the lower surface of described chip, described insulating material is entered bottom described second.
3. the chip package structure of belt edge buffering according to claim 1, is characterized in that: described groove is run through the strip groove of described substrate or be formed at square groove, the arc groove of substrate local.
4. the chip package structure of belt edge according to claim 3 buffering, is characterized in that: described groove be square groove or arc groove time, a weld pad of its corresponding described chip or multiple adjacent welding-pad.
5. the chip package structure of belt edge buffering according to claim 1, is characterized in that: described insulating material is negative photoresist.
6. the chip package structure of belt edge according to claim 1 buffering, is characterized in that: the sidewall of described groove or described step vertical with the upper surface of described chip or have certain angle.
7. the chip package structure of belt edge buffering according to claim 1, its feature is: be equipped with insulating barrier (5) between the base material of described metal wiring layer and described chip.
8. the chip package structure of belt edge buffering according to claim 1, its feature is: described metal wiring layer is provided with overcoat (7), this overcoat is formed with opening in the default pad locations of metal wiring layer, is implanted with solder bump (8) in described opening.
9. the chip package structure of belt edge buffering according to claim 8, its feature is: the metal wiring layer bottom described step does not extend to the edge of corresponding chip, and described insulating material and the described overcoat of edge combine.
10. the wafer level chip encapsulating structure of a belt edge buffering, it is characterized in that, the encapsulating structure of arbitrary single chips that the chip package structure that described wafer level chip encapsulating structure is the belt edge buffering described in any one of claim 1 to 9 is formed after predetermined cuts Linear cut.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105621344A (en) * | 2016-03-04 | 2016-06-01 | 华天科技（昆山）电子有限公司 | MEMS (Micro-Electromechanical System) hermetic packaging structure and method |
| CN108511409A (en) * | 2018-04-19 | 2018-09-07 | 苏州晶方半导体科技股份有限公司 | The wafer-level packaging method and its encapsulating structure of semiconductor chip |
| CN109052923A (en) * | 2018-08-02 | 2018-12-21 | 京东方科技集团股份有限公司 | Motherboard to be cut and its cutting backfill and cutter unit forming method, cutter device |
| CN110993495A (en) * | 2019-12-18 | 2020-04-10 | 苏州晶方半导体科技股份有限公司 | Chip preparation method and wafer level packaging chip |
| CN111293047A (en) * | 2018-11-21 | 2020-06-16 | 长鑫存储技术有限公司 | Wafer, semiconductor device and manufacturing method thereof |
| CN111933586A (en) * | 2019-05-13 | 2020-11-13 | 中芯长电半导体（江阴）有限公司 | Wafer-level chip packaging structure and preparation method |
| CN114203558A (en) * | 2020-09-17 | 2022-03-18 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and carrier plate used for semiconductor packaging method |
| CN115280489A (en) * | 2020-07-15 | 2022-11-01 | Pep创新私人有限公司 | Semiconductor device having buffer layer |
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2015
- 2015-02-10 CN CN201520096218.1U patent/CN204424242U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105621344A (en) * | 2016-03-04 | 2016-06-01 | 华天科技（昆山）电子有限公司 | MEMS (Micro-Electromechanical System) hermetic packaging structure and method |
| CN108511409A (en) * | 2018-04-19 | 2018-09-07 | 苏州晶方半导体科技股份有限公司 | The wafer-level packaging method and its encapsulating structure of semiconductor chip |
| CN109052923A (en) * | 2018-08-02 | 2018-12-21 | 京东方科技集团股份有限公司 | Motherboard to be cut and its cutting backfill and cutter unit forming method, cutter device |
| CN111293047A (en) * | 2018-11-21 | 2020-06-16 | 长鑫存储技术有限公司 | Wafer, semiconductor device and manufacturing method thereof |
| CN111933586A (en) * | 2019-05-13 | 2020-11-13 | 中芯长电半导体（江阴）有限公司 | Wafer-level chip packaging structure and preparation method |
| CN110993495A (en) * | 2019-12-18 | 2020-04-10 | 苏州晶方半导体科技股份有限公司 | Chip preparation method and wafer level packaging chip |
| CN110993495B (en) * | 2019-12-18 | 2023-09-08 | 苏州晶方半导体科技股份有限公司 | Chip preparation method and wafer-level packaging chip |
| CN115280489A (en) * | 2020-07-15 | 2022-11-01 | Pep创新私人有限公司 | Semiconductor device having buffer layer |
| CN114203558A (en) * | 2020-09-17 | 2022-03-18 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and carrier plate used for semiconductor packaging method |
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