CN204130536U - A kind of array base palte and display unit - Google Patents
A kind of array base palte and display unit Download PDFInfo
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- CN204130536U CN204130536U CN201420613618.0U CN201420613618U CN204130536U CN 204130536 U CN204130536 U CN 204130536U CN 201420613618 U CN201420613618 U CN 201420613618U CN 204130536 U CN204130536 U CN 204130536U
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Abstract
The utility model provides a kind of array base palte and display unit thereof, wherein array base palte comprises the active layer, gate insulation layer and the gate electrode layer that set gradually on substrate, and described active layer is disposed with the first heavily doped region, the first doped regions, the first undoped region, the second doped regions, the second undoped region, the 3rd doped regions, the second heavily doped region in the horizontal direction.Described display unit comprises above-mentioned array base palte.Thus can under the prerequisite guaranteeing aperture opening ratio, the heat effectively reducing low-temperature polysilicon film transistor produces and effectively suppresses the leakage current of polycrystalline SiTFT.
Description
Technical field
The utility model relates to Display Technique field, specifically can relate to a kind of array base palte and display unit.
Background technology
Low temperature polycrystalline silicon (LTPS:Low Temperature Poly-Silicon) technology is thin-film transistor (TFT:Thin Film Transistor) the display unit manufacturing process of a new generation, LTPS TFT display unit has the response time faster, higher resolution, therefore has better picture display quality.Using LTPS technology when forming the circuit of display unit periphery, integrated circuit (IC) can be reduced, simplify the periphery of display unit, and then realize narrow frame technology.
Although LTPS technology is greatly developed, LTPS TFT still exists leakage current (leakage Current) cannot effectively suppress and produce the excessive problem of heat.Wherein, it is that electric field is comparatively large in the horizontal direction due to LTPS TFT that LTPS TFT produces the excessive problem of heat, and electronics, under the effect of electric field acceleration, causes ionization by collision to cause.LTPS TFT generation heat is crossed conference and is caused the impact of following several respects: too much thermal conductance causes lattice scattering, causes as sodium metal diffuses to active area in glass substrate, thus affects the threshold voltage (Vth) of LTPS TFT; Produce negative resistance phenomenon in saturation region, carrier mobility and On current are declined; Long-term impact can cause LTPS TFT characteristic degradation, affects product quality.
Found by research, at the vibrational power flow of the employing lightly doped drain, active area (LDD:Lightly Doped Drain) of LTPS TFT, effectively can reduce the generation of LTPS TFT heat, and the leakage current of LTPS TFT is also along with reduction.This is because, because the resistance of LDD is relatively high, be equivalent to the resistance that a resistance of having connected is larger, because this reducing the electric field strength of LTPS TFT horizontal direction, improve LTPS TFT electric field distribution in channel, thus reduce the probability of the hot carrier of the ionization by collision generation that electric field acceleration causes, effectively suppress the generation of leakage current simultaneously.
But prior art exists a technical contradiction point, namely when LDD length is too short, LDD loses the effect reducing heat generation and suppress leakage current, and when LDD is long, increases the consumption of LTPS TFT power, and have impact on the aperture opening ratio of display unit.
Utility model content
The utility model provides a kind of array base palte and display unit, thus can under the prerequisite guaranteeing aperture opening ratio, and the heat effectively reducing low-temperature polysilicon film transistor produces and effectively suppresses the leakage current of polycrystalline SiTFT.
The utility model provides scheme as follows:
The utility model embodiment provides a kind of array base palte, comprising:
The active layer set gradually on substrate, gate insulation layer and gate electrode layer, wherein, described active layer is disposed with the first heavily doped region, the first doped regions, the first undoped region, the second doped regions, the second undoped region, the 3rd doped regions, the second heavily doped region in the horizontal direction.
Preferably, described second doped regions is arranged at the centre position in described active layer horizontal direction.
Preferably, the view field of pattern on array base palte of described gate electrode layer, is covered in described first doped regions, the first undoped region, the second doped regions, the second undoped region, the 3rd view field of doped regions on array base palte.
Preferably, described gate electrode layer comprises first grid electrode pattern and second gate electrode pattern;
The described view field of first grid electrode pattern on array base palte, covers the described view field of the first undoped region on array base palte;
The described view field of second gate electrode pattern on array base palte, covers the described view field of the second undoped region on array base palte.
Preferably, described array base palte also comprises:
Be arranged at the first insulating barrier between substrate and active layer.
Preferably, described array base palte also comprises:
Be arranged at the second insulating barrier on described gate insulation layer and gate electrode layer;
Be arranged at the source-drain electrode layer on described second insulating barrier, described source-drain electrode layer comprises source electrode line and electric leakage polar curve, wherein, described source electrode line is electrically connected with described first heavily doped region by the first via hole run through in described second insulating barrier and gate insulation layer, and described electric leakage polar curve is electrically connected with described second heavily doped region by the second via hole running through described second insulating barrier and gate insulation layer;
Be arranged at the passivation layer on described source-drain electrode layer;
Be arranged at the pixel electrode layer on described passivation layer, described pixel electrode layer is electrically connected with described electric leakage polar curve by the 3rd via hole be arranged in described passivation layer.
Preferably, described array base palte also comprises:
Be arranged at the protective layer on described passivation layer and pixel electrode layer;
Be arranged at the common electrode layer on described protective layer.
Preferably, the length of described first doped regions, the second doped regions and the 3rd doped regions is 1 to 3 micron, and doped regions ion implantation concentration is 5 to 30ions/ centimetre
2.
The utility model embodiment still provides a kind of display unit, and this display unit specifically can comprise the array base palte that above-mentioned the utility model embodiment provides.
As can be seen from the above, the array base palte that the utility model provides and display unit, by on the substrate of array base palte, set gradually active layer, gate insulation layer and gate electrode layer, described active layer is disposed with the first heavily doped region, the first doped regions, the first undoped region, the second doped regions, the second undoped region, the 3rd doped regions, the second heavily doped region in the horizontal direction.Thus can under the prerequisite guaranteeing aperture opening ratio, the heat effectively reducing low-temperature polysilicon film transistor produces and effectively suppresses the leakage current of polycrystalline SiTFT.
Accompanying drawing explanation
The array base-plate structure schematic diagram one that Fig. 1 provides for the utility model embodiment;
The array base-plate structure schematic diagram two that Fig. 2 provides for the utility model embodiment;
The array base-plate structure schematic diagram three that Fig. 3 provides for the utility model embodiment;
The array substrate manufacturing method schematic flow sheet one that Fig. 4 provides for the utility model embodiment;
The array substrate manufacturing method schematic flow sheet two that Fig. 5 provides for the utility model embodiment;
Array base palte view one in the array substrate manufacturing method implementation procedure that Fig. 6 provides for the utility model embodiment;
Array base palte view two in the array substrate manufacturing method implementation procedure that Fig. 7 provides for the utility model embodiment;
Array base palte view three in the array substrate manufacturing method implementation procedure that Fig. 8 provides for the utility model embodiment;
Array base palte view four in the array substrate manufacturing method implementation procedure that Fig. 9 provides for the utility model embodiment;
Array base palte view five in the array substrate manufacturing method implementation procedure that Figure 10 provides for the utility model embodiment;
The array substrate manufacturing method schematic flow sheet three that Figure 11 provides for the utility model embodiment;
Array base palte view six in the array substrate manufacturing method implementation procedure that Figure 12 provides for the utility model embodiment;
Array base palte view seven in the array substrate manufacturing method implementation procedure that Figure 13 provides for the utility model embodiment;
Array base palte view eight in the array substrate manufacturing method implementation procedure that Figure 14 provides for the utility model embodiment;
Array base palte view nine in the array substrate manufacturing method implementation procedure that Figure 15 provides for the utility model embodiment.
Embodiment
For making the object of the utility model embodiment, technical scheme and advantage clearly, below in conjunction with the accompanying drawing of the utility model embodiment, the technical scheme of the utility model embodiment is clearly and completely described.Obviously, described embodiment is a part of embodiment of the present utility model, instead of whole embodiments.Based on described embodiment of the present utility model, the every other embodiment that those of ordinary skill in the art obtain, all belongs to the scope of the utility model protection.
Unless otherwise defined, technical term used herein or scientific terminology should be in field belonging to the utility model the ordinary meaning that the personage with general technical ability understands." first ", " second " that use in the utility model patent application specification and claims and similar word do not represent any order, quantity or importance, and are only used to distinguish different parts.Equally, the similar word such as " " or " " does not represent restricted number yet, but represents to there is at least one." connection " or " being connected " etc. similar word be not defined in physics or the connection of machinery, no matter but can comprise electrical connection, be direct or indirectly." on ", D score, "left", "right" etc. only for representing relative position relation, when be described object absolute position change after, then this relative position relation also correspondingly changes.
The utility model embodiment provides a kind of array base palte, and as shown in Figure 1, this array base palte specifically can comprise:
The active layer set gradually on substrate 1, gate insulation layer 3 and gate electrode layer 4, wherein, active layer is disposed with the first undoped region 23, second doped regions 24, second, doped regions 22, first, heavily doped region 21, first undoped region 25, the 3rd heavily doped region 27, doped regions 26, second in the horizontal direction.
The array base palte that the utility model embodiment provides, by linking up centre and the both sides predetermined position in region at thin-film transistor, multiple doped regions with high value is set, thus the acceleration distance of electronics under electric field action can be reduced, thus reducing the probability of the kinetic energy of electronics and the hot carrier of ionization by collision generation, the heat that effectively can reduce low-temperature polysilicon film transistor produces and effectively suppresses leakage current.
In the utility model embodiment, as shown in Figure 1, second doped regions 24 specifically can be arranged at active layer centre position in the horizontal direction, like this, when electronics is in two undoped region transmitting procedures, through the second doped regions 24, thus will inevitably can reduce speed and the kinetic energy of electric transmission, to realize the object reducing heat and suppress leakage current.And in other embodiments of the utility model, the second doped regions 24 also can be arranged at the predetermined position near the first doped regions 22 or the 3rd doped regions 26.
In the utility model embodiment, can based on array base palte channel region electric field strength, or the characteristic requirements such as the ON state current (Ion) of thin-film transistor (TFT) (such as low-temperature polysilicon film transistor LTPS TFT) or off-state current (Ioff), the length of doped regions is controlled, thus under the prerequisite meeting territory, thin-film transistor channel region property requirements, the lifting of aperture opening ratio can be realized.
In the utility model embodiment, also by the adjustment to ion implantation kind and concentration, thus realize the control to doped regions length.
Channel region structure in the array base palte that the utility model embodiment provides both can be NMOS structure, also can be PMOS structure etc., for convenience of explanation, during subsequent descriptions, to adopt NMOS, the array base-plate structure that the utility model embodiment provides is described in detail.
The array base palte that the utility model embodiment provides, specifically can be single grid-type array base palte, also can be double grid type array base palte.
When the array base palte that the utility model embodiment provides is single grid-type array base palte, as shown in the figures 1 and 2, be positioned at pattern and the grid of gate electrode layer 4, view field on array base palte, the first undoped region 23, second doped regions 24, second, doped regions 22, first undoped region 25, the 3rd view field of doped regions 26 on array base palte can be covered in, thus while realizing low-leakage current, there is graphics area little, be conducive to the design degree of improving product, realize higher resolution (PPI).
When the array base palte that the utility model embodiment provides is double grid type array base palte, as shown in Figure 3, the pattern being positioned at gate electrode layer 4 specifically can comprise first grid electrode pattern 41 (i.e. first grid) and second gate electrode pattern 42 (i.e. second grid).
Further, the view field of first grid electrode pattern 41 on array base palte, can cover the first view field of undoped region 23 on array base palte; The view field of second gate electrode pattern 42 on array base palte, can cover the second view field of undoped region 36 on array base palte.Due in the utility model embodiment, three doped regions lay respectively at both sides and the centre of two undoped region, therefore, utilize the pattern of gate electrode layer 4 to block the vibrational power flow of undoped region, be conducive in manufacturing process, accurately control the length of the position of doped regions.
In the utility model one specific embodiment, as shown in figures 2 and 3, the array base palte that the utility model embodiment provides specifically can also comprise:
Be arranged at the first insulating barrier 5 between substrate 1 and active layer.
The arranging of first insulating barrier 5 can play the object of isolated substrate 1 and active layer.
In the utility model one specific embodiment, as shown in figures 2 and 3, the array base palte that the utility model embodiment provides specifically can also comprise:
Be arranged at the second insulating barrier 6 on gate insulation layer 3 and gate electrode layer 4;
Be arranged at the source-drain electrode layer on the second insulating barrier 6, source electrode line 71 (i.e. source electrode) and electric leakage polar curve 72 (namely draining) is specifically comprised in source-drain electrode layer, wherein, source electrode line 71 is electrically connected with the first heavily doped region 21 by the first via hole 61 run through in the second insulating barrier 6 and gate insulation layer 3, and electric leakage polar curve 72 is electrically connected with the second heavily doped region 27 by the second via hole 62 running through the second insulating barrier 6 and gate insulation layer 3.In the utility model embodiment, the setting position of source electrode line 71 and electric leakage polar curve 72 is interchangeable.
Be arranged at the passivation layer 8 on source-drain electrode layer, in passivation layer 8, be provided with via hole 81;
Be arranged at the pixel electrode layer 9 on passivation layer 8, pixel electrode layer 9 is electrically connected with electric leakage polar curve 72 by the 3rd via hole 81 be arranged in passivation layer 8.
In another specific embodiment, the array base palte that the utility model embodiment provides, as shown in figures 2 and 3, specifically can also comprise:
Be arranged at the protective layer 10 on passivation layer 8 and pixel electrode layer 9;
Be arranged at the common electrode layer 11 on protective layer 10.
In the utility model embodiment, the length of doped regions (comprising the first doped regions 24, doped regions 22, second and the 3rd doped regions 26) specifically can be 1 to 3 micron, preferably 1.5 microns; And doped regions ion implantation concentration specifically can be 5-30ions/ centimetre
2, preferred 10ions/ centimetre
2.
And in the utility model embodiment, the ion implantation concentration of heavily doped region specifically can be 10-15ions/ centimetre
2scope, belongs to heavy doping category, and its length specifically can be 2 ~ 5 microns.
In order to make the array base palte that the utility model embodiment provides, the utility model embodiment still provides a kind of array substrate manufacturing method, and as shown in Figure 4, the method specifically can comprise:
On substrate 1, be formed with the pattern of active layer, gate insulation layer 3 and gate electrode layer 4 successively, wherein, active layer is disposed with the first undoped region 23, second doped regions 24, second, doped regions 22, first, heavily doped region 21, first undoped region 25, the 3rd heavily doped region 27, doped regions 26, second in the horizontal direction.
In one embodiment, the array substrate manufacturing method that the utility model embodiment provides specifically can also comprise:
The pattern of the first insulating barrier 5 is made on substrate 1.
In one embodiment, the array substrate manufacturing method that the utility model embodiment provides specifically can also comprise:
The pattern of the second insulating barrier 6 is formed on gate insulation layer 3 and gate electrode layer 4;
In the second insulating barrier 6 and gate insulation layer 3, form the first via hole 61 and the second via hole 62, first via hole 61 is positioned on the first heavily doped region 21, the second via hole 62 is positioned on the second heavily doped region 27;
Source-drain electrode layer is formed on the second insulating barrier 6, source-drain electrode layer comprises source electrode line 71 and electric leakage polar curve 72, wherein, source electrode line 71 is electrically connected with the first heavily doped region 21 by the first via hole 61, and electric leakage polar curve 72 is electrically connected with the second heavily doped region 27 by the second via hole 62;
On source-drain electrode layer, form passivation layer 8 pattern, passivation layer 8 pattern comprises the 3rd via hole 81;
On passivation layer 8, form pixel electrode layer 9 pattern, pixel electrode layer 9 pattern is electrically connected with electric leakage polar curve 72 by the 3rd via hole 81.
In another specific embodiment, the array substrate manufacturing method that the utility model embodiment provides specifically can also comprise:
Protective layer 10 pattern is formed on passivation layer 8 and pixel electrode layer 9 pattern;
Common electrode layer 11 pattern is formed on protective layer 10 pattern.
The array base palte provided due to the utility model embodiment specifically can be single grid-type array base palte or double grid type array base palte, therefore, below to make single grid-type and double grid type array base palte, the array substrate manufacturing method that the utility model embodiment provides is described in detail.
When array base palte is single grid-type array base palte, as shown in Figure 5, the method specifically can comprise:
Step 51, makes the first insulating barrier 5 pattern on substrate 1.
The first insulating barrier 5 and the second insulating barrier 6 involved in the utility model embodiment, the material usually adopted is SiNx/SiO
2film combinations or SiO
2film, and carry out high-temperature process dehydrogenation after deposition is complete, not affect the characteristic of semiconductor of the active layer be formed thereon.
Step 52, deposition of amorphous silicon films on the first insulating barrier 5, after amorphous silicon membrane crystallization, by patterning processes, is formed with the silicon island 2 of active layer.
Concrete, can on the first insulating barrier 5 deposited amorphous silicon film, after laser annealing crystallization, formed polycrystalline silicon membrane, the silicon island 2 that patterning processes (comprise the coating of photoresist, exposure and development, and etching technics) is formed with active layer is carried out to polycrystalline silicon membrane.
Array base palte view after this step specifically can be as shown in Figure 6.
Step 53, silicon island 2 applies photoresist (PR), by patterning processes, forms breach in the photoresist, and breach is arranged in the top at doped regions 24, active layer first doped regions 22, second, the 3rd position place, doped regions 26.
Step 54, by breach, in silicon island 2, the first doped regions 24, doped regions 22, second, the 3rd position place, doped regions 26 carry out ion implantation, are formed with the first doped regions 24, doped regions 22, second in active layer, the 3rd doped regions 26.
In the utility model embodiment, the length of doped regions (comprising the first doped regions 24, doped regions 22, second and the 3rd doped regions 26) specifically can be 1 to 3 micron, preferably 1.5 microns.And doped regions ion implantation concentration specifically can be 5-30ions/ centimetre
2, preferred 10ions/ centimetre
2.
Ion involved by the utility model embodiment specifically can be boron ion etc.
Due in the utility model embodiment, doped regions and undoped region interval are arranged, and undoped region is the material of silicon island 2 without the need to the material of carrying out ion implantation and undoped region, therefore, after the first doped regions 24, doped regions 22, second, the 3rd doped regions 26 complete, the first undoped region 23 and the second undoped region 24 also synchronously complete.
Array base palte view after this step specifically can be as shown in Figure 7.
Step 55, deposits gate insulation layer 3 film and grid layer 5 film successively on silicon island 2, by patterning processes, forms gate insulation layer 3 pattern and gate electrode layer 4 pattern.
Wherein, the view field of gate electrode layer 4 pattern on array base palte, is covered in the first undoped region 23, second doped regions 24, second, doped regions 22, first undoped region 25, the 3rd view field of doped regions 26 on array base palte in active layer.
Concrete, this step can adopt conventional patterning processes, is formed the pattern of gate insulation layer 3 and gate electrode layer 4 by techniques such as gluing, exposure, development, etching, strippings.
Array base palte view after this step specifically can be as shown in Figure 8.
Step 56, in silicon island 2, the first heavily doped region 21 and the second position place, heavily doped region 27 carry out ion implantation, are formed with the first heavily doped region 21 and the second heavily doped region 27 in active layer.
In the utility model embodiment, the ion implantation concentration of heavily doped region specifically can be 10-15ions/ centimetre
2scope, belongs to heavy doping category.And the length of heavily doped region can be same as the prior art.
Array base palte view after this step specifically can be as shown in Figure 9.
Step 57, forms the second insulating barrier 6, source-drain electrode layer, passivation layer 8, pixel electrode layer 9 pattern successively.
Concrete, specifically can comprise in this step:
The pattern of the second insulating barrier 6 is formed on gate insulation layer 3 and gate electrode layer 4;
In the second insulating barrier 6 and gate insulation layer 3, form the first via hole 61 and the second via hole 62, first via hole 61 is positioned on the first heavily doped region 21, the second via hole 62 is positioned on the second heavily doped region 27;
Source-drain electrode layer is formed on the second insulating barrier 6, source-drain electrode layer comprises source electrode line 71 and electric leakage polar curve 72, wherein, source electrode line 71 is electrically connected with the first heavily doped region 21 by the first via hole 61, electric leakage polar curve 72 is electrically connected with the second heavily doped region 27 by the second via hole 62, now, array base palte view can as shown in Figure 10 (vertical view);
On source-drain electrode layer, form passivation layer 8 pattern, passivation layer 8 pattern comprises the 3rd via hole 81;
On passivation layer 8, form pixel electrode layer 9 pattern, pixel electrode layer 9 pattern is electrically connected with electric leakage polar curve 72 by the 3rd via hole 81.
In the utility model embodiment, the making of each layer in conventional patterning processes completing steps 57 can be adopted.
Step 58, forms protective layer 10 and common electrode layer 11 pattern.
This step specifically can comprise:
Protective layer 10 pattern is formed on passivation layer 8 and pixel electrode layer 9 pattern;
Common electrode layer 11 pattern is formed on protective layer 10 pattern.
In the utility model embodiment, the making of each layer in conventional patterning processes completing steps 58 can be adopted.
By the realization of above-mentioned manufacture craft, can make single grid-type array base palte that the utility model embodiment provides, the concrete structural representation of this array base palte can be as shown in Figure 2.
When the array base palte that the utility model embodiment provides is double grid type array base palte, as shown in figure 11, the method specifically can comprise:
Step 111, makes the first insulating barrier 5 pattern on substrate 1.
The implementation procedure of this step can be identical with above-mentioned steps 51.
Step 112, deposition of amorphous silicon films on the first insulating barrier 5, after amorphous silicon membrane crystallization, by patterning processes, is formed with the silicon island 2 of active layer.
The implementation procedure of this step can be identical with above-mentioned steps 52.
Array base palte view after this step can be as shown in Figure 6.
Step 113, silicon island 2 applies photoresist, by patterning processes, etches away the photoresist above the first heavily doped region 21 and the second position place, heavily doped region 27 in silicon island 2.
Step 114, carries out ion implantation to the first heavily doped region 21 and the second position place, heavily doped region 27 in silicon island 2, is formed with the first heavily doped region 21 and the second heavily doped region 27 in active layer.
In this step, specifically can inject phosphine (PH to the silicon island 2 at the first heavily doped region 21 and the second position place, heavily doped region 27
3) ion, thus form the first heavily doped region 21 (N
+sI) and the second heavily doped region 27 (N
+sI).
Array base palte view after this step specifically can be as shown in figure 12.
Step 115, deposits gate insulation layer 3 film and grid layer 5 film successively on silicon island 2, by patterning processes, forms gate insulation layer 3 pattern and gate electrode layer 4 pattern.
Gate electrode layer 4 pattern comprises first grid electrode pattern 41 and second gate electrode pattern 42, and wherein, the view field of first grid electrode pattern 41 on array base palte, can cover the first view field of undoped region 23 on array base palte; The view field of second gate electrode pattern 42 on array base palte, can cover the view field of the second undoped region on array base palte.
Due in the utility model embodiment, three doped regions lay respectively at both sides and the centre of two undoped region, therefore, utilize gate electrode pattern to block the vibrational power flow of undoped region, be conducive in subsequent fabrication process, accurately control position and the width of doped regions.
Concrete, this step can adopt conventional patterning processes, is formed the pattern of gate insulation layer 3 and gate electrode layer 4 by techniques such as gluing, exposure, development, etching, strippings.
Etching technics involved in this step specifically can adopt dry etch process to carry out.High resolution lithography glue can be used, on mask pattern is selected on Other substrate materials is selected.Phase mask technology or wing patterned mask (Wing Pattern Mask) technology can be used, also can the comprehensive use of above-mentioned mask technique, thus can the accurately position of control gate layer 5 pattern and width, thus be conducive to the position and the width that accurately control doped regions.
Array base palte view after this step specifically can be as shown in figure 13.
Step 116, in silicon island 2, the first doped regions 24, doped regions 22, second, the 3rd position place, doped regions 26 carry out ion implantation, are formed with the first doped regions 24, doped regions 22, second in active layer, the 3rd doped regions 26.
To be positioned at above the first undoped region 23 due to first grid electrode pattern 41 and to cover the first undoped region 23, and second gate electrode pattern 42 is positioned at above the second undoped region 25 and cover the second undoped region 25, therefore, gate electrode layer 4 pattern completed can be utilized in this step to be benchmark, from first grid electrode pattern 41 and second gate electrode pattern 42 both sides and centre position, in silicon island 2, inject ion, thus be formed with the first doped regions 24, doped regions 22, second in active layer, the 3rd doped regions 26.
Array base palte view after this step specifically can be as shown in figure 14.
Step 117, forms the second insulating barrier 6, source-drain electrode layer, passivation layer 8, pixel electrode layer 9 pattern successively.
This step can be identical with step 57 or similar, but form source electrode line 71 and electric leakage polar curve 72 on the second insulating barrier 6 after, array base palte view can as shown in figure 15 (vertical view).
Step 118, forms protective layer 10 and common electrode layer 11 pattern.
This step specifically can comprise:
Protective layer 10 pattern is formed on passivation layer 8 and pixel electrode layer 9 pattern;
Common electrode layer 11 pattern is formed on protective layer 10 pattern.
In the utility model embodiment, the making of each layer in conventional patterning processes completing steps 118 can be adopted.
By the realization of above-mentioned manufacture craft, can make the double grid type array base palte that the utility model embodiment provides, the concrete structural representation of this array base palte can be as shown in Figure 3.
In the utility model one specific embodiment, between step 52 and step 53, or between step 112 and 113, specifically can also comprise array base palte channel region (i.e. thin-film transistor TFT) threshold voltage (Vth) doping (Vth Doping) process, namely by injecting the ion of respective type and quantitative levels concentration to the active layer silicon island 2 formed, to realize the object that array substrate channel region threshold voltage arranges adjustment.
The utility model embodiment still provides a kind of display unit, and this display makes the array base palte that specifically can comprise above-mentioned the utility model embodiment and provide.
This display unit is specifically as follows the display unit such as liquid crystal panel, LCD TV, liquid crystal display, oled panel, OLED display, plasma display or Electronic Paper.
As can be seen from the above, array base palte that the utility model provides and preparation method thereof, display unit, by on the substrate of array base palte, set gradually active layer, gate insulation layer and gate electrode layer, described active layer is disposed with the first heavily doped region, the first doped regions, the first undoped region, the second doped regions, the second undoped region, the 3rd doped regions, the second heavily doped region in the horizontal direction.Thus can under the prerequisite guaranteeing aperture opening ratio, the heat effectively reducing low-temperature polysilicon film transistor produces and effectively suppresses the leakage current of polycrystalline SiTFT.
The above is only execution mode of the present utility model; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection range of the present utility model.
Claims (9)
1. an array base palte, is characterized in that, comprising:
The active layer set gradually on substrate, gate insulation layer and gate electrode layer, wherein, described active layer is disposed with the first heavily doped region, the first doped regions, the first undoped region, the second doped regions, the second undoped region, the 3rd doped regions, the second heavily doped region in the horizontal direction.
2. array base palte as claimed in claim 1, it is characterized in that, described second doped regions is arranged at the centre position in described active layer horizontal direction.
3. array base palte as claimed in claim 1, it is characterized in that, the view field of pattern on array base palte of described gate electrode layer, is covered in described first doped regions, the first undoped region, the second doped regions, the second undoped region, the 3rd view field of doped regions on array base palte.
4. array base palte as claimed in claim 1, it is characterized in that, described gate electrode layer comprises first grid electrode pattern and second gate electrode pattern;
The described view field of first grid electrode pattern on array base palte, covers the described view field of the first undoped region on array base palte;
The described view field of second gate electrode pattern on array base palte, covers the described view field of the second undoped region on array base palte.
5. array base palte as claimed in claim 1, is characterized in that, also comprise:
Be arranged at the first insulating barrier between substrate and active layer.
6. array base palte as claimed in claim 1, is characterized in that, also comprise:
Be arranged at the second insulating barrier on described gate insulation layer and gate electrode layer;
Be arranged at the source-drain electrode layer on described second insulating barrier, described source-drain electrode layer comprises source electrode line and electric leakage polar curve, wherein, described source electrode line is electrically connected with described first heavily doped region by the first via hole run through in described second insulating barrier and gate insulation layer, and described electric leakage polar curve is electrically connected with described second heavily doped region by the second via hole running through described second insulating barrier and gate insulation layer;
Be arranged at the passivation layer on described source-drain electrode layer;
Be arranged at the pixel electrode layer on described passivation layer, described pixel electrode layer is electrically connected with described electric leakage polar curve by the 3rd via hole be arranged in described passivation layer.
7. array base palte as claimed in claim 6, is characterized in that, also comprise:
Be arranged at the protective layer on described passivation layer and pixel electrode layer;
Be arranged at the common electrode layer on described protective layer.
8. the array base palte as described in any one of claim 1 to 7, is characterized in that, the length of described first doped regions, the second doped regions and the 3rd doped regions is 1 to 3 micron, and doped regions ion implantation concentration is 5 to 30ions/ centimetre
2.
9. a display unit, is characterized in that, comprises the array base palte as described in any one of claim 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420613618.0U CN204130536U (en) | 2014-10-22 | 2014-10-22 | A kind of array base palte and display unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420613618.0U CN204130536U (en) | 2014-10-22 | 2014-10-22 | A kind of array base palte and display unit |
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| CN204130536U true CN204130536U (en) | 2015-01-28 |
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| CN201420613618.0U Expired - Fee Related CN204130536U (en) | 2014-10-22 | 2014-10-22 | A kind of array base palte and display unit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104282696A (en) * | 2014-10-22 | 2015-01-14 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN111863605A (en) * | 2020-07-31 | 2020-10-30 | 合肥维信诺科技有限公司 | Thin film transistor, method of making the same, and display |
| WO2023272503A1 (en) * | 2021-06-29 | 2023-01-05 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method therefor, display substrate, and display apparatus |
-
2014
- 2014-10-22 CN CN201420613618.0U patent/CN204130536U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104282696A (en) * | 2014-10-22 | 2015-01-14 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| WO2016061961A1 (en) * | 2014-10-22 | 2016-04-28 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor and display device |
| US9917198B2 (en) | 2014-10-22 | 2018-03-13 | Boe Technology Group Co., Ltd. | Array substrate, manufacturing method thereof and display device |
| CN104282696B (en) * | 2014-10-22 | 2018-07-13 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display device |
| CN111863605A (en) * | 2020-07-31 | 2020-10-30 | 合肥维信诺科技有限公司 | Thin film transistor, method of making the same, and display |
| WO2023272503A1 (en) * | 2021-06-29 | 2023-01-05 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method therefor, display substrate, and display apparatus |
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