CN101286530B - polysilicon thin film transistor - Google Patents
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- CN101286530B CN101286530B CN2008100181478A CN200810018147A CN101286530B CN 101286530 B CN101286530 B CN 101286530B CN 2008100181478 A CN2008100181478 A CN 2008100181478A CN 200810018147 A CN200810018147 A CN 200810018147A CN 101286530 B CN101286530 B CN 101286530B
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Abstract
本发明公开了一种多晶硅薄膜晶体管。主要解决目前多晶硅薄膜器件性能较差，饱和电压较高的问题。整个器件包括玻璃衬底、栅电极、漏电极和源电极，其中栅电极位于玻璃衬底上方，该栅电极的长度覆盖源电极和源漏之间的沟道长度，以同时控制源电极和沟道区。栅电极上淀积有Si3N4介质层，该Si3N4介质层的长度覆盖整个栅电极和漏电极。Si3N4介质层上淀积有本征多晶硅薄，源极和漏极分别设置其两端，且源极采用肖特基金属，并通过栅电压，控制源电极肖特基势垒高度，进而控制器件中的电流大小。本发明比常规多晶硅薄膜器件的饱和电压低10倍，在相同偏压情况下，比常规多晶硅薄膜晶体管的开态电流提高了50％以上，可用于有源矩阵阵列液晶显示器的开关。
The invention discloses a polysilicon thin film transistor. It mainly solves the problems of poor performance and high saturation voltage of current polysilicon thin film devices. The whole device includes a glass substrate, a gate electrode, a drain electrode and a source electrode, wherein the gate electrode is located above the glass substrate, and the length of the gate electrode covers the channel length between the source electrode and the source and drain to simultaneously control the source electrode and the channel length. road area. A Si 3 N 4 dielectric layer is deposited on the gate electrode, and the length of the Si 3 N 4 dielectric layer covers the entire gate electrode and the drain electrode. Intrinsic polysilicon is deposited on the Si 3 N 4 dielectric layer, and the source and drain are respectively set at both ends, and the source is made of Schottky metal, and the height of the Schottky barrier of the source electrode is controlled by the gate voltage. And then control the size of the current in the device. The invention is 10 times lower than the saturation voltage of the conventional polysilicon thin film device, under the same bias condition, the on-state current of the conventional polysilicon thin film transistor is increased by more than 50%, and can be used for the switch of the active matrix array liquid crystal display.
Description
Technical field
The invention belongs to field of electrical components, relate to semiconductor device, particularly a kind of polysilicon membrane structure.
Background technology
In the later stage eighties, the microelectronics technology combines with liquid crystal display, has formed active matrix liquid crystal display AMLCD.Because the definition of AMLCD can be compared with traditional picture tube CRT with chromaticity, and itself has advantages such as volume is little, in light weight, power consumptive province, no X-radiation, thereby becomes the regeneration product of Display Technique, develops very rapid.AMLCD requires in a bigger areal extent, for example 3 inches to 9 inches, be each pixel cell, for example 480 * 640 pixel cells are mixed a switch element, the array of this switch element must be made on the substrate of printing opacity, thereby conventional transistor MOS integrated circuit technique is difficult to competent.In order to adapt to the needs of AMLCD, people have studied the switch element array of many types, but at present real practicability has only two terminal device MIM diode MIM array, three terminal device amorphous silicon film transistor a-Si tft array and polycrystalline SiTFT Poly-Si tft array.And aspect the demonstration of high picture element video, can drive AMLCD with the thin-film transistor that has only that CRT is equal to mutually.
First thin-film transistor AMLCD tv display screen adopts amorphous silicon to make in the world.Amorphous silicon membrane can be at a lower temperature, for example 300-400 ℃ of deposit forms, backing material can be selected common glass for use, the technology cost is lower, the switch performance of a-Si TFT is better than two terminal device MIM array in addition, make the a-Si tft array become the mainstream technology that current AMLCD adopts, be used for fields such as large-curtain projecting TV set, pocket TV, portable computer.Yet,, become the technical bottleneck of display development owing to lower, the less stable of mobility of charge carrier rate in the non-crystalline silicon tft device under voltage stress and the illumination condition.Because the height of the mobility ratio non-crystalline silicon tft of multi-crystal TFT device, ghost effect is again little, shows that at implacable big panel of non-crystalline silicon tft and smaller screen face multi-crystal TFT has demonstrated huge superiority under the situation in field.
The typical structure of multi-crystal TFT is as shown in Figure 1: at the substrate of insulating material, as deposition of intrinsic polysilicon membrane on glass, the mode of injecting with ion forms source-drain area, is gate insulation layer then, as SiO
2And grid, as heavily doped polysilicon.Multi-crystal TFT is similar to the MOS field-effect transistor structure, especially close with the full-exhaustion SOI mos transistor structure, topmost difference is a backing material, and polycrystalline SiTFT is not to be substrate with monocrystalline silicon, and the glass of printing opacity is substrate but adopt cheaply.The general SiO that adopts thermal oxidation in the MOS transistor
2Gate dielectric layer, yet a large amount of Si that experimental results show that the deposit of low temperature PECVD method
3N
4Gate medium as polycrystalline SiTFT has a lot of advantages, and for example anti-preferably radiation property, higher barrier height can suppress the impurity break-through, resists preferably and wears characteristic etc.Similar to the field effect transistor of crystal, when making alive on grid, will respond to the formation conductive channel, by regulating the size of grid voltage, the electric current between Controlling Source is leaked.When adding,, drain voltage exhausted the channel carrier of drain terminal, the raceway groove pinch off, leakage current reaches capacity.Behind the raceway groove pinch off, continue to apply drain voltage, the output impedance of field-effect transistor is determined by the length of effective channel from the source end to pinch-off point, increases along with leaking to press, and the electric field in the raceway groove increases, thereby channel conduction increases.Along with dwindling of multi-crystal TFT channel length, the drain terminal electric field sharply increases.Owing to have a large amount of crystal grain boundaries in the polysilicon membrane, the high electric field of drain terminal is by the emission of trap states field, and leakage current sharply increases, and becoming influences the key factor that field-effect transistor performance improves.The effective measures that reduce multi-crystal TFT device off-state current are to reduce the high electric field of drain terminal.For this reason, people have proposed many improvement devices, for example offset gate structure, LDD structure, an induction drain junction structure etc.When multi-crystal TFT was in OFF state, with respect to traditional multi-crystal TFT device, the drain terminal electric field of these devices all decreased, and therefore, leakage current reduces, and effectively raises the performance of multi-crystal TFT.Yet when polycrystalline SiTFT was in ON state, the parasitic series resistance of these devices was too high again, has suppressed the raising of ON state current.The multi-crystal TFT device is as the switching device among the AMLCD, and what characterize its performance is the ratio of ON state current and off-state current.Therefore the increase that reduces or only have ON state current of off-state current is only arranged, the desirable device architecture of all can not saying so.For this reason, be badly in need of seeking more effective TFT device architecture,, improve device performance, promote further developing of AMLCD by improving the ratio of ON state current and off-state current.
The content of invention
The objective of the invention is to overcome the deficiency of polysilicon film device, the big polycrystalline silicon thin film transistor structure and the preparation method of ratio of a kind of ON state current and off-state current is provided, to improve the performance of polycrystalline SiTFT
Technical thought of the present invention is the structure with reference to silicon-based devices, the successful Schockley barrier MOS device of preparing in the silicon-based devices, leak without heavily doped region in the source of this device, but replace heavily doped region with silicide with metallic character or metal, two back-to-back Schottky barriers separate source, leakage, and drain current depends on the electron tunneling situation by whole potential barrier.A large amount of Schottky contacts that experiment showed, have for example effectively reduced to perplex the short channel effect of conventional field effect transistor and parasitic dipolar effect, parasitic series resistance and electric capacity when device size lowers significantly.During ON state, near the potential barrier thickness attenuate in source region, tunnelling current sharply rises along with the decline of potential barrier thickness grid, makes source, leakage current cross significant electric current down; During OFF state, the space charge region of the anti-inclined to one side schottky junction of source end is thicker, the tunnelling current by potential barrier seldom, the electric current that flows through source, leakage is littler.Therefore the ratio of ON state current and off-state current increases substantially, and device performance improves.In addition, its technology is much simpler than ion implantation technology, can the lattice of material not exerted an influence, and helps improving Devices Characteristics.Gain enlightenment from silica-based Schockley barrier MOS device, we consider whether also can use the performance that Schottky barrier improves device in multi-crystal TFT.Can increase the high electric field that extra technology just can reduce drain terminal like this, eliminate parasitic high series resistance, improve ON state current and reduce leakage current.Yet one must not irrespective factor be exactly that polysilicon is easy to crystallization again at Schottky source drain and polysilicon interface, still grain boundary may occur at whole active area like this, makes the film quality variation.In addition, by the source, omit living series resistance to the influence of device and circuit performance as can be known, the series resistance in source region is more serious to the influence of device and circuit.From these two factors, the present invention considers on the basis of original Schottky source drain structure device architecture to be transformed, and makes negative effect littler, and advantage is more outstanding.
According to above-mentioned thinking, device architecture of the present invention comprises: glass substrate, gate electrode, drain electrode and source electrode, wherein said gate electrode are positioned at the glass substrate top, and this is deposited with Si above gate electrode
3N
4Dielectric layer, Si
3N
4Be deposited with the intrinsic polysilicon film on the dielectric layer; Described source electrode adopts the schottky metal electrode, is positioned at the top of intrinsic polysilicon film.
Above-mentioned polycrystalline SiTFT, wherein the length of gate electrode covers the channel length between source electrode and the source leakage, with while Controlling Source electrode and channel region.
Above-mentioned polycrystalline SiTFT, wherein Si
3N
4The thickness of dielectric layer is 50-300nm, and length covers whole gate electrode and drain electrode.
Above-mentioned polycrystalline SiTFT wherein is deposited with Si on the glass substrate of gate electrode one end simultaneously
3N
4Dielectric layer.
The present invention makes the method for polycrystalline SiTFT, comprises following process:
(1) sputter one deck chromium metal on glass substrate, the etching metal gate also forms gate electrode;
(2) on the substrate of grid metal electrode and grid metal electrode one end, utilize plasma-reinforced chemical vapor deposition method PECVD at the 200-350 ℃ of thick Si of following deposit 50-300nm
3N
4Gate dielectric layer;
(3) at Si
3N
4Utilize the PECVD method at 200-350 ℃ of following deposition of intrinsic amorphous silicon membrane active area on the gate dielectric layer earlier, by scanning, annealing, making the amorphous silicon recrystallization is polysilicon again, and at polysilicon surface 10KeV, dosage 1 * 10
14Cm
-2Phosphorus carry out the potential barrier adjustment and mix;
(4) carry out phosphonium ion earlier on the surface of phosphor doped polysilicon one end and inject, form n
+Polysilicon drain contact district, and deposit aluminium is as leaking Ohm contact electrode; Deposit chromium forms the Schottky source contact electrode again;
(5) between source leakage metal electrode, use 12KeV, 2 * 10
13Cm
-2BF
2Compensate doping, the phosphonium ion that forms at channel region when mixing because of the potential barrier adjustment with adjustment;
(6) under 250 ℃ of temperature, form polycrystalline SiTFT with nitrogen by annealing, passivation.
Among the present invention owing to adopt bottom gate structural manufacturing process, i.e. gate electrode and Si
3N
4Gate dielectric layer is positioned at the below of intrinsic polysilicon film active area, thereby Si
3N
4Better with the characteristic at polysilicon membrane interface, interface trap density is lower; Simultaneously because the present invention adopts the length of its gate electrode to cover source electrode and the source channel length between leaking, so can while Controlling Source electrode and channel region; In addition because the source electrode adopts schottky metal, so can be by being applied to the gate voltage on the gate electrode, come Controlling Source electrode schottky barrier height, when increase along with drain voltage, when the drain depletion layer expands to polysilicon/gate dielectric layer interface, current saturation, corresponding drain voltage is saturated drain voltage V
SAT, drain voltage further increases, the expansion of drain depletion course drain electrode, but the height of Schottky barrier is not almost influenced, the short-channel effect of device has obtained very big improvement; Owing to after polycrystalline SiTFT reaches capacity state, by the anti-height of Schottky barrier partially of gate voltage control, can improve ON state current, reduce off-state current, promptly the ratio of ON state current and off-state current increases, thereby improves the performance of device in addition.
Simulation result shows, polycrystalline SiTFT of the present invention has lower saturation voltage and higher output impedance, and its saturation voltage hangs down 10 times than the saturation voltage of conventional polycrystalline SiTFT.Under the identical bias situation, improved more than 50% than the ON state current of conventional polycrystalline SiTFT, the ratio of ON state current and off-state current is greater than 10
-9
Description of drawings
Fig. 1 is conventional multi-crystal TFT device architecture schematic diagram;
Fig. 2 is a device architecture schematic diagram of the present invention;
Fig. 3 is the main technique step schematic diagram of preparation device of the present invention;
Fig. 4 is at different gate medium Si
3N
4Thickness T
InsFollowing threshold voltage analogous diagram to device of the present invention;
Fig. 5 is at different gate medium Si
3N
4Thickness T
InsFollowing I-V characteristic Simulation figure to device of the present invention;
Fig. 6 (a) is at different gate voltage V
GsFollowing output characteristic analogous diagram to device of the present invention;
Fig. 6 (b) is at different gate voltage V
GsFollowing output characteristic analogous diagram to conventional polycrystalline SiTFT
Fig. 7 (a) is at different gate voltage V
GsFollowing electron distributions analogous diagram to device of the present invention;
Fig. 7 (b) is at different gate voltage V
GsFollowing electron distributions analogous diagram to conventional polycrystalline SiTFT;
Fig. 8 (a) is to the output characteristic analogous diagram of device of the present invention under different channel length d;
Fig. 8 (b) is to the output characteristic analogous diagram of conventional polycrystalline SiTFT under different channel length d;
Fig. 9 is at different barrier height Φ
bFollowing transfer characteristic analogous diagram to device of the present invention.
Embodiment
With reference to Fig. 2, device of the present invention mainly is made of glass substrate, gate electrode, drain electrode and source electrode, wherein being deposited with thickness on the glass substrate is the 100-200nm gate electrode, the length of gate electrode covers the channel length between source electrode and the source leakage, with the electromotive force of while Controlling Source electrode and channel region.It is 50-300nmSi that the upper surface of gate electrode is deposited with thickness
3N
4Dielectric layer, also being deposited with thickness simultaneously on the glass substrate of gate electrode one end is 150-500nmSi
3N
4Dielectric layer, this Si
3N
4The length of dielectric layer covers whole gate electrode and drain electrode.Si
3N
4Being deposited with thickness on the dielectric layer is 100-300nm intrinsic polysilicon film Poly-Si.End at polysilicon membrane is that phosphate ion concentration is greater than 10
19Cm
-3The heavy doping drain region, be the aluminium Ohm contact electrode of 100-200nm on it.The other end of polysilicon membrane is that thickness is the Schottky source electrode of the chromium metal formation of 100-200nm.Channel length d between leak in the source is 0.5-2 μ m, and the length s of source electrode is 4 μ m, and the length of drain electrode is identical with the source electrode length, and the length L of gate electrode is channel length d and source electrode length s sum.
The operation principle of device of the present invention is that the schottky barrier height by the reversed bias voltage Controlling Source end that is applied to gate electrode carries out.When drain voltage reached capacity, the depletion layer of drain terminal arrived Si
3N
4The interface of dielectric layer and polysilicon membrane further increases drain voltage, and depletion layer is expanded to drain electrode, Schottky barrier influence to the source end is very little, change source end schottky barrier height by applying gate voltage this moment, and control is by the charge carrier of Schottky barrier, to change the size of current of device.
With reference to Fig. 3, preparation of devices process of the present invention is as follows:
Example 1
(1) the thick chromium metal of sputter one deck 100nm on glass substrate, etching length is the metal gate of 4.5 μ m, and forms gate electrode;
(2) on the glass substrate of grid metal electrode and grid metal electrode one end, utilize plasma-reinforced chemical vapor deposition method PECVD deposit Si
3N
4Gate dielectric layer, deposition temperature are 200 ℃, the Si of deposit on the grid metal electrode
3N
4Thickness is 50nm, at the Si of grid metal electrode one end deposit
3N
4Thickness is 150nm;
(3) at Si
3N
4Utilize the PECVD method at 200 ℃ of following deposition of intrinsic amorphous silicon membrane active areas on the gate dielectric layer earlier, by XeCl excimer pulse laser scanning film surface, anneal under room temperature, inert gas atmosphere then, making the amorphous silicon recrystallization is polysilicon again, then use the dry etching polysilicon, at Si
3N
4Carve the contact hole of island formation gate electrode;
(4) at polysilicon surface 10KeV, dosage 1 * 10
14Cm
-2Phosphorus carry out the potential barrier adjustment and mix, and carry out phosphonium ion earlier on the surface of phosphor doped polysilicon one end and inject, form ion concentration greater than 10
19Cm
-3N
+Polysilicon drain contact district, deposition thickness is 100nm aluminium and chromium respectively again, as leaking Ohm contact electrode and Schottky source contact electrode;
(5) between source leakage metal electrode, use 12KeV, 2 * 10
13Cm
-2BF
2Compensate doping, the phosphonium ion that forms at channel region when mixing because of the potential barrier adjustment with adjustment;
(6) with nitrogen pressure be 2Torr, temperature be anneal under 250 ℃, passivation, punching extraction electrode solder joint forms polycrystalline SiTFT.
Example 2
(1) the thick molybdenum of sputter one deck 150nm on glass substrate, etching length is the metal gate of 5 μ m, and forms gate electrode;
(2) on the substrate of grid metal electrode and grid metal electrode one end, utilize plasma-reinforced chemical vapor deposition method PECVD deposit Si
3N
4Gate dielectric layer, deposition temperature are 250 ℃, the Si of deposit on the grid metal electrode
3N
4Thickness is 100nm, at the Si of grid metal electrode one end deposit
3N
4Thickness is 250nm;
(3) at Si
3N
4Utilize the PECVD method at 250 ℃ of following deposition of intrinsic amorphous silicon membrane active areas on the gate dielectric layer earlier, by scanning, annealing, making the amorphous silicon recrystallization is polysilicon, then uses the dry etching polysilicon, at Si again
3N
4Carve the contact hole of island formation gate electrode;
(4) at polysilicon surface 10KeV, dosage 1 * 10
14Cm
-2Phosphorus carry out the potential barrier adjustment and mix, and carry out phosphonium ion earlier on the surface of phosphor doped polysilicon one end and inject, form ion concentration greater than 10
19Cm
-3N
+Polysilicon drain contact district, deposition thickness is 150nm aluminium and chromium respectively again, as leaking Ohm contact electrode and Schottky source contact electrode;
(5) between source leakage metal electrode, use 12KeV, 2 * 10
13Cm
-2BF
2Compensate doping, the phosphonium ion that forms at channel region when mixing because of the potential barrier adjustment with adjustment;
(6) with nitrogen pressure be 2Torr, temperature be anneal under 250 ℃, passivation, punching extraction electrode solder joint forms polycrystalline SiTFT.
Example 3
(1) the thick chromium metal of sputter one deck 200nm on glass substrate, etching length is the metal gate of 6 μ m, and forms gate electrode;
(2) on the glass substrate of grid metal electrode and grid metal electrode one end, utilize plasma-reinforced chemical vapor deposition method PECVD deposit Si
3N
4Gate dielectric layer, deposition temperature are 350 ℃, the Si of deposit on the grid metal electrode
3N
4Thickness is 300nm, at the Si of grid metal electrode one end deposit
3N
4Thickness is 500nm;
(3) at Si
3N
4Utilize the PECVD method at 350 ℃ of following deposition of intrinsic amorphous silicon membrane active areas on the gate dielectric layer earlier, by XeCl excimer pulse laser scanning film surface, anneal under room temperature, inert gas atmosphere then, making the amorphous silicon recrystallization is polysilicon again, then use the dry etching polysilicon, at Si
3N
4Carve the contact hole of island formation gate electrode;
(4) at polysilicon surface 10KeV, dosage 1 * 10
14Cm
-2Phosphorus carry out the potential barrier adjustment and mix, and carry out phosphonium ion earlier on the surface of phosphor doped polysilicon one end and inject, form ion concentration greater than 10
19Cm
-3N
+Polysilicon drain contact district, deposition thickness is 200nm aluminium and chromium respectively again, as leaking Ohm contact electrode and Schottky source contact electrode;
(5) between source leakage metal electrode, use 12KeV, 2 * 10
13Cm
-2BF
2Compensate doping, the phosphonium ion that forms at channel region when mixing because of the potential barrier adjustment with adjustment;
(6) with nitrogen pressure be 2Torr, temperature be anneal under 250 ℃, passivation, punching extraction electrode solder joint forms polycrystalline SiTFT.
Effect of the present invention can further specify by following emulation:
Simulated conditions:
A. change device channel length d of the present invention, Si
3N
4Thickness of dielectric layers T
Ins, grain size Lg and schottky barrier height Φ
bDraw electric properties of devices of the present invention;
B. change conventional polycrystalline silicon device channel length d, draw the electrology characteristic of conventional device;
C. the band-to-band-tunneling model and the carrier mobility model that adopt drift-diffusion Transport Model in the simulation process, begin from density of states tail, and in the carrier mobility model, select, High-Field saturation effect relevant, polysilicon and dielectric interface migration rate degradation parameter for use with channel doping;
D: in the simulation process source electrode of device of the present invention and the interface of polysilicon are defined as Schottky barrier.
If gate electrode length s=4 μ is m, channel length d=2 μ m, schottky barrier height Φ
b=0.3eV is by the device descriptive tool MDRAW generation emulation device of two-dimensional device numerical simulation device ISE.
In device simulation instrument DESSIS, device is applied the gate voltage V of 0-1V
Gs, obtain the transfer characteristic simulation curve and the threshold voltage of device of the present invention by visualization tool INSPECT, as Fig. 4.Fig. 4 has provided gate medium Si
3N
4Thickness is respectively 50nm, 100nm, 200nm, when 300nm, grain size Lg are 0.1-0.6 μ m to the influence of device threshold voltage of the present invention.As can see from Figure 4, when gate dielectric layer thickness was 100nm, grain boundary was very little to the influence of threshold voltage.When gate dielectric layer thickness is 50nm, because Si
3N
4Too thin, as to begin to grow ropy Si
3N
4Influence to polysilicon membrane is bigger, so threshold voltage shift is bigger.
In DESSIS, device is applied the gate voltage V of 0-8V
Gs, obtain the transfer characteristic simulation curve of device of the present invention by INSPECT, as shown in Figure 5.Fig. 5 has provided gate medium Si
3N
4When thickness is respectively 100nm, 200nm, 300nm, when being respectively 0.1 μ m, 0.3 μ m and 0.6 μ m, grain size, from Fig. 5 as seen, works as Si to the influence of device I-V properties of the present invention
3N
4When thickness was 100nm, transfer characteristic curve was best.
In the device of the present invention, establish grid length s=4 μ m, channel length d=2 μ m, schottky barrier height Φ
b=0.3eV utilizes two-dimensional device numerical simulation device ISE to apply the gate voltage V of 2V, 4V, 6V and 8V respectively
Gs, its output characteristic curve shown in Fig. 6 (a), its electronics along the distribution map of raceway groove shown in Fig. 7 (a)
In conventional polycrystalline SiTFT, establish the source, drain electrode length is 4 μ m, channel length d=2 μ m, its output characteristic curve shown in Fig. 6 (b), its electronics along the distribution map of raceway groove shown in Fig. 7 (b).
Show from Fig. 6 (a) and Fig. 6 (b) result relatively: device of the present invention has lower saturation voltage, is about 0.3V, and than low 10 times of the saturation voltage of conventional polysilicon film device, this has important meaning to the access display based on Organic Light Emitting Diode; The ON state current of device of the present invention is very big, under the identical bias situation, has improved more than 50% than the ON state current of conventional polycrystalline SiTFT.
Show from Fig. 7 (a) and Fig. 7 (b) result relatively: the electron concentration of device source end of the present invention is lower, and along with drain voltage increases, excess carrier concentration reduces.Therefore, electron concentration is not only lower at the source end, and is all lower in whole raceway groove.Excess carrier concentration in the device is low more, and the probability that forms defective is just more little.
In summary it can be seen that the performance of device of the present invention is much stable than conventional device.
In device of the present invention, establish source electrode length s=4 μ m, schottky barrier height Φ
b=0.3eV, channel length d are respectively 0.5 μ m, 1 μ m and 2 μ m, gate voltage V
GsBe respectively 2V, 4V, 6V and 8V, drain voltage V
DsDuring for 0-8V to device output characteristic of the present invention emulation shown in Fig. 8 (a).
In conventional device, establish channel length L and be respectively 0.5 μ m, 1 μ m and 2 μ m, gate voltage V
GsBe respectively 2V, 4V, 6V and 8V, drain voltage V
DsDuring for 0-8V, to the output characteristic emulation of conventional polysilicon film device shown in Fig. 8 (b).
Show from the comparative result of Fig. 8 (a) and Fig. 8 (b): the device of the present invention, along with channel length d shortens, leakage current under the same gate voltage much at one, the saturation voltage excursion is very little, even channel length d narrows down to 0.5 μ m, device still has preferable performance, shows that device of the present invention is lower to the short-channel effect susceptibility, influenced by it; And in conventional polysilicon film device, along with channel length L shortens, the electricity in electric current and the raceway groove is led and is increased sharply, when gate voltage Vgs is 6V, significantly warping phenomenon has appearred in the curve of output of channel length L=0.5 μ m device, shows serious short-channel effect.
In sum, even raceway groove narrows down to submicron-scale, device of the present invention still can keep higher performance, and output impedance is higher.
In the device of the present invention, establish source electrode length s=4 μ m, channel length d=0.5 μ m, schottky barrier height Φ
bBe respectively 0.1eV, 0.2eV, 0.3eV and 0.4eV, its transfer characteristic curve such as Fig. 9.
As seen from Figure 9: along with schottky barrier height Φ
bReduce, source-drain current increases rapidly.The off-state current of all barrier heights still hangs down barrier height device ON state current I much at one
OnWith off-state current I
OffRatio higher.
As can be known from the above results, pass through to optimize schottky barrier height Φ in the reality
bCan improve the performance of device.
Claims (2)
1. method for preparing polycrystalline SiTFT comprises following process:
(1) sputter one layer thickness is chromium or the molybdenum of 100-200nm on glass substrate, and etching length is 4.5-6 μ m metal gate and forms gate electrode;
(2) on the substrate of grid metal electrode and grid metal electrode one end, utilize plasma-reinforced chemical vapor deposition method PECVD deposition thickness to be respectively the Si of 50-300nm and 150-500nm
3N
4Gate dielectric layer, deposition temperature are 200-350 ℃;
(3) at Si
3N
4Utilize PECVD method deposition of intrinsic amorphous silicon membrane active area under 200-350 ℃ temperature on the gate dielectric layer earlier, by scanning, annealing, making the amorphous silicon recrystallization is polysilicon again, and at polysilicon surface 10KeV, dosage 1 * 10
14Cm
-2Phosphorus carry out the potential barrier adjustment and mix;
(4) carry out phosphonium ion earlier on the surface of phosphor doped polysilicon one end and inject, form phosphate ion concentration greater than 10
19Cm
-3N
+Polysilicon drain contact district, and deposition thickness is that the aluminium of 100-200nm is as leaking Ohm contact electrode; Deposition thickness is the chromium formation Schottky source contact electrode of 100-200nm again;
(5) between source leakage metal electrode, use 12KeV, 2 * 10
13Cm
-2BF
2Compensate doping, the phosphonium ion that forms at channel region when mixing because of the potential barrier adjustment with adjustment;
(6) usefulness nitrogen by annealing, passivation, punching extraction electrode solder joint, forms polycrystalline SiTFT under 250 ℃ of temperature.
2. the method for preparing polycrystalline SiTFT according to claim 1, wherein the preferred parameter of step (2) and step (3) is:
The Si of deposit on the grid metal electrode
3N
4Gate dielectric layer thickness is 100nm;
At Si
3N
4The temperature of the non-polysilicon membrane of deposition of intrinsic is 250 ℃ on the gate dielectric layer.
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|---|---|---|---|
| CN2008100181478A CN101286530B (en) | 2008-05-08 | 2008-05-08 | polysilicon thin film transistor |
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|---|---|---|---|
| CN2008100181478A CN101286530B (en) | 2008-05-08 | 2008-05-08 | polysilicon thin film transistor |
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| CN101286530A CN101286530A (en) | 2008-10-15 |
| CN101286530B true CN101286530B (en) | 2010-06-02 |
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| CN2008100181478A Expired - Fee Related CN101286530B (en) | 2008-05-08 | 2008-05-08 | polysilicon thin film transistor |
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| CN102236188B (en) * | 2010-04-23 | 2014-07-02 | 北京京东方光电科技有限公司 | Gate driving method and circuit and liquid crystal display (LCD) panel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4942441A (en) * | 1986-03-29 | 1990-07-17 | Hitachi, Ltd. | Thin film semiconductor device and method of manufacturing the same |
| US5159416A (en) * | 1990-04-27 | 1992-10-27 | Nec Corporation | Thin-film-transistor having schottky barrier |
| CN1815740A (en) * | 2004-12-16 | 2006-08-09 | 三星电子株式会社 | Thin film transistor, inverter, logic device, and method of manufacturing semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4942441A (en) * | 1986-03-29 | 1990-07-17 | Hitachi, Ltd. | Thin film semiconductor device and method of manufacturing the same |
| US5159416A (en) * | 1990-04-27 | 1992-10-27 | Nec Corporation | Thin-film-transistor having schottky barrier |
| CN1815740A (en) * | 2004-12-16 | 2006-08-09 | 三星电子株式会社 | Thin film transistor, inverter, logic device, and method of manufacturing semiconductor device |
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