CN203537350U

CN203537350U - Delay circuit

Info

Publication number: CN203537350U
Application number: CN201320669413.XU
Authority: CN
Inventors: 尹航; 王钊
Original assignee: Wuxi Vimicro Corp
Current assignee: Wuxi Vimicro Corp
Priority date: 2013-10-28
Filing date: 2013-10-28
Publication date: 2014-04-09
Anticipated expiration: 2023-10-28

Abstract

The utility model provides a low-noise delay circuit to achieve mentioned goals. The delay circuit comprises a delay circuit and a feedback control circuit. The delay circuit comprises an MP1, an MP2, a resistor R1, a charging capacitor C1 and an inverter, wherein the inverter is formed by an MP2 and an MN2. The source electrodes of the MP1 and the MP2 are connected with a power supply. The grid electrodes of the MN1 and the MP1 are connected with an input end. The public node of the source electrode of the NM2 and the drain electrode of the MP2 are connected with an output end. One end of R1 is connected with the drain electrode of the MP1, and the other end of R1 is connected with the source electrode of the MN1. The first end of the C1 is connected with the ground, and the second end of the C1 is connected with the public node of the inverter, the R1 and the MN1. The feedback control circuit comprises an MP3 and an MP4. The grid electrode of the MP4 is connected with the output end. The source electrode of the MP4 is connected with the drain electrode of the MP3. The drain electrode of the MP4 is connected with the second end of the C1. The grid electrode of the MP3 is connected with the input end, and the source electrode of the MP3 is connected with the power supply. The low-noise delay circuit provided by the embodiments of the utility model can be used for improving anti-interference capability.

Description

A kind of delay circuit

Technical field

The utility model relates to electronic applications, is specifically related to a kind of delay circuit.

Background technology

In chip design, often can use delay cell, some delay cell, is used capacitance resistance to form the delay of signal, and this kind of delay circuit is easily subject to noise jamming and causes delay cell output abnormality.

Fig. 1 is the circuit theory diagrams for the delay cell of prior art, wherein, IN is digital signal input end, OUT is for postponing digital signal output end, when the signal level of input IN is during from high step-down, NMOS pipe MN1 cut-off, PMOS transistor MP1 opens, power vd D charges to charging capacitor C1 by current-limiting resistance R1, its waveform can be referring to Fig. 2, when node node1 voltage rises to, surpasses by MN2, during inverter trigging signal that MP2 forms, the upset of output OUT level is from high step-down, thereby acquisition IN signal trailing edge is to the delay between OUT signal trailing edge.The shortcoming of this kind of delay circuit is if node1 is interfered near inverter trigging signal, and for example, larger noise appears in earth terminal, can cause OUT signal to occur repeatedly upset, probably causes subsequent conditioning circuit operation irregularity, and state can be referring to Fig. 3.

Utility model content

The purpose of this utility model is to provide a kind of low noise delay circuit, to avoid the noise effect of earth terminal noise to output output signal.

For achieving the above object, the utility model embodiment provides a kind of low noise delay circuit, and it comprises delay circuit and feedback control circuit,

Described delay circuit comprises a PMOS transistor, the first nmos pass transistor, resistance, the inverter that charging capacitor and the 2nd PMOS transistor and the second nmos pass transistor form, described first, the source electrode of the 2nd PMOS pipe connects power supply, described the first nmos pass transistor is connected input with the grid of a PMOS pipe, the source electrode of described the second nmos pass transistor is connected output with the common node of the transistorized drain electrode of the 2nd PMOS, described resistance one end is connected to the transistorized drain electrode of a described PMOS, the other end is connected to the source electrode of described the first nmos pass transistor, described charging capacitor first end ground connection, the second end is connected to the common node of described inverter and described resistance and described the first nmos pass transistor,

Described feedback control circuit comprises the 3rd MPOS transistor and the 4th PMOS transistor, the transistorized grid of described the 4th PMOS connects described output, the transistorized source electrode of described the 4th PMOS is connected to the transistorized drain electrode of described the 3rd PMOS, the transistorized drain electrode of described the 4th PMOS is connected to the second end of described charging capacitor, the transistorized grid of described the 3rd PMOS connects described input, and the transistorized source electrode of described the 3rd PMOS connects described power supply.

The low noise delay circuit providing according to the utility model embodiment, the input signal of described input is during from high step-down, described the first nmos pass transistor cut-off, a described PMOS transistor turns, described charging capacitor store electrical energy, when the voltage at described charging capacitor two ends reaches the trigging signal of described inverter, described the second nmos pass transistor conducting, so that described output end voltage reduces, described the 4th PMOS transistor turns, described the 3rd PMOS transistor turns, to improve the voltage of the second end of described charging capacitor.

The low noise delay circuit that adopts the utility model embodiment to provide, in the signal access feedback control circuit that output is drawn, when the voltage of output is during from high step-down, make the transistor turns in feedback control circuit, thereby draw high rapidly the voltage of charging capacitor, to avoid the impact of external factor on capacitance voltage, thus the antijamming capability of raising delay circuit.

Accompanying drawing explanation

In order to be illustrated more clearly in the technical scheme in the utility model embodiment, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is the schematic diagram of prior art delay circuit;

Fig. 2 is the perfect condition signal condition figure of the delay circuit shown in Fig. 1;

Fig. 3 is the reference diagram that the delay circuit shown in Fig. 1 is disturbed state;

Fig. 4 is the schematic diagram of the delay circuit that provides of the utility model embodiment;

Fig. 5 is the signal condition figure of the delay circuit shown in Fig. 4.

Embodiment

Below by drawings and Examples, the technical solution of the utility model is described in further detail.

As shown in Figure 4, a kind of low noise delay circuit that the utility model embodiment provides, comprise delay circuit and feedback control circuit, described delay circuit comprises a PMOS transistor MP3, the first nmos pass transistor MN1, resistance R 1, the inverter that charging capacitor C1 and the 2nd PMOS transistor MP2 and the second nmos pass transistor MN2 form, described MP1, the source electrode of MP2 connects power vd D, described the first nmos pass transistor MN1 is connected input IN with the grid of a PMOS pipe MP1, the source electrode of described the second nmos pass transistor MN2 is connected output OUT with the common node of the drain electrode of the 2nd PMOS transistor MP2, described resistance R 1 one end is connected to the drain electrode of a described PMOS transistor MP1, the other end is connected to the source electrode of described the first nmos pass transistor MN1, described charging capacitor C1 first end ground connection, the second end is connected to the common node node1 of described inverter and described resistance R 1 and described the first nmos pass transistor MN1,

Described feedback control circuit comprises the 3rd MPOS transistor MP3 and the 4th PMOS transistor MP4, the grid of described the 4th PMOS transistor MP4 connects described output OUT, the source electrode of described the 4th PMOS transistor MP4 is connected to the drain electrode of described the 3rd PMOS transistor MP3, the drain electrode of described the 4th PMOS transistor MP4 is connected to the second end of described charging capacitor C1, the grid of described the 3rd PMOS transistor MP3 connects described input IN, and the source electrode of described the 3rd PMOS transistor mp3 connects described power vd D.

The input signal of described input IN is during from high step-down, described the first nmos pass transistor MN1 cut-off, a described PMOS transistor MP1 conducting, described charging capacitor C1 store electrical energy, when the voltage at described charging capacitor C1 two ends reaches the trigging signal of described inverter, described the second nmos pass transistor MP2 conducting, so that described output OUT lower voltage, described the 4th PMOS transistor turns MP4, described the 3rd PMOS transistor MP3 conducting, thereby the voltage of C1 the second end is improved rapidly, reduce the interference of external signal to delay circuit, its signal condition figure, can be with reference to figure 5.

The delay circuit that adopts the utility model embodiment to provide, negate feedback signal from inhibit signal output channel, make it after having postponed, open immediately additional passageway, accelerate to postpone the process that discharges and recharges of electric capacity, make capacitance voltage as early as possible away from the trigging signal of rear class signal amplification circuit, thereby improve delay cell antijamming capability.

Above-described embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only embodiment of the present utility model; and be not used in and limit protection range of the present utility model; all within spirit of the present utility model and principle, any modification of making, be equal to replacement, improvement etc., within all should being included in protection range of the present utility model.

Claims

1. a low noise delay circuit, is characterized in that, comprises delay circuit and feedback control circuit,

2. low noise delay circuit as claimed in claim 1, it is characterized in that, the input signal of described input is during from high step-down, described the first nmos pass transistor cut-off, a described PMOS transistor turns, described charging capacitor store electrical energy, when the voltage at described charging capacitor two ends reaches the trigging signal of described inverter, described the second nmos pass transistor conducting, so that described output end voltage reduces, described the 4th PMOS transistor turns, described the 3rd PMOS transistor turns, to improve the voltage of the second end of described charging capacitor.