CN203102274U

CN203102274U - High speed data transmission connector

Info

Publication number: CN203102274U
Application number: CN 201320102546
Authority: CN
Inventors: 余国灿; 雍军; 李海滨
Original assignee: Chengdu City Weilai Heli Science & Technology Co Ltd
Current assignee: Chengdu City Weilai Heli Science & Technology Co Ltd
Priority date: 2013-03-07
Filing date: 2013-03-07
Publication date: 2013-07-31
Anticipated expiration: 2023-03-07

Abstract

The utility model discloses a high speed data transmission connector which comprises an ARM processor and an FPGA large-scale gate array. The FPGA large-scale gate array is provided with a double-port RAM converter and a data processor. The double-port RAM converter comprises a first I/O converter, a second I/O converter, a first data buffer, a second data buffer, a first decoder, a second decoder, a gate array memorizer, a logical controller, a control bus port, a data bus port and an address bus port. The high speed data transmission connector achieves temporary storage and real-time exchange of data, exchange of different types of data is achieved on the same interface, the hardware limitation of a traditional structural form when the function is upgraded or expanded is removed, and the high speed data transmission connector has strong function expanding performance, is safe and reliable and reduces maintenance cost.

Description

A kind of high speed data transfer connector

Technical field

The utility model relates to a kind of data transmission technology, refers more particularly to a kind of high speed data transfer connector.

Background technology

The extensive gate array of FPGA has very high data processing speed, and by a large amount of being applied in the high-speed digital signal treatment technology, FPGA relies on the signal handling capacity of its high speed and gains great popularity.Processor is as the trend of current electronic technology field, and it has high arithmetic capability and control characteristic, and it is as the outstanding person in the microcontroller, by a large amount of applying in the various intelligent equipments.Will give play to stronger effect if the thing of FPGA and these two kinds of very advantageous of processor combined, but to carry out this difference in conjunction with the problem that at first will consider speed, because say more a lot soon with respect to FPGA than the speed of processor, the port of data transmission has a lot of different types in intelligent equipment, as the data bus port, the address bus port, the control bus port, so just need additional equipment respectively different data line ports to be transformed respectively, not only increased the link of intermediate data conversion, and can not expand and upgrade equipment functional, also increased extra maintenance cost.

The utility model content

A kind of extendability is strong, the high speed data transfer connector of real-time Transmission exchange with regard to being to provide in order to address the above problem for the purpose of this utility model.

The utility model is achieved through the following technical solutions above-mentioned purpose:

The utility model comprises arm processor and the extensive gate array of FPGA, the extensive gate array of described FPGA includes dual port RAM converter and data processor, described dual port RAM converter comprises an I/O converter, the 2nd I/O converter, first data buffer, second data buffer, first code translator, second code translator, the gate array storer, logic controller, the control bus port, data bus port and address bus port, the control bus output terminal of described arm processor and the control bus output terminal of described data processor are connected with the input end of described logic controller respectively, the output terminal of described logic controller is connected with the input end of a described I/O converter and the input end of the 2nd I/O converter respectively, the data bus port of described arm processor is connected with the FPDP of a described I/O converter, the data bus port of described data processor is connected with the FPDP of described the 2nd I/O converter, the FPDP of a described I/O converter is connected with the FPDP of described first data buffer, the FPDP of described the 2nd I/O converter is connected with the FPDP of described second data buffer, described first data buffer is connected with described gate array storer respectively with described second data buffer, the address bus port of described arm processor is connected with the input end of described first code translator, the address bus port of described data processor is connected with the input end of described second code translator, and the FPDP of the FPDP of described first code translator and described second code translator is connected with the FPDP of described gate array storer respectively.

Particularly, described first data buffer and second data buffer are the FIFO storer.

The beneficial effects of the utility model are:

The utility model has been realized the temporary and real-time exchange of data, on same interface, realize the exchange of different types of data, break away from the hardware constraints of traditional framework form when function upgrading or function expansion, have very strong function expansibility, safe and reliable, reduce maintenance cost.

Description of drawings

Fig. 1 is a structural representation of the present utility model.

Embodiment

The utility model is described in further detail below in conjunction with accompanying drawing:

As shown in Figure 1, the utility model comprises arm processor and the extensive gate array of FPGA, the extensive gate array of described FPGA includes dual port RAM converter and data processor, described dual port RAM converter comprises an I/O converter, the 2nd I/O converter, first data buffer, second data buffer, first code translator, second code translator, the gate array storer, logic controller, the control bus port, data bus port and address bus port, the control bus output terminal of described arm processor and the control bus output terminal of described data processor are connected with the input end of described logic controller respectively, the output terminal of described logic controller is connected with the input end of a described I/O converter and the input end of the 2nd I/O converter respectively, the data bus port of described arm processor is connected with the FPDP of a described I/O converter, the data bus port of described data processor is connected with the FPDP of described the 2nd I/O converter, the FPDP of a described I/O converter is connected with the FPDP of described first data buffer, the FPDP of described the 2nd I/O converter is connected with the FPDP of described second data buffer, described first data buffer is connected with described gate array storer respectively with described second data buffer, the address bus port of described arm processor is connected with the input end of described first code translator, the address bus port of described data processor is connected with the input end of described second code translator, the FPDP of the FPDP of described first code translator and described second code translator is connected with the FPDP of described gate array storer respectively, and described first data buffer and second data buffer are the FIFO storer.

The dual port RAM converter is that function served as bridge has been played in message exchange between arm processor and the FPGA, the AMR processor mainly plays the function control of equipment in entire equipment, data acquisition, the effect of data assembling, FPGA is the main time control that plays digital signal in entire equipment, the effect that the logical operation of signal is handled, by the dual port RAM converter, realized the exchange fast and effectively of information between AMR processor and the FPGA, and the control section that has guaranteed entire equipment obtains fully effectively combining with the main number signal section, and the equipment that guaranteed has been given play to its due effect under the prerequisite of safe and stable operation.

The all functions logic module of FPGA inside realizes that by extensive logic gate array able to programme the various functional modules of forming by logic gate array can cover all digital circuitry functions modules substantially.

I/O converter, its inside mainly are made up of latch cicuit, switch numbers circuit, and main effect is that the control information according to logic control element comes information or the transmission information on the readout data bus.

Data buffer, its essence are exactly a first in first out (FIFO) storer, mainly are the effects of playing metadata cache when mass data is transmitted.

Code translator, inside is digital decoder, main effect is that the address is deciphered.

The gate array storer, by the storer that a large amount of logic gates unit is formed, main effect is the storage data.

Logic controller is made up of combinational logic circuit, and main effect is the read-write of control port to storer, avoids the logic race problem of two ports to same address.

Workflow of the present utility model is: during reading of data, ARM can send control information to the dual port RAM converter according to the control timing of design in advance, address information, at first logic control element can judge that whether correctly and whether conflict arranged steering logic according to address information and control information, if steering logic is correct and not conflict, then the data of gate array storer (in the corresponding address) can be written into buffer memory, again these data are sent on the data bus by the I/O control module, ARM is by the data bus reading of data then, so just realized reading of data, the data processor of FPGA inside is also with same flow process reading of data in dual port RAM.

The AMR processor just can carry out data write to this dual port RAM converter as self a external memory storage, as long as the AMR processor writes data certain address of dual port RAM converter, other functional module of FPGA inside reads out the data in this address and has just realized the data transmission of AMR processor to FPGA then, and same mode just can realize the data transmission of FPGA to the AMR processor conversely.These are written into the data message of dual port RAM converter simultaneously, in not power down with write again and will be temporarily stored in the dual port RAM converter under the situation of new data always, this mode has reduced taking the AMR processor resource, also improve simultaneously the stability of its work operation, make the stability of entire equipment and reliability be improved.

Claims

1. high speed data transfer connector, comprise the extensive gate array of arm processor and FPGA, it is characterized in that: the extensive gate array of described FPGA comprises dual port RAM converter and data processor, described dual port RAM converter comprises an I/O converter, the 2nd I/O converter, first data buffer, second data buffer, first code translator, second code translator, the gate array storer, logic controller, the control bus port, data bus port and address bus port, the control bus output terminal of described arm processor and the control bus output terminal of described data processor are connected with the input end of described logic controller respectively, the output terminal of described logic controller is connected with the input end of a described I/O converter and the input end of the 2nd I/O converter respectively, the data bus port of described arm processor is connected with the FPDP of a described I/O converter, the data bus port of described data processor is connected with the FPDP of described the 2nd I/O converter, the FPDP of a described I/O converter is connected with the FPDP of described first data buffer, the FPDP of described the 2nd I/O converter is connected with the FPDP of described second data buffer, described first data buffer is connected with described gate array storer respectively with described second data buffer, the address bus port of described arm processor is connected with the input end of described first code translator, the address bus port of described data processor is connected with the input end of described second code translator, and the FPDP of the FPDP of described first code translator and described second code translator is connected with the FPDP of described gate array storer respectively.

2. a kind of high speed data transfer connector according to claim 1 is characterized in that: described first data buffer and second data buffer are the FIFO storer.