CN201936294U - Caching system for high-speed image acquisition system - Google Patents

Abstract

The utility model provides a cache system of a high-speed image acquisition system, which includes a cache module of FPGA and an SDRAM connected with the cache module of FPGA. The buffer module of described FPGA comprises input FIFO, controller, and output FIFO; And described controller comprises data controller and SDRAM controller; Data controller plays the data reading and writing between control input FIFO, output FIFO and SDRAM The main function of the SDRAM controller is to control the conversion of the state machine, and to pass control commands, read and write addresses (including chip selection, row selection, column selection), data masks, etc. to SDRAM. In a certain timing state, data read and write between input FIFO, output FIFO and SDRAM can be carried out continuously. Compared with the prior art, the caching system of the high-speed image acquisition system in the utility model adopts the FPGA with the advantages of small development process investment, short development cycle, and convenient repeated programming modification to design the controller of SDRAM, which is very good. The cost is reduced, and the extremely complex timing and combinational logic design required by the SDRAM in the cache system of the high-speed image acquisition system is completed through the reasonable editing and application of the internal logic of the FPGA.

Description

A cache system of high-speed image acquisition system

technical field

The utility model relates to the field of electronic circuits, in particular to a cache system of a high-speed image acquisition system.

Background technique

Because SDRAM has the advantages of large capacity and high speed, at present, the large-capacity memory of many embedded devices is realized by SDRAM, and most of these memories designed with SDRAM use dedicated chips to complete their control circuits, which not only increases the cost, Moreover, the hardware circuit of the system becomes complicated.

Utility model content

In order to solve the problems of high cost of large-capacity memory and complicated system hardware circuits in the prior art, the utility model utilizes the functions of high integration, extremely complex timing and combinational logic circuits, small investment in the development process, and short development cycle. , and can be easily repeated programming modification FPGA to design SDRAM controller, provides a high-speed image acquisition system cache system.

A cache system of a high-speed image acquisition system provided by the utility model includes a cache module of FPGA and an SDRAM connected with the cache module of FPGA.

The further work that the utility model does is: the cache module of described FPGA comprises input FIFO, controller and output FIFO; Between described input FIFO and described controller, connect with din data line; Described controller and all The SDRAMs are connected with the cs control and state connection lines and the dq bidirectional data lines; the output FIFOs are connected with the controller with the dout data lines.

The further work done by the utility model is: the controller includes a data controller and an SDRAM controller; the data controller is connected with the input FIFO with the din data line; the data controller is connected with the The said output FIFO is connected with said dout data line; said data controller is connected with said SDRAM controller with cc control and status connection line; said data controller is connected with said SDRAM with said data line The dq bidirectional data line is connected; the SDRAM controller is connected with the SDRAM with the cs control and status connection line.

The further work done by the utility model is: the cc control and state connection lines include clk clock line, cmd command control line, ready state line, addr address line, and dm data mask line; the cs control and state connection line Including sclk clock line, scmd command control line, saddr address line, and dqm data mask line.

The further work of the utility model is: the input FIFO is provided with a fin_wr signal terminal, and a fin_rd signal terminal is also provided; the output FIFO is provided with a fout_wr signal terminal, and a fout_rd signal terminal is also provided.

The further work of the utility model is: the cc control and status connection line also includes wr_en write enable signal line and rd_en read enable signal line.

Compared with the prior art, the cache system of the high-speed image acquisition system in the utility model adopts the FPGA with the advantages of small development process investment, short development cycle, and the advantages of easy repeated programming modification to design the SDRAM controller, which is very good The cost is reduced, and the extremely complex timing and combinational logic design required by the SDRAM in the cache system of the high-speed image acquisition system is completed through the reasonable editing and application of the internal logic of the FPGA.

Description of drawings

Fig. 1 is the structural composition and working logic diagram of the cache system of the high-speed image acquisition system of the present invention.

FIG. 2 is a timing diagram of reading data from SDRAM.

FIG. 3 is a schematic diagram of the timing sequence of control commands of the SDRAM controller when reading data from the SDRAM.

FIG. 4 is a timing diagram of data written into SDRAM.

FIG. 5 is a schematic diagram of the timing sequence of control commands of the SDRAM controller when writing data into the SDRAM.

Detailed ways

The utility model will be further described below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 1, the cache system of the high-speed image acquisition system in the utility model comprises the cache module 1 of FPGA, also comprises the SDRAM 2 that is connected with the cache module 1 of FPGA.

The cache module 1 of FPGA comprises input FIFO 11, controller 12, and output FIFO 13; Input FIFO 11 and controller 12 are connected with din data line, and this din data line can make data (represent this data with din) from The input FIFO 11 is unidirectionally transmitted to the controller 12; the controller 12 is connected with the SDRAM 2 with a cs control and status connection line and a dq bidirectional data line, and the cs control and status connection line can enable the system to control the setting of the SDRAM 2 Information or status information (including clock signal, command control signal, read and write address signal, status parameter signal, etc.) is unidirectionally transmitted from controller 12 to SDRAM 2, and the dq bidirectional data line can make the communication between controller 12 and SDRAM 2 Data (represented by dq) is bidirectionally transmitted; the output FIFO 13 is connected to the controller 12 with a dout data line, which enables data (represented by dout) to be transmitted unidirectionally from the controller 12 to the output FIFO13.

Controller 12 comprises data controller 121 and SDRAM controller 122; Connect with din data line between data controller 121 and input FIFO 11; Be connected with doout data line between data controller 121 and output FIFO 13; Data control The controller 121 and the SDRAM controller 122 are connected with the cc control and state connection line; the data controller 121 and the SDRAM 2 are connected with the dq bidirectional data line; the SDRAM controller 122 and the SDRAM 2 are connected with the cs control and state The control information or state information (including clock signal, command control signal, read and write address signal, state parameter signal, etc.) set by the system to SDRAM 2 needs to be transmitted from the data controller 121 through the cc control and state connection line first. Transmit to SDRAM controller 122, then transmit from SDRAM controller 122 to SDRAM 2 through cs control and status connection line; And data do not need to pass through SDRAM controller 122, can directly directly transmit between data controller 121 and SDRAM 2.

The cc control and status connection lines include the clk clock line, the cmd command control line, the ready status line, the addr address line, and the dm data mask line, which respectively transmit the clock signal of the system (the signal is represented by clk) and the decoding of the system Command signal (use cmd to represent this signal), SDRAM 2 status signal (use ready to represent this signal), read or write address signal (use addr to represent this signal), and data mask signal (use dm to represent this signal); and The cs control and status connection lines include the sclk clock line, the scmd command control line, the saddr address line, and the dqm data mask line, which respectively transmit the system clock signal (the signal is represented by sclk), the command control signal (the Signal, read or write address signal (use saddr to represent the signal), and data mask signal (use dqm to represent the signal).

The input FIFO 11 is provided with a fin_wr signal terminal and a fin_rd signal terminal. When the write enable signal read from the fin_wr signal terminal is valid (that is, fin_wr='1'), the data is read from the image sensor in the high-speed image acquisition system Write into the input FIFO 11, when the read enable signal read from the fin_rd signal terminal is valid (ie fin_rd='1'), then start to read data from the input FIFO 11 and write the data into SDRAM 2 through the data controller 121; The output FIFO 13 is provided with a fout_wr signal terminal and a fout_rd signal terminal. When the write enable signal read from the fout_wr signal terminal is valid (that is, fout_wr='1'), the data in the SDRAM is read out and passed through the data The controller 121 writes the output FIFO 13, and when the read enable signal read from the fout_rd signal terminal is valid (ie fout_rd='1'), the data of the output FIFO 13 is read and transmitted through the USB interface in the high-speed image acquisition system to the USB controller in the high-speed image acquisition system.

The cc control and status connection lines also include the wr_en write enable signal line and the rd_en read enable signal line; if the write enable signal is valid (wr_en='1'), the write operation is performed, and the data is read from the input FIFO 11 and passed through The data controller 121 writes in the SDRAM 2; if the read enable signal is valid (rd_en='1'), a read operation is performed, and the data is read from the SDRAM 2, and written into the output FIFO 13 by the data controller 121.

In order to improve the read and write efficiency of SDRAM 2, SDRAM 2 works in FULL-PAGE mode, and completes each read and write operation in units of rows, that is, one read and write command can complete 512×16bit data transmission; due to the read and write operations of SDRAM 2 It is time-sharing. For the input and output data rate of a certain frequency ν, the read and write operation clock of SDRAM 2 is greater than 2ν and the read and write operations can be successfully completed.

The working logic of the cache system of the image acquisition system of the present invention is introduced below.

Data controller 121 is a core of this design, it has played the effect of controlling the data reading and writing between input FIFO 11, output FIFO 13 and SDRAM 2, can work under two kinds of modes of file emulation mode and real-time emulation mode.

When the data controller 121 works in the file emulation mode, after the system is reset, it enters the "startup" state and waits for the initialization of the SDRAM 2. After the initialization, the ready signal of the SDRAM 2 is valid and passed to the SDRAM controller 122. If the ready signal of the SDRAM controller 122 If the signal is valid, enter the state of reading SDRAM 2, send the corresponding address, command, and status information to SDRAM 2 from the SDRAM controller 122, and set the write control signal fout_wr of the output FIFO 13 to be valid, and set the input FIFO 11 at this time The write enable signal fin_wr of the SDRAM 2 is valid; then it enters the read waiting state. When the ready signal of SDRAM 2 is valid again, it indicates that the read operation of 512×16bit has been completed, and the read control signal fout_rd of the output FIFO 13 is set to be valid, and the read from the output FIFO 13 Output data to the USB interface; since the data rate of the input FIFO 11 and the output FIFO 13 are the same, and the data input to the FIFO should be greater than 512 at this time, SDRAM 2 write operation can be performed.

When the data controller works in real-time simulation mode, after the system is reset, it enters the "startup" state. When the data input into FIFO 11 is full of 512 16bits, it enters the "init_write_sdram" state, writes SDRAM 2 once, and then continues to wait for input into FIFO 11 When 512 16 bits are full, enter the "init_write_sdram" state and continue to write data to SDRAM 2. When it is found that the data in SDRAM 2 is full, turn to the "init_read_sdram" state to read SDRAM 2 and set the output FIFO 13 to write effectively (fout_wr='1 '), after completing the read operation, the output FIFO 13 read control is valid (fout_rd='1') and enters the next read SDRAM 2 state ("read_sdram" state), when the "read_sdram" state is completed, enter the "idle" state, If it is found that the input FIFO 11 is full of 512 16bits, the input FIFO 11 read control is valid (fin_rd='1'), and SDRAM 2 is written once, and once the output FIFO 13 data is found to be less than 512, the input FIFO 11 write control is valid (fin_wr ='1'), and read SDRAM 2 once, which ensures the continuity of data.

The input FIFO 11 determines its operation by detecting the read (fin_rd) write (fin_wr) enable signal. When the write enable signal is valid (fin_wr='1'), write data into the input FIFO; when the read enable signal When it is valid (fin_rd='1'), the data written in the FIFO is more than 512 at this time, and the data is read from the input FIFO 11 and written into SDRAM 2.

Like the input FIFO 11, the output FIFO 13 also determines its operation by detecting the read (fout_rd) write (fout_wr) enable signal. When the write enable signal is valid (fout_wr='1'), the data in SDRAM 2 starts Write into the output FIFO 13; when the read enable signal is valid (fout_rd='1'), it means that the output FIFO 13 has been filled with 512×16bit data, and the data will be sent out at this time.

The SDRAM controller 122 is another core of this design, and it and the data controller 121 constitute the main body of the design. Its main function is to control the conversion of the state machine, and transmit control commands, read and write addresses (including chip selection, row selection, column selection), data mask, etc. to SDRAM 2. When the system is reset, the state machine enters the "startup" state, sets the corresponding initial value, and sends the "startup" command to SDRAM 2; then completes the power-on delay requirement in the "delay" state; after the necessary precharge and refresh commands, Then set the working mode and various parameters of SDRAM 2 in the "loadreg" state; then SDRAM 2 enters the waiting state, and in the waiting state SDRAM 2 puts the ready signal effectively and transmits it to the data controller 121, indicating that it can receive reading and writing at this time For the control command, if the read/write control signal sent by the data controller 121 is detected, the corresponding operation will be performed.

Reading and writing SDRAM 2 must meet certain timing requirements. When the data controller 121 sends an effective read enable signal (rd_en='1'), the operation of reading SDRAM 2 is executed, the read sequence is as shown in Figure 2, and the control command sequence of the SDRAM controller 122 is as shown in Figure 3; when the data What the controller 121 sends is an effective write enable signal (wr_en='1') to execute the operation of writing SDRAM 2, the write sequence is shown in Figure 4, and the control command sequence of the SDRAM controller 122 is shown in Figure 5.

The above content is a further detailed description of the utility model in combination with specific preferred embodiments, and it cannot be assumed that the specific implementation of the utility model is only limited to these descriptions. For a person of ordinary skill in the technical field to which the utility model belongs, without departing from the concept of the utility model, some simple deduction or substitutions can also be made, which should be regarded as belonging to the protection scope of the utility model.

Claims (6)

1. A buffer system of a high-speed image acquisition system, characterized in that: it comprises a buffer module of FPGA, and also includes an SDRAM connected with the buffer module of said FPGA. 2. the data cache system in the high-speed image acquisition system according to claim 1, is characterized in that: the buffer module of described FPGA comprises input FIFO, controller and output FIFO; Between described input FIFO and described controller The controller is connected with the SDRAM with a cs control and status connection line and the dq bidirectional data line; the output FIFO is connected with the controller with a dout data line . 3. the data cache system in the high-speed image acquisition system according to claim 2, is characterized in that: said controller comprises data controller and SDRAM controller; The din data line is connected; the data controller is connected with the output FIFO with the dout data line; the data controller is connected with the SDRAM controller with a cc control and status connection line ; The data controller is connected to the SDRAM with the dq bidirectional data line; the SDRAM controller is connected to the SDRAM with the cs control and status connection line. 4. the data cache system in the high-speed image acquisition system according to claim 3, is characterized in that: described cc control and status connection line comprise clk clock line, cmd command control line, ready state line, addr address line and dm data mask line; the cs control and state connection lines include sclk clock line, scmd command control line, saddr address line, and dqm data mask line. 5. the data cache system in the high-speed image acquisition system according to claim 2 is characterized in that: the input FIFO is provided with a fin_wr signal terminal, and is also provided with a fin_rd signal terminal; the described output FIFO is provided with a fout_wr signal The terminal is also provided with a fout_rd signal terminal. 6. The data cache system in the high-speed image acquisition system according to claim 2, characterized in that: the cc control and status connection lines further include wr_en write enable signal line and rd_en read enable signal line.

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