CN100357870C - Method of proceeding access multikind storage on chip select outer unibus - Google Patents

Abstract

The invention discloses a method for accessing a variety of memories connected to an off-chip single bus, and aims to provide a method for accessing a variety of memories connected to an off-chip single bus. The technical solution is to divide the memory access address range into M subspaces, and each subspace corresponds to a memory; design a single-bus memory interface, set M chip select signals on the interface, and each chip select signal is connected to a memory; The memory interface integrates a decoding unit, a control register group, M types of memory controllers and a crossbar switch to realize the configuration of various memory parameters, the decoding of chip select signals and the generation of bus signals. Through the selection of bus signals Realize the access to M kinds of memories connected to the single bus at the same time. After adopting the invention, the embedded microprocessor can access various memories connected outside the chip through a single bus, thereby reducing the power consumption and area of this type of microprocessor, and reducing the number of pins.

Description

Method for accessing various memories attached to off-chip single bus

Technical field: the present invention relates to embedded microprocessor and SoC (System on Chip, system on a chip), the method for accessing multiple memory devices connected on the single bus outside the chip.

BACKGROUND OF THE INVENTION: In a general-purpose CPU, the memory control components responsible for exchanging data with external memories are implemented by bridge chips on the motherboard. In embedded microprocessors, such as DSP (Digital Signal Processor, digital signal processor), ASIC (Application Specific Integrated Circuit, application specific integrated circuit), and some SoCs, memory control components are often combined with CPU core, DMA (Direct Memory Access, direct memory access) and other components are integrated on a chip, and directly exchange data with the memory through an external bus. This storage control unit responsible for accessing off-chip memory is also called a memory interface. The method of integrating the memory interface and the CPU core on the same chip can effectively improve the data throughput bandwidth, reduce system power consumption, and reduce the interference of on-board wiring on high-speed signal transmission. However, in embedded applications, the system often needs to connect multiple memories at the same time, such as SDRAM or SBSRAM for high-speed data buffering, Flash or ROM for storing user programs, and FIFO for data exchange. The memory interface responds to the memory access request of the DMA internally, and accesses different memories externally. These memories are read and written in different ways, and the address range of each kind of memory is also different. The conventional implementation method is to design a storage control unit for each type of memory in the chip, and set a read-write bus for each type of memory in the chip pins. But this method will greatly increase the power consumption, area and number of pins of the chip, and embedded applications often require microprocessors to have lower power consumption, smaller area and fewer pins. How to access multiple memories connected simultaneously on a single bus is an important problem to be solved urgently in the design of this type of microprocessor. The "single bus" mentioned here refers to the only set of memory access bus including address, data, read/write enable and other memory control signals.

Invention content:

The technical problem to be solved by the present invention is to propose a method for accessing various memories connected to an off-chip single bus for the embedded application system that needs to connect and access various memories, so that the embedded micro The processor can access a variety of memories connected outside the chip through a single bus, overcome the shortcomings of the traditional method of using multiple buses to access a variety of memories, reduce the power consumption and area of this type of microprocessor, and reduce the number of pins .

The technical solution is to divide the memory access address range into M subspaces, and each subspace corresponds to a kind of memory. A single-bus memory interface is designed in an embedded microprocessor, and M chip selection signals are set on the interface, and each chip selection signal is connected to a memory. The memory interface integrates a decoding unit, a control register group, M types of memory controllers and a crossbar switch to realize the configuration of various memory parameters, the decoding of chip select signals and the generation of bus signals. Through the selection of bus signals The goal of accessing M kinds of memories connected simultaneously on the single bus is realized.

The specific technical solutions are:

Firstly, the access address range is divided. If M types of memories are connected to the external bus at the same time, the entire memory access address range is divided into M subspaces, and each subspace corresponds to a memory. When dividing the address subspace, start dividing from the MSB (Most Significant Bit) of the address. If the capacity of each memory is different, the size of each divided subspace is different, that is, it is divided unevenly; if the total address range is large enough, after being evenly divided into M subspaces, the size of each subspace can meet the capacity of the corresponding memory. The uniform division is performed, that is, the total address range is evenly divided into M subspaces, which is convenient for the decoding unit to perform decoding. Where M is an integer greater than or equal to 1.

The design method of the single-bus memory interface is: it is composed of a decoding unit, a control register group, M types of memory controllers, and a crossbar switch. The decoding unit is connected with the DMA, the control register group, the storage controller and the crossbar switch, receives the memory access request signal, address signal and control parameters of the control register group of the DMA, decodes the memory access request information, and generates M chip selects The signal is output to the crossbar switch, and the generated read/write start command signal and read/write times signal are output to the storage controller; the control register group is connected to the CPU core through the CPU configuration bus, accepts the CPU to check the configuration of various memory parameters, and sends to the The decoding unit and the storage controller send control parameters; the storage controller receives the data signal for DMA access, the address signal, the read/write command and the read/write times signal generated by the decoding unit, the control parameter signal of the control register group, and generates Read/write the data and control signals (address, read/write enable, output enable, etc.) required by the corresponding memory, and send these signals to the crossbar switch. is M, then the number of storage controllers is also M. The crossbar is internally connected with M chip select signals and bus signals generated by M memory controllers, and externally connected with M types of memories through an off-chip single bus.

The decoding unit is composed of a chip selection signal decoding module, a read/write signal decoding module and a read/write times decoding module. Since the memory interface contains M chip select signals, and each chip select signal is connected to a memory, when the chip select signal decoding module decodes the high bits of the DMA memory access address, it judges the subspace to which the address belongs, and then Activate one of the corresponding M chip select signals to select the corresponding memory on the off-chip single bus; the read/write signal decoding module decodes according to the high bit of the memory access address and the memory access request, and judges the memory to be read and written The memory sends a corresponding read/write start command signal to the corresponding storage controller to start the read/write process of the storage controller. The reading and writing times decoding module performs decoding according to the memory access data width and the memory width parameter sent by the control register group, and generates a read/write times signal. If the data width to be accessed is greater than the configured memory width in the corresponding control register, the read/write times signal will be greater than 1, which is used to indicate the operation of the corresponding memory controller. For example, if the data width of a certain read request is 32 bits, but the width of the corresponding memory is only 16 bits, then the decoding unit will decode and generate a read count signal with a size of 2, and the memory controller will follow this signal from 16-bit data is read out from two consecutive addresses of the corresponding memory, combined into 32-bit data, and returned to the DMA. Assuming that the maximum value of the access data width is S times the minimum width among the M memory widths, and S is an integer power of 2, then the width of the read/write times signal should be set to log ₂ S bits.

The control register group includes a decoding circuit and M groups of control registers. Each group of control registers contains several registers, which are used to configure the control parameters of a memory, such as the width and type of the memory, the setup/trigger/hold time of the asynchronous memory, Parameters such as the number of row/column/body addresses of the SDRAM memory. The type and number of parameters increase or decrease according to the needs of the actual memory. If a certain type of memory requires less control parameters and one control register can represent all the parameters, then only one control register needs to be set in the corresponding control register group. If multiple control registers must be used to represent all the control parameters, multiple control registers need to be set in the corresponding control register group. The bit width of each control register is generally set to the word length of the microprocessor, and corresponds to a global logical address. The CPU reads/writes the control parameters of each control register through the configuration bus. When reading/writing, the decoding circuit decodes the reading/writing address and reading/writing command sent from the configuration bus to generate a command signal for reading/writing the corresponding control register. The control register accepts the command signal of the decoding circuit: if it is a write parameter command, write the data sent from the configuration bus into the corresponding field of the register; if it is a read parameter command, output the data in its corresponding field to the configuration bus , while giving a data-ready signal. Each memory controller in the memory interface uses a published standard design methodology. The read/write start command generated by the decoding unit only activates the controller of one kind of memory each time, and the other memory controllers will not respond. The activated memory controller generates valid data and control signals required to read/write the corresponding memory, and the remaining memory controllers generate invalid data and control signals.

The crossbar is a group of selection logic circuits, which are composed of M multiple selectors. According to M chip selection signals, it performs multi-select operation on the data and control signals sent by each storage controller. If the i-th (1≤i≤M) chip select signal is valid, select the data and control signals generated by the i-th memory controller (that is, the activated memory controller), output to the external bus, and output M A chip select signal.

The method for using the above-mentioned memory interface to access multiple memories connected to the off-chip single bus is: before starting memory access, the CPU writes the control parameters of various memories into the control register group through the configuration bus. During memory access, the decoding unit decodes the memory access address, memory access request and memory access data width according to the control parameters provided by the control register group, activates one of the M chip select signals, and simultaneously generates effective read/write The start command signal and the read/write times signal are output to the storage controller. Since each memory access only accesses one of the memories, only one corresponding memory controller is activated by the read/write start command of the decoding unit, and the rest of the memory controllers do not respond. The activated memory controller generates data and control signals that meet the timing requirements of the corresponding memory according to the memory access data, address and control parameters, and outputs them to the crossbar. The crossbar selects the data and control signals generated by the corresponding memory controller according to the M chip selection signals, and outputs them to the external bus. The memory selected by the effective chip select signal responds to the signal on the external bus to complete the memory access operation. Other memories not selected by the chip select signal do not respond to external bus signals. In this way, the goal of accessing multiple memories connected simultaneously on the single bus is realized.

If it is necessary to increase/decrease the type of memory, it is only necessary to increase/decrease the corresponding control register, chip select signal, memory controller and switch selection logic.

Adopting the present invention can produce following beneficial technical effect:

1. All memories reuse a set of external buses, reducing the number of chip pins in the original multi-bus mode, reducing chip power consumption and area;

2. According to the needs of different applications for memory types, the present invention has good scalability and tailorability:

3. The present invention adopts a standard module interface and has good module reusability.

Description of drawings:

Figure 1 is a general logic structure diagram of embedded microprocessor application system.

FIG. 2 is a logical structure diagram of the single-bus memory interface of the present invention.

Fig. 3 is a logical structure diagram of the decoding unit of the present invention.

Fig. 4 is a structural diagram of the control register group of the present invention.

Fig. 5 is the interconnection instance that the memory interface of the present invention is connected with a slice of 32-bit wide SDRAM and a slice of 16-bit Flash at the same time.

Detailed ways:

Figure 1 is a general embedded microprocessor application system. A memory interface of the present invention is integrated inside the microprocessor. In this example, four different memories including SDRAM, SBSRAM, FIFO and Flash are connected to the external bus of the memory interface at the same time.

Figure 2 is a logical structure diagram of a single-bus memory interface connected to commonly used SDRAM, SBSRAM, FIFO, and Flash memories. The single-bus memory interface is composed of a decoding unit, a control register group, 4 memory controllers and a crossbar switch. The decoding unit receives the memory access request signal of the DMA, the control register group is connected to the configuration bus of the CPU, and the crossbar is connected to four kinds of memories through the off-chip single bus. Before starting to access the memory, the CPU writes the control parameters of the four kinds of memory into the control register group through the configuration bus. During memory access, the decoding unit decodes the memory access address, memory access request and memory access data width according to the control parameters provided by the control register group, activates one of the four chip select signals, and simultaneously generates effective read/write The start command signal and the read/write times indication signal are output to the storage controller. Since each memory access only accesses one of the memories, only one corresponding memory controller is activated by the read/write start command of the decoding unit, and the rest of the memory controllers do not respond. The activated memory controller generates data and control signals that meet the timing requirements of the corresponding memory according to the memory access data, address and control parameters, and outputs them to the crossbar. The crossbar is a four-select-one logic, which selects the data and control signals generated by one of the memory controllers according to the four chip select signals, and outputs them to the external bus. The memory selected by the effective chip select signal responds to the signal on the external bus to complete the memory access operation.

Fig. 3 shows the composition structure of the decoding unit of the present invention. This figure still takes four commonly used memories of SDRAM, SBSRAM, FIFO, and Flash as examples. Assuming that the memory access address length is n bits, and after being divided into 4 subspaces, the 4 subspaces can be distinguished according to the nth bit and the n-1th bit address, the "chip select signal decoding" module can use a 2-4 Decoder to realize, decode and output 4 stored chip select signals. The "read and write signal decoding" module generates 4 memory read/write start command signals after decoding according to the nth and n-1th address and the read/write request signal. The "reading and writing times decoding" module decodes according to the memory access data width signal and the memory width parameters sent by the 4 control registers, and generates the reading/writing times signal, which is used to indicate the reading and writing process of the storage controller. Assuming that the maximum value of the access data width is S times the minimum width of the 4 memory widths (S is generally an integer power of 2), then the width of the read/write times signal should be set to log ₂ S bits. For example, the maximum width of the access data is 64 bits, and the minimum width of the external memory is 8 bits, then S is equal to 8, and the width of the read/write times signal should be set to 3 bits.

如果某种存储器的控制参数较多，使用一个控制寄存器无法完全表示，那么可以用多个控制寄存器配置一种存储器的参数。图4中用来配置SDRAM参数的R1组就使用了2个控制寄存器。每个控制寄存器都具有一个全局地址，CPU通过配置总线即可对各个控制寄存器的控制参数进行读/写。在读/写时，译码电路对配置总线上送来的读/写地址、读/写命令进行译码，产生读/写相应控制寄存器的命令信号。控制寄存器接受译码电路的命令信号：如果是写参数命令，则把配置总线上送来的数据写入寄存器的相应字段；如果是读参数命令，则把自己相应字段的数据输出到配置总线上，同时给出数据准备好信号。FIG. 4 shows a logical structure diagram of the control register group of the present invention. Still taking the four commonly used memories of SDRAM, SBSRAM, FIFO, and Flash as examples, the control register group is composed of a decoding circuit and four groups of control registers. The example in the figure contains four groups of control registers, and gives the detailed field structure of each group of control registers, which are used to configure the control parameters of SDRAM, SBSRAM, FIFO and Flash respectively. Among them, R1 is a control register group for configuring SDRAM control parameters, which contains two 32-bit registers, which are used to configure control parameters such as burst mode, CAS response beat, refresh enable, and refresh cycle. R2 is the control register group of SBSRAM, which only contains a 32-bit register. R3 is the control register group of FIFO, R4 is the control register group of Flash, each has only one 32-bit control register. Divide the control register into multiple fields, each field is used to set a parameter, and the length of the field depends on the complexity of the parameters. If there are n cases of this parameter, then the number of bits B required for this field should satisfy

If there are many control parameters of a certain type of memory, which cannot be fully represented by one control register, then multiple control registers can be used to configure the parameters of a type of memory. The R1 group used to configure SDRAM parameters in Figure 4 uses two control registers. Each control register has a global address, and the CPU can read/write the control parameters of each control register by configuring the bus. When reading/writing, the decoding circuit decodes the reading/writing address and reading/writing command sent from the configuration bus to generate a command signal for reading/writing the corresponding control register. The control register accepts the command signal of the decoding circuit: if it is a write parameter command, write the data sent from the configuration bus into the corresponding field of the register; if it is a read parameter command, output the data in its corresponding field to the configuration bus , while giving a data-ready signal.

FIG. 5 shows a schematic diagram of a 32-bit wide SDRAM and a 16-bit wide Flash connected simultaneously to the memory interface of the present invention through an external bus.

At present, the present invention has been adopted in the 32-bit high-performance floating-point DSP "Galaxy Feiteng-DSP700" independently developed by the University of National Defense Science and Technology. The DSP can be connected to 4 different memories on the off-chip single bus at the same time.

Claims (6)

1. the method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews is characterized in that the memory access address realm is divided into the M sub spaces, the corresponding a kind of storer in each subspace; A kind of unibus memory interface of design is provided with the M silver and selects signal on interface in embedded microprocessor, and each chip selection signal connects a kind of storer; The inner integrated decoding unit of memory interface, control register group, M kind memory controller and a cross bar switch, decoding unit links to each other with DMA, receive the controlled variable of memory access request signal, address signal and the control register group of DMA, the memory access solicited message is deciphered, produce M chip selection signal and export to cross bar switch, the read/write start up command signals of generation and read-write number of times signal are exported to memory controller; The control register group connects by configuration bus and the CPU nuclear phase of CPU, accepts the configuration that CPU checks various memory parameter, and sends controlled variable to decoding unit and memory controller; The controlled variable signal of read/write command that data-signal, address signal, the decoding unit of memory controller reception DMA memory access produces and read/write number of times signal, control register group, produce required data and the control signal of read/write respective memory, and these signals are delivered to cross bar switch, the number of memory controller is consistent with the storer kind, if the storer kind is M, then the number of memory controller also is M; Cross bar switch internally connects the M silver and selects signal and M the bus signals that memory controller produces, and externally articulates M kind storer by the outer unibus of sheet; Realize the configuration of each memory parameter, the decoding of chip selection signal and the generation of bus signals by memory interface, realize the target that the M kind storer that articulates simultaneously on the unibus is conducted interviews by selection bus signals; Wherein M is the integer more than or equal to 1.

2. the method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews as claimed in claim 1, it is characterized in that the method that the memory access address realm is divided being: if external bus articulates M kind storer simultaneously, then whole memory access address realm is divided into the M sub spaces, the corresponding storer in each subspace, begin to divide from the highest significant position MSB of address, if the capacity difference of each storer, each sub spaces of being divided varies in size, and promptly carries out inhomogeneous division; If total address realm is enough big, evenly be divided into the M sub spaces after, the size of each subspace can both satisfy the capacity of respective memory, then evenly divides, and is about to total address realm and evenly is divided into the M sub spaces.

3. the method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews as claimed in claim 1 is characterized in that described decoding unit is made of chip selection signal decoding module, read/write signal decoding module and read-write number of times decoding module; When the chip selection signal decoding module is deciphered the high position of DMA memory access address, judge the subspace that this address is affiliated, activate in the corresponding M chip selection signal then, be used to choose corresponding memory on the outer unibus of sheet; The read/write signal decoding module is deciphered according to a high position and the memory access request of memory access address, judges the storer that will read and write, sends corresponding read/write start up command signals and gives corresponding memory controller, starts the read/write processes of memory controller; The memory width parameter that read-write number of times decoding module is sent here according to memory access data width and control register group is deciphered, and produces read/write number of times signal; If the data width of memory access is greater than the memory width that has disposed in the corresponding control register, read/write number of times signal will be used to indicate the operation of respective stored controller greater than 1; If the maximal value of memory access data width is S times of minimum widith in M the memory width, S is 2 integral number power, and the width of read/write number of times signal should be made as log so ₂The S position.

4. the method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews as claimed in claim 1, it is characterized in that described control register group comprises decoding scheme and M group control register, comprise several registers in every group of control register, be used to dispose a kind of controlled variable of storer, the type of parameter and number are according to the needs increase and decrease of actual storage; The bit wide of each control register is traditionally arranged to be the word length of microprocessor, simultaneously corresponding global logic address; CPU carries out read/write by configuration bus to the controlled variable of each control register; When read/write, decoding scheme is deciphered read/write address, the read/write command sent here on the configuration bus, produces the command signal of the corresponding control register of read/write; Control register is accepted the command signal of decoding scheme: if the write parameters order, then the data of sending here on the configuration bus are write the respective field of register; If read parameter command, then the data of own respective field are outputed on the configuration bus, provide ready for data signal simultaneously.

5. the method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews as claimed in claim 1, it is characterized in that described cross bar switch is a group selection logical circuit, constitute by M road multi-selection device, data and control signal that it is sent here each memory controller according to M chip selection signal are carried out multiselect one operation, if i chip selection signal is effective, data and control signal that the memory controller of then selecting i memory controller promptly to be activated produces, output on the external bus, also export M chip selection signal simultaneously, wherein 1≤i≤M.

6. the method that the multiple storer that is articulated on the outer unibus of sheet is conducted interviews as claimed in claim 1, it is characterized in that utilizing described memory interface to the method that a plurality of storeies that are articulated on the outer unibus of sheet conduct interviews to be: before the beginning memory access, CPU writes the control register group by configuration bus with the controlled variable of various storeies; When memory access, decoding unit is deciphered memory access address, memory access request and memory access data width according to the controlled variable that the control register group provides, activation M silver selects in the signal, produces effective read/write start up command signals and read/write number of times signal simultaneously, exports to memory controller; Because wherein a kind of storer is only visited in each memory access, therefore have only the read/write startup command of a corresponding decoded unit of memory controller to activate, remaining memory controller does not respond; The memory controller that is activated produces the data and the control signal that meet the requirement of respective memory sequential according to memory access data, address and controlled variable, exports to cross bar switch; Cross bar switch selects signal according to the M silver, and data and the control signal of selecting the respective stored controller to produce output on the external bus; Signal on the memory response external bus that the effective chip selection signal of quilt is chosen is finished accessing operation; Other storeies of not chosen by chip selection signal are the response external bus signals not.

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