CN201766073U - Lead frame and its packaging structure that can strengthen the bonding degree of sealing glue - Google Patents
Lead frame and its packaging structure that can strengthen the bonding degree of sealing glue Download PDFInfo
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- CN201766073U CN201766073U CN 201020189142 CN201020189142U CN201766073U CN 201766073 U CN201766073 U CN 201766073U CN 201020189142 CN201020189142 CN 201020189142 CN 201020189142 U CN201020189142 U CN 201020189142U CN 201766073 U CN201766073 U CN 201766073U
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- 238000007789 sealing Methods 0.000 title claims abstract description 26
- 239000003292 glue Substances 0.000 title abstract description 14
- 238000004806 packaging method and process Methods 0.000 title abstract description 10
- 238000005728 strengthening Methods 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 230000021615 conjugation Effects 0.000 claims 12
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 239000000565 sealant Substances 0.000 description 15
- 238000000034 method Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 230000032798 delamination Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
技术领域technical field
本实用新型是关于一种可强化封胶接合度的导线架及其封装结构,尤指一种适用于强化封胶层与导线架的接合强度的导线架及其封装结构。The utility model relates to a lead frame and its packaging structure capable of strengthening the bonding degree of sealing glue, in particular to a lead frame and its packaging structure suitable for strengthening the joint strength of the sealing glue layer and the lead frame.
背景技术Background technique
请参阅图1,图1是已知半导体封装件的剖面示意图。如图中所示,于已知导线架9上固设半导体芯片91,并以金线92电性连接。再者,通过封胶93包覆半导体芯片91、金线92、及已知导线架9,以达保护、及绝缘的功效。然而,随着科技不断地发展,电子元件也不断地朝向轻、薄、短、小的趋势急速发展。因此,因应电子元件体积不断缩小的趋势,导线架9亦不断缩小其体积,而导线架9与封胶93接触面积便逐渐受限。Please refer to FIG. 1 . FIG. 1 is a schematic cross-sectional view of a known semiconductor package. As shown in the figure, a
据此,因已知导线架9与封胶93接触部位平滑,且因应趋势而接触面积锐减的情况下,其接合的强度便大大降低,进而增加导线架9与封胶93脱层(Delamination)现象,甚至造成切单(Singulation)后导脚脱落,造成严重影响工艺良率。尤其,QFN(Quad Flat Non-lead)封装件逐渐成为封装工艺主流,QFN封装件特征在于,其未设置有外导脚,亦即未形成有如已知四边形平面(QFP)半导体封装件中用以与外界电性连接的外导脚。如此,QFN封装件又得以缩小半导体封装件的尺寸,但导线架与封胶脱层现象亦趋严重。Accordingly, since it is known that the contact portion between the
请参阅图2,图2是另一已知半导体封装件的剖面示意图。再者,随着工艺技术不断的进步,目前又发展有T形或倒L形的已知导线架94,其特征在于可通过T形或倒L形凸伸平台95来增加导线架94与封胶96的接合强度。然而,此一方式虽能加强接合强度,但其仍显不足,仍易产生脱层情况。Please refer to FIG. 2 , which is a schematic cross-sectional view of another known semiconductor package. Furthermore, with the continuous improvement of technology, there is a T-shaped or inverted L-shaped known
实用新型内容Utility model content
本实用新型一种可强化封胶接合度的导线架,包括:一芯片座、及一接脚架。其中,芯片座是包括有一芯片承载台、及一底座。芯片承载台包括有一侧凸部,其是凸伸出底座外,侧凸部包括有一下表面,底座包括有一侧壁,而下表面与侧壁相交于一内线,且下表面上向凹设有一凹槽。其凹槽是邻接于内线,又凹槽沿内线的至少一部份延伸。The utility model relates to a lead frame capable of strengthening the bonding degree of sealing glue, comprising: a chip seat and a tripod. Wherein, the chip seat includes a chip carrying platform and a base. The chip carrying platform includes a side convex portion, which protrudes out of the base, the side convex portion includes a lower surface, the base includes a side wall, and the lower surface and the side wall intersect on an inner line, and the lower surface is concavely provided with a groove. The groove is adjacent to the inner wire, and the groove extends along at least a part of the inner wire.
再者,接脚架是包括有一接脚台、及一底架。其中,接脚台包括有一凸缘部,其是凸伸出底架外,凸缘部包括有一下表面,底架包括有一侧壁。而下表面与侧壁相交于一接线,且下表面上凹设有一凹沟。其凹沟是邻接于接线,又凹沟沿接线的至少一部份延伸。因此,本实用新型由侧凸部、凸缘部、凹槽与凹沟的设置,能大幅提高导线架与封胶的接触面积,进而显着提升接合强度,减少封胶脱层情况。Furthermore, the stand includes a stand and a bottom frame. Wherein, the foot platform includes a flange portion protruding out of the bottom frame, the flange portion includes a lower surface, and the bottom frame includes a side wall. The lower surface intersects with the side wall at a line, and a concave groove is formed on the lower surface. The groove is adjacent to the wiring, and the groove extends along at least a part of the wiring. Therefore, the utility model can greatly increase the contact area between the lead frame and the sealant by setting the side protrusions, flanges, grooves and grooves, thereby significantly improving the joint strength and reducing the delamination of the sealant.
其中,本实用新型可强化封胶接合度的导线架的凹槽、及凹沟可具有相同的深度,当然亦可不同深度。此外,本实用新型的凹槽、及凹沟的深度可通过工艺条件加以控制其深浅,进而由此可更进一步调整导线架与封胶接合的抓紧力,以达最佳的固持力。再且,本实用新型可强化封胶接合度的导线架的接脚架的接脚台上布设有至少一金属接脚,其是用以电性连接芯片。Wherein, the grooves and grooves of the lead frame which can strengthen the joint degree of the sealant of the present invention can have the same depth, of course, they can also have different depths. In addition, the depths of the grooves and grooves of the present invention can be controlled by technological conditions, and thus the gripping force of the joint between the lead frame and the sealant can be further adjusted to achieve the best holding force. Furthermore, at least one metal pin is arranged on the pin platform of the pin frame of the lead frame which can strengthen the adhesive bonding degree of the present invention, which is used for electrically connecting the chip.
另外,本实用新型可强化封胶接合度的导线架的凹槽、及凹沟可分别为一弧形沟槽,而弧形沟槽又可为一半圆弧沟槽。但本实用新型的弧形沟槽又非以半圆弧为限,其亦可为四分的三圆弧沟槽、椭圆弧沟槽、或其它圆弧形状皆可。此外,本实用新型的凹槽、及凹沟亦可分别为一多边形沟槽,如梯形沟槽、三角形沟槽、矩形沟槽、锥形沟槽、或其它等效多边形沟槽等。In addition, in the utility model, the groove and groove of the lead frame which can strengthen the joint degree of sealing glue can be an arc-shaped groove respectively, and the arc-shaped groove can be a half-arc groove. However, the arc-shaped groove of the present invention is not limited to a semi-circular arc, and it can also be a quarter-divided three-arc groove, an elliptical arc groove, or other arc shapes. In addition, the groove and groove of the present invention can also be a polygonal groove, such as a trapezoidal groove, a triangular groove, a rectangular groove, a tapered groove, or other equivalent polygonal grooves.
本实用新型的另一态样为一种可强化封胶接合度的封装结构,包括:一导线架、一芯片、至少一焊线、及一封胶体。其中,导线架是包括一芯片座、及一接脚架。且芯片座包括有一芯片承载台、及一底座。芯片承载台包括有一下表面,底座包括有一侧壁,而其下表面与侧壁相交于一内线,且下表面上凹设有一凹槽。其中,凹槽是邻接于内线,又凹槽沿内线的至少一部份延伸。Another aspect of the present invention is a packaging structure capable of strengthening the bonding degree of sealing glue, including: a lead frame, a chip, at least one bonding wire, and sealing glue. Wherein, the lead frame includes a chip seat and a socket frame. And the chip seat includes a chip carrying platform and a base. The chip carrying platform includes a lower surface, the base includes a side wall, and the lower surface and the side wall intersect on an inner line, and a groove is recessed on the lower surface. Wherein, the groove is adjacent to the inner wire, and the groove extends along at least a part of the inner wire.
至于,本实用新型的接脚架包括有一接脚台、及一底架。接脚台包括有一下表面,底架包括有一侧壁,且下表面与侧壁相交于一接线。而下表面上凹设有一凹沟,且凹沟是邻接于接线,又凹沟沿接线的至少一部份延伸。再且,接脚架的接脚台上布设有至少一金属接脚。As for, the socket frame of the present utility model includes a socket platform and a bottom frame. The pin table includes a lower surface, the bottom frame includes a side wall, and the lower surface and the side wall intersect at a wiring. A groove is recessed on the lower surface, and the groove is adjacent to the wiring, and the groove extends along at least a part of the wiring. Furthermore, at least one metal pin is arranged on the pin platform of the pin frame.
再者,本实用新型的芯片是固设于芯片承载台上,芯片的上表面包括有至少一焊垫。此外,本实用新型的至少一焊线是电性连接芯片的至少一焊垫与接脚架的至少一金属接脚。然而,本实用新型的封胶体是包覆芯片、至少一焊线、及导线架的部分并填满凹槽、及凹沟。据此,本实用新型由侧凸部、凸缘部、凹槽、及凹沟来增加导线架与封胶体的接合强度。Moreover, the chip of the present invention is fixed on the chip carrying platform, and the upper surface of the chip includes at least one welding pad. In addition, the at least one bonding wire of the present invention is to electrically connect at least one bonding pad of the chip and at least one metal pin of the stand. However, the encapsulant of the present invention covers the part of the chip, at least one bonding wire, and the lead frame, and fills the grooves and grooves. Accordingly, the utility model increases the bonding strength between the lead frame and the sealant through the side protrusions, flanges, grooves, and grooves.
此外,本实用新型的芯片可固设于芯片承载台上并对应于底座处,且未凸伸出底座的侧壁外,其主要是因芯片于粘晶工艺时,下方的芯片承载台需承受较大的承载应力。据此,本实用新型的芯片较佳未凸伸出底座的侧壁外,且未位于凹槽的正上方。如此,将可避免下方侧凸部、或凹槽因承受过度的承载应力导致弯曲或断裂。另外,本实用新型的至少一焊线是电性连接芯片的至少一焊垫与接脚架位于底架上方的至少一金属接脚上,且较佳未位于凹沟的正上方。同样地,为避免于打线工艺时,过度的承载应力导致凸缘弯曲或断裂。In addition, the chip of the present invention can be fixed on the chip carrier corresponding to the base, and does not protrude out of the side wall of the base. This is mainly because the chip carrier below needs to bear greater bearing stress. Accordingly, the chip of the present invention preferably does not protrude out of the side wall of the base, and is not located directly above the groove. In this way, it is possible to avoid bending or breaking of the lower side protrusions or grooves due to excessive bearing stress. In addition, the at least one bonding wire of the present invention is electrically connected to at least one bonding pad of the chip and the at least one metal pin on the bottom frame, and is preferably not directly above the groove. Likewise, in order to avoid excessive bearing stress during the wire bonding process, the flanges will be bent or broken.
本实用新型的有益效果是:能大幅提高导线架与封胶的接合强度,减少封胶脱层的情况。The beneficial effect of the utility model is that the bonding strength between the lead frame and the sealant can be greatly improved, and the delamination of the sealant can be reduced.
附图说明Description of drawings
为使审查员能对本实用新型目的、技术特征及其功效,做更进一步的认识与了解,以下结合实施例配合附图,详细说明如下,其中:In order to enable the examiner to further understand and understand the purpose, technical features and effects of the utility model, the detailed description is as follows in conjunction with the embodiments and accompanying drawings, among which:
图1A是已知半导体封装件的剖面示意图。FIG. 1A is a schematic cross-sectional view of a known semiconductor package.
图1B是另一已知半导体封装件的剖面示意图。FIG. 1B is a schematic cross-sectional view of another known semiconductor package.
图2是本实用新型第一实施例的俯视图。Fig. 2 is a top view of the first embodiment of the utility model.
图3A是本实用新型第一实施例的剖视图。Fig. 3A is a cross-sectional view of the first embodiment of the present invention.
图3B是本实用新型第一实施例剖视图的局部放大图。Fig. 3B is a partially enlarged view of the cross-sectional view of the first embodiment of the present invention.
图4是本实用新型第二实施例的剖视图。Fig. 4 is a cross-sectional view of the second embodiment of the present invention.
图5是本实用新型第三实施例的剖视图。Fig. 5 is a sectional view of the third embodiment of the present invention.
图6是本实用新型第四实施例的剖视图。Fig. 6 is a sectional view of the fourth embodiment of the present utility model.
图7是本实用新型第五实施例的剖视图。Fig. 7 is a sectional view of the fifth embodiment of the present utility model.
图8是本实用新型第六实施例的剖视图。Fig. 8 is a sectional view of the sixth embodiment of the present utility model.
具体实施方式Detailed ways
请同时参阅图2、图3A、及图3B,图2是本实用新型可强化封胶接合度的封装结构的第一实施例的俯视图,图3A是本实用新型第一实施例封装结构的剖视图,图3B是本实用新型第一实施例封装结构剖视图的局部放大图。图中主要显示有一导线架1、一芯片4、多条焊线5、及一封胶体6。Please refer to FIG. 2, FIG. 3A, and FIG. 3B at the same time. FIG. 2 is a top view of the first embodiment of the packaging structure of the utility model that can strengthen the bonding degree of sealing glue, and FIG. 3A is a cross-sectional view of the packaging structure of the first embodiment of the utility model. , FIG. 3B is a partial enlarged view of the cross-sectional view of the package structure of the first embodiment of the present invention. The figure mainly shows a lead frame 1, a
其中,导线架1是包括一芯片座2、及一接脚架3。而芯片座2包括有一芯片承载台21、及一底座22,芯片承载台21是一体连接于底座22上方,并于侧边凸伸底座22的侧壁221外有一侧凸部210,而侧凸部210又包括有一下表面211。另外,下表面211与侧壁221相交于一内线24,亦即下表面211与侧壁221相连接于内线24。此外,下表面211向上凹设有一凹槽23,其是邻接于内线24,且凹槽23沿内线24延伸。Wherein, the lead frame 1 includes a
再者,图中另显示有一接脚架3,其包括有一接脚台31、及一底架32。接脚台31包括有一下表面311,底架32包括有一侧壁321。同样地,接脚台31是一体连接于底架32上方并凸伸于底架32的侧壁321外有一凸缘部310。此外,凸缘部310的下表面311与底架32的侧壁321相交于一接线37,亦即下表面311与侧壁321相连接于接线37。另外,下表面311上向凹设有一凹沟33,其是邻接于接线37,且凹沟33沿接线37。再且,本实施例的接脚架3的接脚台31上布设有一金属接脚34,其常以银或铅为材质,完整镀附于接脚台31的上表面上。Furthermore, the figure also shows a
在本实施例中,凹槽23、及凹沟33是利用蚀刻方式制成,且其皆具一深度D。据此,通过工艺条件的设定可控制其深浅,进而由此可更进一步调整抓紧力,以达最佳的固持力。再者,本实施例的凹槽23、及凹沟33是分别沿整条内线24、及接线37延伸开设。然而,凹槽23、及凹沟33亦可采用激光工艺、或其它等效工艺,故凹槽23、及凹沟33亦可采区段式的分别沿内线24及接线37的至少一部份延伸进行布设。再且,在本实施例中,凹槽23、及凹沟33分别为一弧形沟槽20,且为半圆弧沟槽30。In this embodiment, the groove 23 and the groove 33 are formed by etching, and both have a depth D. As shown in FIG. Accordingly, the depth can be controlled by setting the process conditions, and thus the gripping force can be further adjusted to achieve the best holding force. Furthermore, the groove 23 and the groove 33 in this embodiment extend along the entire
另外,图中另显示一芯片4,是固设于芯片座2的芯片承载台21上,且芯片4的上表面41包括有多个焊垫411。本实施例中,芯片4是固设于芯片承载台21上并对应于底座22处,且未凸伸出底座22的侧壁221外,并未位于凹槽23的正上方。主要是因芯片4于粘晶工艺时,下方的芯片承载台21需承受较大的承载应力,如此设置将可避免下方侧凸部210、或凹槽23处因承受过度的承载应力,而导致弯曲或断裂。In addition, another
而且,图中显示有多条焊线5,是分别电性连接芯片4的多个焊垫411与接脚架3的金属接脚34。其中,本实施例的多条焊线5是分别电性连接芯片4的焊垫411与接脚架3位于底架32上方的金属接脚34上,且又未位于凹沟33的正上方处。同样地,为避免于打线工艺时,过度的打线承载应力,而导致凸缘310、或凹沟33处弯曲、或断裂。Moreover, the figure shows a plurality of
再且,一封胶体6,其包覆芯片4、至少一焊线5、及导线架1的部分并填满凹槽23、及凹沟33。因此,本实用新型由侧凸部210、凸缘部310、凹槽23、及凹沟33的设置,不仅增加导线架1与封胶6的接合面积,更利用结构的卡固特性,以便能大幅提高导线架1与封胶6的接合强度,避免封胶6自任一方向的脱层情况,进而提高良率,大幅降低成本。Furthermore, the
请参阅图4,图4是本实用新型可强化封胶接合度的封装结构的第二实施例的剖视图。第二实施例与第一实施例主要差异在于,第一实施例的凹槽23、及凹沟33分别为半圆弧沟槽30且其整体分别位于芯片承载台21的下表面211、及接脚台31的下表面311。反观,第二实施例的凹槽23、及凹沟33皆为四分的三圆弧沟槽36,且其又分别位于芯片承载台21的下表面211与底座22的侧壁221、及接脚台31的下表面311与底架32侧壁321上。Please refer to FIG. 4 . FIG. 4 is a cross-sectional view of a second embodiment of the packaging structure of the present invention that can strengthen the bonding degree of sealing glue. The main difference between the second embodiment and the first embodiment is that the groove 23 and the groove 33 of the first embodiment are respectively semi-arc grooves 30 and the whole is located on the
请同时参阅图5、图6、图7、及图8,图5是本实用新型可强化封胶接合度的封装结构的第三实施例的剖视图,图6是本实用新型第四实施例封装结构的剖视图,图7是本实用新型第五实施例封装结构的剖视图,图8是本实用新型第六实施例的剖视图。图5所示的第三实施例与上述实施例主要差异在于,第三实施例的凹槽23、及凹沟33分别为一多边形沟槽35,且其为一梯形沟槽351。另外,图6所示的第四实施例的凹槽23、及凹沟33同样分别为一多边形沟槽35,但其为一三角形沟槽352。至于,图7所示的第五实施例,其凹槽23、及凹沟33同样为多边形沟槽35,又分别为矩形沟槽353,且其分别位于芯片承载台21的下表面211与底座22的侧壁221、及接脚台31的下表面311与底架32侧壁321上。另外,图8所示的第六实施例,其凹槽23、及凹沟33同样为多边形沟槽35,又分别为不规则多边形沟槽354,主要用以说明本发明可适用于任何形状的凹槽23、或凹沟33。Please refer to Fig. 5, Fig. 6, Fig. 7, and Fig. 8 at the same time. Fig. 5 is a cross-sectional view of the third embodiment of the packaging structure of the utility model that can strengthen the joint degree of sealing glue, and Fig. 6 is the package of the fourth embodiment of the utility model. The cross-sectional view of the structure, Fig. 7 is a cross-sectional view of the packaging structure of the fifth embodiment of the present invention, and Fig. 8 is a cross-sectional view of the sixth embodiment of the present invention. The main difference between the third embodiment shown in FIG. 5 and the above-mentioned embodiments is that the groove 23 and the groove 33 of the third embodiment are respectively a polygonal groove 35 and a trapezoidal groove 351 . In addition, the groove 23 and the groove 33 of the fourth embodiment shown in FIG. 6 are also a polygonal groove 35 , but they are a triangular groove 352 . As for the fifth embodiment shown in FIG. 7, the groove 23 and the groove 33 are also polygonal grooves 35 and rectangular grooves 353 respectively, and they are respectively located on the
Claims (12)
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102522382A (en) * | 2012-01-11 | 2012-06-27 | 日月光半导体制造股份有限公司 | Chip package |
CN104425421A (en) * | 2013-08-30 | 2015-03-18 | 联发科技股份有限公司 | Chip package and method of forming the same |
CN107195612A (en) * | 2017-06-20 | 2017-09-22 | 南京矽邦半导体有限公司 | One kind is based on pin QFN frameworks in lengthening half-etching arch and its encapsulation chip |
CN112595301A (en) * | 2020-11-04 | 2021-04-02 | 上海航天控制技术研究所 | Mercury ring of magnetic fluid angular velocity sensor and bonding method thereof |
-
2010
- 2010-05-07 CN CN 201020189142 patent/CN201766073U/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102522382A (en) * | 2012-01-11 | 2012-06-27 | 日月光半导体制造股份有限公司 | Chip package |
CN104425421A (en) * | 2013-08-30 | 2015-03-18 | 联发科技股份有限公司 | Chip package and method of forming the same |
CN107195612A (en) * | 2017-06-20 | 2017-09-22 | 南京矽邦半导体有限公司 | One kind is based on pin QFN frameworks in lengthening half-etching arch and its encapsulation chip |
CN112595301A (en) * | 2020-11-04 | 2021-04-02 | 上海航天控制技术研究所 | Mercury ring of magnetic fluid angular velocity sensor and bonding method thereof |
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