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CN100424864C - Lead frame for improving packaging reliability and packaging structure thereof - Google Patents

Lead frame for improving packaging reliability and packaging structure thereof Download PDF

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Publication number
CN100424864C
CN100424864C CNB2004100690728A CN200410069072A CN100424864C CN 100424864 C CN100424864 C CN 100424864C CN B2004100690728 A CNB2004100690728 A CN B2004100690728A CN 200410069072 A CN200410069072 A CN 200410069072A CN 100424864 C CN100424864 C CN 100424864C
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lead frame
package reliability
weld layer
chip
semiconductor chip
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CN1722423A (en
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林伟胜
江连成
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48996—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/48997—Reinforcing structures
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/85951—Forming additional members, e.g. for reinforcing
    • H—ELECTRICITY
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    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/30—Technical effects
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    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A lead frame for improving package reliability and a package structure thereof are provided, the lead frame comprising: a chip seat and a plurality of pins distributed around the chip seat; the invention mainly forms relative uneven structures such as metal bumps or concave parts on a welding layer to be connected with bonding wires on a routing distribution area of a lead frame, and when an encapsulation colloid coats a chip, the bonding wires and part of the lead frame in the subsequent encapsulation process, the uneven structure of the welding layer provides more contact area and bonding force with the encapsulation colloid, thereby avoiding the breakage of the bonding wires and improving the electrical property and the encapsulation reliability.

Description

提高封装可靠性的导线架及其封装结构 Lead Frame and Its Package Structure for Improving Packaging Reliability

技术领域 technical field

本发明是关于一种提高封装可靠性的导线架及其封装结构，特别是关于一种提高芯片与导线架间的金线焊接可靠性的导线架结构以及应用该导线架的封装结构。The invention relates to a lead frame and its package structure for improving packaging reliability, in particular to a lead frame structure for improving the reliability of gold wire welding between a chip and the lead frame and a package structure using the lead frame.

背景技术 Background technique

传统半导体芯片是以导线架(Lead Frame)作为芯片承载件以形成一半导体封装件。该导线架包括一芯片座及形成在该芯片座周围的多条管脚，待半导体芯片粘接至芯片座上并以焊线电性连接该芯片与管脚后，经由一封装树脂包覆该芯片、芯片座、焊线以及管脚的内段，从而形成该具导线架的半导体封装件。A traditional semiconductor chip uses a lead frame as a chip carrier to form a semiconductor package. The lead frame includes a chip seat and a plurality of pins formed around the chip seat. After the semiconductor chip is bonded to the chip seat and the chip and the pins are electrically connected by welding wires, the package resin is used to cover the lead frame. The chip, the chip seat, the bonding wire and the inner section of the pin form the semiconductor package with a lead frame.

以导线架作为芯片承载件的半导体封件的形态及种类繁多，如QFP半导体封装件(Quad Flat Package)、QFN(Quad-Flat Non-leaded)半导体封装件、SOP半导体封装件(Small Outline Package)或DIP半导体封装件(Dual in-line Package)等，为提高半导体封装件的散热效率与兼顾芯片尺寸封装(Chip Scale Package，CSP)的小尺寸要求，目前多以芯片座底部外露的QFN半导体封装件或露垫式(Exposed Pad)半导体封装件为封装主流。There are many forms and types of semiconductor packages with lead frame as chip carrier, such as QFP semiconductor package (Quad Flat Package), QFN (Quad-Flat Non-leaded) semiconductor package, SOP semiconductor package (Small Outline Package) Or DIP semiconductor package (Dual in-line Package), etc., in order to improve the heat dissipation efficiency of the semiconductor package and take into account the small size requirements of the chip size package (Chip Scale Package, CSP), at present, the QFN semiconductor package with the exposed bottom of the chip base is mostly used Package or Exposed Pad (Exposed Pad) semiconductor package is the mainstream of packaging.

此外，传统导线架形态的半导体封装件为进一步提高半导体封装件的电性品质，该半导体芯片上除可利用信号线(Signal Wire)电性连接各管脚外，也能通过向下打线(Down Bond)方式用接地线(Ground Wire)电性连接芯片接地垫及该导线架的芯片座。也就是该导线架提供焊线作电性连接的打线分布区是可包括该管脚部分及该芯片座周围。In addition, in order to further improve the electrical quality of the semiconductor package in the form of a traditional lead frame, the semiconductor chip can not only use the signal wire (Signal Wire) to electrically connect each pin, but also can use the downward bonding (Signal Wire) The Down Bond) method uses a ground wire (Ground Wire) to electrically connect the chip ground pad and the chip holder of the lead frame. That is, the wire bonding distribution area where the lead frame provides bonding wires for electrical connection may include the pin part and the periphery of the die pad.

在提供半导体芯片与导线架作电性连接时，因该导线架的材质主要是铜，而焊线的材质主要是金，由于铜与金的接合性不佳，因此通常会在导线架上要进行打线的区域(例如管脚)上先预镀银金属，在打线时，利用焊线的金与该导线架的打线区域的银形成共晶结构，提供焊线接合并电性连接至导线架上。由于该银金属与封装胶体的附着性不佳，在后续工序中容易因热应力发生脱层问题，进而导致焊线裂损或断裂问题。When providing electrical connection between the semiconductor chip and the lead frame, because the material of the lead frame is mainly copper, and the material of the bonding wire is mainly gold, because the bonding between copper and gold is not good, it is usually used on the lead frame. The area where the wire is to be bonded (such as the pin) is pre-plated with silver metal. When the wire is bonded, the gold of the wire and the silver in the wire area of the lead frame form a eutectic structure to provide wire bonding and electrical connection. onto the wire rack. Due to the poor adhesion between the silver metal and the encapsulation colloid, it is easy to cause delamination due to thermal stress in the subsequent process, which in turn leads to the problem of cracking or breaking of the bonding wire.

特别是对于QFN半导体封装件而言，其中未设置有外管脚，即未形成有如现有的QFP半导体封装件中用以与外界电性连接的外管脚，如此，能够缩小半导体封装件的尺寸。如图1A所示，该QFN半导体封装件1导线架10的芯片座11底面及管脚12底面均是外露出封装胶体15，使得接置在该芯片座11上并借由焊线14电性连接至管脚12的半导体芯片13产生的热量能够有效地传播至外界，并使该QFN半导体封装件1能够借该管脚12外露表面直接与外界装置如印刷电路板(printed circuit board)(图未标)电性连接。Especially for the QFN semiconductor package, no external pins are provided therein, that is, no external pins are formed as in the existing QFP semiconductor package for electrical connection with the outside world, so that the size of the semiconductor package can be reduced. size. As shown in Figure 1A, the bottom surface of the chip holder 11 and the bottom surface of the pin 12 of the lead frame 10 of the QFN semiconductor package 1 all expose the packaging compound 15, so that they are connected to the chip holder 11 and electrically connected by the bonding wire 14. The heat generated by the semiconductor chip 13 connected to the pin 12 can be effectively dissipated to the outside world, and the QFN semiconductor package 1 can be directly connected to an external device such as a printed circuit board (printed circuit board) by the exposed surface of the pin 12 (Fig. Not marked) electrical connection.

另请参阅图1B及图1C所示的用以电性导接半导体芯片与导线架的焊线局部放大示意图，由于该QFN导线架仅以其单一表面被封装胶体15所包覆，因此在封装工序中，极易因为受到热应力的影响，使得封装胶体15与管脚12的银金属间发生脱层问题，进而导致焊线14裂损或断裂，严重影响工序的可靠性。Please also refer to the partially enlarged schematic diagrams of the bonding wires for electrically connecting the semiconductor chip and the lead frame shown in FIG. 1B and FIG. During the process, due to the influence of thermal stress, delamination between the encapsulant 15 and the silver metal of the pin 12 is likely to occur, which in turn leads to cracks or breakage of the bonding wire 14, seriously affecting the reliability of the process.

鉴于上述缺点，美国专利第6,208,020、6,338,984、6,483,178号案，即揭示在导线架的管脚上，形成凹槽或孔洞，借由该凹槽或孔洞提高该导线架与封装胶体的接合力。In view of the above disadvantages, US Patent Nos. 6,208,020, 6,338,984, and 6,483,178 disclose that grooves or holes are formed on the pins of the lead frame, and the bonding force between the lead frame and the encapsulant is improved through the grooves or holes.

请参阅图2，它是美国专利第6,483,178号案所揭示的导线架封装结构。该导线架封装结构是QFN半导体封装件2，它包括底侧表面外露的芯片座21，接合在该芯片座上的芯片23，设置在该芯片座周围的多条管脚22，连设在该芯片23与该管脚22之间的焊线24，以及使该管脚22的外侧表面及底侧表面外露的方式将该管脚22、芯片23、焊线24与该芯片座21除底侧表面以外的部份加以包覆的封装胶体25。其中该管脚22上设有至少一贯穿该管脚22厚度方向的栓孔26a，使封装胶体25也能够充满在该栓孔26a当中。该栓孔26a是由两个圆柱形通孔261a及262a所组成，且其中位于上方处的通孔261a的轴向投影截面积是小于位在其下方处的通孔262a的轴向投影截面积，以使充满在该栓孔26a内的封装胶体25，即可借由其投影截面积上小下大的段差结构将该管脚3嵌扣住，使管脚22能够固接在封装胶体25中。Please refer to FIG. 2 , which is a lead frame package structure disclosed in US Patent No. 6,483,178. The lead frame packaging structure is a QFN semiconductor package 2, which includes a chip base 21 exposed on the bottom surface, a chip 23 bonded on the chip base, a plurality of pins 22 arranged around the chip base, and connected to the chip base. The bonding wire 24 between the chip 23 and the pin 22, and the outer surface and the bottom side surface of the pin 22 are exposed except the bottom side of the pin 22, the chip 23, the bonding wire 24 and the chip holder 21. The encapsulation compound 25 that covers the part other than the surface. The pin 22 is provided with at least one pin hole 26 a through the thickness direction of the pin 22 , so that the encapsulant 25 can also be filled in the pin hole 26 a. The bolt hole 26a is composed of two cylindrical through holes 261a and 262a, and the axially projected cross-sectional area of the through hole 261a at the top is smaller than the axially projected cross-sectional area of the through hole 262a at its lower position. In order to make the encapsulation compound 25 filled in the bolt hole 26a, the pin 3 can be embedded and buckled by means of its projected cross-sectional area, which is small in the upper part and larger in the lower part, so that the pin 22 can be fixed on the encapsulation compound 25 middle.

然而在追求电子装置轻薄短小的前提下，使用具有细间距与小尺寸的管脚结构形态的导线架已成为目前业界主流，因此在小面积的管脚上不仅没有充分空间形成凹槽或孔洞，且其工序困难，再者，该凹槽或孔洞的设置会使得小尺寸的管脚结构刚性降低，造成焊接时难度增加，况且现有这些凹槽及孔洞设置位置是在管脚的打线区域外，对于解决打线区域内的银层与封装胶体的脱层问题并无多大助益。However, under the premise of pursuing light, thin and small electronic devices, the use of leadframes with fine-pitch and small-sized pin structures has become the mainstream in the industry. Therefore, there is not enough space to form grooves or holes on small-area pins. Moreover, the process is difficult. Moreover, the arrangement of the grooves or holes will reduce the rigidity of the small-sized pin structure, which will increase the difficulty of soldering. Moreover, the existing grooves and holes are located in the wiring area of the pins. In addition, it does not help much to solve the problem of delamination between the silver layer and the packaging colloid in the wiring area.

另外，美国专利第5,960,262号案则揭示一种在焊线尾端接点(Stitch Bond，一般称为二焊点)上植设金质凸块(Stud-Bond)来补强焊接结构的焊线连接技术，该技术的整体制作流程请参阅图3A至图3F。In addition, U.S. Patent No. 5,960,262 discloses a bonding wire connection in which a gold bump (Stud-Bond) is planted on a bonding wire tail point (Stitch Bond, generally referred to as a second bonding point) to reinforce the bonding structure. technology, please refer to FIG. 3A to FIG. 3F for the overall production process of this technology.

如图3A及图3B所示，首先，预备一打线机(Wire Bonder)，该打线机至少包括一容纳金线(焊线)32的焊嘴34，以及提供金线32夹放的线夹36(Clamper)，其中，该焊嘴34前端的金线32是以常用的烧球技术形成球型接点(Free Air Ball，FAB)，以与半导体芯片上各I/O连接点300对应压接，从而将该球型接点(Ball Bond，一般称作第一焊点)焊接至I/O连接点300上。如图3C所示，接着，移动焊嘴34，借由焊嘴34的牵引将金线32拉到导线架的管脚(Lead)31预设位置上，予以焊接(Stitch Bond)并且截断成为第二焊点。如图3D至图3F所示，之后，在该管脚31的第二焊点上补植一与该金线32相同材料的金质凸块37(Stud)，借以增强第二焊点与管脚31预设位置间焊接结构的强度。As shown in Fig. 3A and Fig. 3B, at first, prepare a wire bonder (Wire Bonder), this wire bonder at least includes a welding nozzle 34 that accommodates gold wire (bonding wire) 32, and provides the wire that gold wire 32 clamps and puts Clamper 36 (Clamper), wherein, the gold wire 32 at the front end of the welding nozzle 34 is a ball joint (Free Air Ball, FAB) formed by a commonly used ball burning technology, so as to correspond to the pressure of each I/O connection point 300 on the semiconductor chip. so as to weld the ball bond (Ball Bond, generally referred to as the first solder joint) to the I/O connection point 300. As shown in Figure 3C, then, move the welding nozzle 34, pull the gold wire 32 to the preset position of the pin (Lead) 31 of the lead frame by the traction of the welding nozzle 34, be welded (Stitch Bond) and cut off to become the first Two solder joints. As shown in FIGS. 3D to 3F, afterward, a gold bump 37 (Stud) of the same material as the gold wire 32 is replanted on the second soldering point of the pin 31, so as to strengthen the connection between the second soldering point and the tube. The strength of the welded structure between the preset positions of the feet 31.

由于第二焊点上补植金质凸块仅可强化焊点与导线架的接合，使得该金线近焊点处的颈部成为金线结构强度的相对弱点，易在此处发生断裂问题；再者，形成该金质凸块必须严格地控制焊嘴平移的精度，这样会使工序时间延长、成本增加并会提高作业上的难度；此外，连接凸块的金线扯断时，断线处往往受限于平移量不易控制而导致残留在焊嘴上的线尾长度不一，因此也会影响到下次烧球(FAB)的球型，使得球型接点的大小无法均一。Since the supplementary gold bump on the second solder joint can only strengthen the joint between the solder joint and the lead frame, the neck of the gold wire near the solder joint becomes a relatively weak point in the structural strength of the gold wire, which is prone to fracture problems Furthermore, the accuracy of the translation of the welding tip must be strictly controlled to form the gold bump, which will prolong the process time, increase the cost and improve the difficulty of the operation; in addition, when the gold wire connecting the bump is broken, the broken The line is often limited by the difficulty of controlling the amount of translation, resulting in different lengths of the tail remaining on the solder tip, which will also affect the ball shape of the next burning ball (FAB), making the size of the ball joints not uniform.

发明内容 Contents of the invention

为克服上述现有技术的缺点，本发明的主要目的在于提供一种提高封装可靠性的导线架及其封装结构，避免导线架与封装胶体之间的应力造成焊线接合部位发生脱层或断裂，维持焊线连接部位良好的导电性。In order to overcome the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide a lead frame and its packaging structure that improves the reliability of the package, so as to avoid delamination or breakage of the bonding parts caused by the stress between the lead frame and the encapsulant , to maintain good electrical conductivity at the wire connection.

本发明的另一目的在于提供一种提高封装可靠性的导线架及其封装结构，可使用传统打线焊接工序，不需要精确控制工序的精细度，以缩短打线花费时间，同时可提高封装胶体与导线架间封装的可靠性。Another object of the present invention is to provide a lead frame and its packaging structure that improves the reliability of packaging, which can use the traditional wire bonding process without the need to accurately control the fineness of the process, so as to shorten the time spent on wire bonding and improve the packaging efficiency. The reliability of the package between the colloid and the lead frame.

本发明的再一目的在于提供一种提高封装可靠性的导线架及其封装结构，无须严格控制打线机(Wire Bonder)平移的精度，以稳定焊接球(Ball Bond)工序而使每一次焊接球形成时，该焊接球的球型维持均一，同时可提高封装胶体与导线架间封装的可靠性。Another object of the present invention is to provide a lead frame and its packaging structure with improved packaging reliability. It is not necessary to strictly control the accuracy of the translation of the wire bonder (Wire Bonder), so as to stabilize the soldering ball (Ball Bond) process and make each soldering When the ball is formed, the ball shape of the solder ball remains uniform, and meanwhile, the reliability of the package between the encapsulation colloid and the lead frame can be improved.

为达上揭及其它目的，本发明的提高封装可靠性的导线架包括：一芯片座以及分布在该芯片座周围的多条管脚，在该导线架在其打线分布区中布设有焊接层，且至少一该焊接层上未供焊线接置处形成有相对凹凸结构。其中该导线架的材质主要是铜金属，该导线架的打线分布区可在管脚上及/或该芯片座的周围，且焊接层的材质是银及镍/钯等金属层，该形成在焊接层上的相对凹凸结构是以植置在该焊接层上的金属凸块的形式，或以形成在该焊接层中的凹部的形式，借由该相对凹凸结构的不平整性，提高后续封装胶体与该焊接层的接合，进而避免发生脱层问题。In order to achieve the above disclosure and other purposes, the lead frame for improving packaging reliability of the present invention includes: a chip base and a plurality of pins distributed around the chip base, and a solder joint is arranged in the lead frame in its wiring distribution area. layers, and at least one of the soldering layers is formed with a relatively concave-convex structure at places where the soldering wires are not connected. Wherein the material of the lead frame is mainly copper metal, the wiring distribution area of the lead frame can be on the pins and/or around the chip holder, and the material of the soldering layer is metal layers such as silver and nickel/palladium, the forming The relative concave-convex structure on the soldering layer is in the form of a metal bump implanted on the soldering layer, or in the form of a concave portion formed in the soldering layer. The unevenness of the relative concave-convex structure improves the subsequent The joint of the encapsulant and the solder layer can avoid the problem of delamination.

此外，本发明的一种提高封装可靠性的导线架封装结构包括：一导线架，其具有一芯片座及分布在该芯片座周围的多条管脚，该导线架在其打线分布区中布设有焊接层，且至少一个该焊接层上未供焊线接置处形成有相对凹凸结构；至少一个半导体芯片，是接置在该芯片座上；多条焊线，是电性连接该半导体芯片与导线架的打线分布区；以及一封装胶体，用以包覆该半导体芯片、焊线与部分的导线架。In addition, a lead frame packaging structure of the present invention to improve packaging reliability includes: a lead frame, which has a chip seat and a plurality of pins distributed around the chip seat, and the lead frame is in its wiring distribution area A welding layer is arranged, and at least one of the soldering layers is not provided with a welding wire to form a relatively concave-convex structure; at least one semiconductor chip is placed on the chip holder; a plurality of welding wires are electrically connected to the semiconductor The wiring distribution area of the chip and the lead frame; and an encapsulation compound used to cover the semiconductor chip, the bonding wire and part of the lead frame.

因此，本发明的提高封装可靠性的导线架及其封装结构主要是在导线架的打线分布区上要与焊线连接的焊接层上形成有例如金属凸块或凹部等相对凹凸不平整结构，在后续进行封装工序中，使得封装胶体包覆在该芯片、焊线与部分导线架时，使得该借由该焊接层的不平整结构，能够提供其与封装胶体较多接触面积及接合力，避免焊接层与封装胶体产生脱层以及焊线断裂问题，借以提高电性品质及封装可靠性。另一方面，与现有技术相比，本发明是借由于导线架的打线分布区的焊接层上形成不平整结构提高导线架与封装胶体的接合性，毋需在小面积的管脚上形成凹槽或孔洞，故得避免管脚结构刚性降低以及工序与打线作业的难度升高，并可充分减少打线分布区内的焊接层与封装胶体的脱层问题；此外，与焊线压接部补球(Stud-bond)的现有技术相比，本发明不需要严格控制打线机的精度以及平移量，避免因为平移控制误差，造成焊嘴线尾残留长度不同而导致球型无法均一的缺点，且本发明不需要使用特殊参数来控制球型，从而提高工序流畅性，以及避免焊线近焊点处的颈部发生断裂问题。Therefore, the lead frame and its packaging structure for improving packaging reliability of the present invention are mainly formed on the welding layer to be connected with the welding wire on the wire bonding distribution area of the lead frame, such as metal bumps or recesses, and other relatively uneven structures. In the subsequent packaging process, when the encapsulation compound is coated on the chip, the bonding wire and some lead frames, the uneven structure of the solder layer can provide more contact area and bonding force with the encapsulation compound , to avoid the delamination of the solder layer and the packaging colloid and the problem of wire breakage, so as to improve the electrical quality and packaging reliability. On the other hand, compared with the prior art, the present invention improves the bondability between the lead frame and the encapsulant by forming an uneven structure on the soldering layer of the wiring distribution area of the lead frame, without the need for small-area pins Grooves or holes are formed, so it is necessary to avoid the reduction of the rigidity of the pin structure and the difficulty of the process and the wiring operation, and can fully reduce the delamination of the solder layer and the packaging colloid in the wiring distribution area; in addition, with the welding wire Compared with the existing technology of stud-bond at the crimping part, the present invention does not need to strictly control the accuracy and translation of the wire bonding machine, and avoids the ball shape caused by the difference in the residual length of the wire tail of the welding tip due to the translation control error. The lack of uniformity, and the present invention does not need to use special parameters to control the ball shape, thereby improving the smoothness of the process, and avoiding the problem of fracture of the neck near the welding point of the welding wire.

附图说明 Description of drawings

图1A是现有QFN半导体封装件的剖面示意图；1A is a schematic cross-sectional view of an existing QFN semiconductor package;

图1B是现有QFN半导体封装件中焊线发生脱层及断裂问题的局部侧视图；Fig. 1B is a partial side view of the problem of delamination and fracture of bonding wires in the existing QFN semiconductor package;

图1C是现有QFN半导体封装件中焊线发生脱层及断裂问题的局部俯视图；1C is a partial top view of the problem of delamination and fracture of bonding wires in the existing QFN semiconductor package;

图2是美国专利第6,483,178号案在导线架的管脚上形成有凹槽的封装结构示意图；FIG. 2 is a schematic diagram of a package structure in which grooves are formed on the pins of the lead frame in US Patent No. 6,483,178;

图3A至图3F是美国专利第5,960,262号案在焊线尾端接点上植设金质凸块来补强焊接结构的焊线连接工序示意图；3A to 3F are schematic diagrams of the welding wire connection process of US Patent No. 5,960,262, where gold bumps are planted on the end points of the welding wires to reinforce the welding structure;

图4A及图4B是本发明实施例1的提高封装可靠性的导线架示意图；FIG. 4A and FIG. 4B are schematic diagrams of lead frames for improving packaging reliability in Embodiment 1 of the present invention;

图4C是在导线架的打线分布区的焊接层上设置有金属凸块的示意图；FIG. 4C is a schematic diagram of metal bumps disposed on the solder layer of the wire bonding distribution area of the lead frame;

图5A及图5B是本发明实施例1的提高封装可靠性的导线架封装结构示意图；FIG. 5A and FIG. 5B are schematic diagrams of lead frame packaging structures for improving packaging reliability according to Embodiment 1 of the present invention;

图6A至图6C是形成本发明实施例2的提高封装可靠性的导线架的焊接层凹凸部工序示意图；以及6A to FIG. 6C are schematic diagrams of the process of forming the concavo-convex portion of the soldering layer of the leadframe for improving the reliability of the package according to Embodiment 2 of the present invention; and

图6D是在导线架的打线分布区的焊接层中形成有外露出该导线架底材的环状凹部结构示意图。FIG. 6D is a structural schematic diagram of a ring-shaped concave portion exposing the substrate of the lead frame formed in the soldering layer of the wire bonding distribution area of the lead frame.

具体实施方式 Detailed ways

以下兹以适用于四边形平面无管脚式(Quad-Flat Non-leaded，QFN)封装件的导线架详细本发明的具体实施例，本发明中的导线架并非局限于此，也可以是其它形态的导线架结构；同时，下述实施例的附图也仅简单绘示与实施内容有关的组件结构，实际所包括的组件数量、大小及布局往往更加复杂。The specific embodiment of the present invention will be described in detail below as a lead frame suitable for quad-flat non-leaded (QFN) packages. The lead frame in the present invention is not limited thereto, and can also be in other forms. At the same time, the drawings of the following embodiments only simply show the structure of the components related to the implementation content, and the actual number, size and layout of the components included are often more complicated.

实施例1Example 1

图4A及图4B是本发明实施例1的提高封装可靠性的导线架示意图。该导线架40主要包括：一芯片座41以及分布在该芯片座周围的多条管脚42，该导线架40在其打线分布区中布设有焊接层43，且至少一该焊接层43上未供焊线接置处形成有例如金属凸块441的相对凹凸结构，其中，该凹凸结构是可选择性或全面设置在该导线架40的焊接层43上，例如可针对该导线架40的焊接层43上可能受到较大热应力处(即该导线架40角隅处的管脚42及芯片座41焊接层43的位置)选择性设置该凹凸结构，借以在封装工序的热环境中提供该导线架40的焊接层43与封装胶体间较佳的接合性。FIG. 4A and FIG. 4B are schematic diagrams of lead frames for improving packaging reliability according to Embodiment 1 of the present invention. The lead frame 40 mainly includes: a chip holder 41 and a plurality of pins 42 distributed around the chip holder; A relative concave-convex structure such as a metal bump 441 is formed at the place where no wire is connected, wherein the concave-convex structure can be selectively or fully disposed on the soldering layer 43 of the lead frame 40 , for example, it can be aimed at the soldering layer 43 of the lead frame 40 The concave-convex structure is selectively provided on the soldering layer 43 that may be subjected to relatively large thermal stress (that is, the position of the pin 42 at the corner of the lead frame 40 and the soldering layer 43 of the chip holder 41), so as to provide protection in the thermal environment of the packaging process. The bonding between the solder layer 43 of the lead frame 40 and the encapsulant is better.

其中，该导线架40的打线分布区可包括该管脚42内侧部分及该芯片座41周围，可供后续将芯片接置在该芯片座41时，除可利用信号焊线(Signal Wire)电性连接各管脚42外，也能利用接地焊线(GroundWire)电性连接芯片接地垫及该导线架40的芯片座41周围未被芯片所占据预先定义出的接地区(Grounding Region)。该导线架的材质主要是铜金属，焊接层的材质是银、镍/钯等金属层，在提供半导体芯片与导线架间利用焊线(金线)作电性连接时，借由焊线(金)与该导线架的打线分布区的焊接层(银)形成共晶结构，使焊线接合并电性连接至导线架上。Wherein, the wiring distribution area of the lead frame 40 may include the inner part of the pin 42 and the periphery of the chip holder 41, which can be used for subsequent placement of the chip on the chip holder 41, in addition to using signal wires (Signal Wire) In addition to electrically connecting the pins 42, grounding wires (GroundWire) can also be used to electrically connect the chip grounding pad and the pre-defined grounding region (Grounding Region) around the chip seat 41 of the lead frame 40 that is not occupied by the chip. The material of the lead frame is mainly copper metal, and the material of the welding layer is a metal layer such as silver, nickel/palladium, etc. When providing an electrical connection between the semiconductor chip and the lead frame using a bonding wire (gold wire), the bonding wire ( Au) forms a eutectic structure with the soldering layer (silver) in the wire bonding distribution area of the lead frame, so that the bonding wires are bonded and electrically connected to the lead frame.

另请参阅图4C，设置在该导线架40的打线分布区的焊接层43上的相对凹凸结构可以是植置在该焊接层43上的金属凸块441形式，该金属凸块441是可利用打线机(Wire Bonder)45植置与焊线相同材料的金质凸块(Stud)，借由该金属凸块441形成的不平整结构来增加对封装胶体的附着力，避免该焊接层(银)43与封装胶体的附着性不佳，造成后续脱层及焊线断裂问题。Also refer to FIG. 4C , the relative concave-convex structure provided on the solder layer 43 of the wire bonding distribution area of the lead frame 40 can be in the form of a metal bump 441 implanted on the solder layer 43, and the metal bump 441 can be Use a wire bonder (Wire Bonder) 45 to implant a gold bump (Stud) of the same material as the welding wire, and use the uneven structure formed by the metal bump 441 to increase the adhesion to the encapsulant, avoiding the solder layer (Silver) 43 has poor adhesion to the encapsulation colloid, resulting in subsequent delamination and wire breakage.

在本实施例1中可在打线机焊嘴处设置有一热熔装置(ElectricFlame-off，EFO)，以借由高压电(约4000伏特)等的放电方式，在焊线前端烧结成一球型接点(Free Air Ball，FAB)。接着，移动焊嘴，将焊嘴前端的球型接点向下压接到焊接层上，使得连接焊线的球型接点熔融接合至焊接层表面上。以本实施例1为例，该球型接点与焊接层接触后，打线机的焊嘴会施予该球型接点约100克向下的压力，并且产生频率约60-120kHz的超声波，使球型接点与焊接层摩擦而产生融接。In this embodiment 1, a hot-melt device (Electric Flame-off, EFO) can be installed at the welding tip of the wire bonding machine to sinter a ball at the front end of the welding wire by means of discharge such as high voltage (about 4000 volts). Type contact (Free Air Ball, FAB). Next, move the welding nozzle, and press the ball joint at the front end of the welding nozzle downward to the soldering layer, so that the ball joint connected with the welding wire is fused and bonded to the surface of the soldering layer. Taking this embodiment 1 as an example, after the ball joint is in contact with the solder layer, the tip of the wire bonding machine will apply a downward pressure of about 100 grams to the ball joint, and generate ultrasonic waves with a frequency of about 60-120 kHz, so that The ball joint rubs against the solder layer to produce fusion.

图5A及图5B是本发明实施例1的提高封装可靠性的导线架封装结构示意图，该封装结构包括如图4A及图4B所显示的导线架40，该导线架40具有一芯片座41及分布在该芯片座41周围的多条管脚42，且在其打线分布区中布设有焊接层43，其中至少一该焊接层43上未供焊线接置处形成有相对凹凸结构，该相对凹凸结构可以是与该焊线相同材料的金属凸块411；至少一半导体芯片51，是接置在该芯片座41上；多条焊线52，是电性连接该半导体芯片51与导线架40的打线分布区的焊接层43；以及一封装胶体53，用以包覆该半导体芯片51、焊线52与部分的导线架40。5A and FIG. 5B are schematic diagrams of a lead frame package structure for improving package reliability according to Embodiment 1 of the present invention. The package structure includes a lead frame 40 as shown in FIG. 4A and FIG. 4B, and the lead frame 40 has a chip holder 41 and A plurality of pins 42 distributed around the chip base 41, and a welding layer 43 is arranged in the wiring distribution area thereof, wherein at least one of the welding layers 43 is formed with a relatively concave-convex structure at a place where the welding wire is not connected, the The relative concave-convex structure can be a metal bump 411 of the same material as the bonding wire; at least one semiconductor chip 51 is connected to the chip holder 41; a plurality of bonding wires 52 are electrically connected to the semiconductor chip 51 and the lead frame The soldering layer 43 of the wire bonding distribution area of 40;

其中，该金属凸块441是可利用打线机预先植置在该导线架40的打线分布区的焊接层43上，再在该导线架40的芯片座41上接置半导体芯片51，之后再以打线机进行焊线作业，使该半导体芯片51与导线架40电性连接。此外，也可在将半导体芯片51置于该导线架的芯片座41后，先利用打线机在该导线架40的打线分布区的焊接层43上形成该金属凸块441，同时利用打线机进行焊线作业，以通过焊线52电性连接该半导体芯片51与该导线架40上打线分布区未植置有金属凸块441的空间。Wherein, the metal bump 441 can be pre-planted on the solder layer 43 of the wire bonding distribution area of the lead frame 40 by using a wire bonding machine, and then the semiconductor chip 51 is connected on the chip holder 41 of the lead frame 40, and then Then use a wire bonding machine to perform wire bonding to electrically connect the semiconductor chip 51 to the lead frame 40 . In addition, after the semiconductor chip 51 is placed on the chip holder 41 of the lead frame, the metal bump 441 can be formed on the solder layer 43 of the wire bonding distribution area of the lead frame 40 by using a wire bonder, and at the same time, the metal bump 441 can be formed by a bonder. The wire machine performs the wire bonding operation to electrically connect the semiconductor chip 51 and the space where the metal bump 441 is not implanted in the wire bonding distribution area on the lead frame 40 through the wire bonding 52 .

实施例2Example 2

图6A至图6C是为形成本发明实施例2的提高封装可靠性的导线架的焊接层凹凸部的工序示意图。它是可利用打线机在焊接层上进行空打方式，以在该焊接层中形成凹部，进而可选择性露出该导线架的底材，也就是在该打线机的焊嘴中未容置有焊线，而直接以空打方式挤压该焊接层，借以在该焊接层中形成有凹凸结构。FIG. 6A to FIG. 6C are schematic diagrams of the process of forming the concave-convex part of the soldering layer of the leadframe for improving the packaging reliability according to the second embodiment of the present invention. It can use the wire bonding machine to perform empty punching on the soldering layer to form a recess in the soldering layer, and then selectively expose the substrate of the lead frame, that is, the soldering tip of the wire bonding machine does not accommodate Welding wires are placed, and the welding layer is directly extruded by empty punching, thereby forming a concave-convex structure in the welding layer.

首先，将焊嘴451中未容置有焊线的打线机45置于导线架40的焊接层43上(如图6A所示)。接着，移动该焊嘴451，并使其向下压迫该焊接层43至该导线架底材部分(如图6B所示)。之后，移开该焊嘴451(如图6C图所示)。借此，如图6D所示，即可在该焊接层43中形成有外露出该导线架底材的环状凹部结构442，借由该凹凸不平整结构以增加对封装胶体的附着力。Firstly, the wire bonder 45 with no welding wire contained in the welding tip 451 is placed on the welding layer 43 of the lead frame 40 (as shown in FIG. 6A ). Next, move the solder tip 451 and make it press the soldering layer 43 downward to the lead frame substrate portion (as shown in FIG. 6B ). Afterwards, the welding tip 451 is removed (as shown in FIG. 6C ). Thereby, as shown in FIG. 6D , an annular recess structure 442 exposing the lead frame substrate can be formed in the soldering layer 43 , and the adhesion to the encapsulant can be increased by the uneven structure.

后续，进行半导体封装工序时，是可提供预先在焊接层形成有凹部结构的导线架，再在该导线架的芯片座上接置半导体芯片，接着再以打线机进行焊线作业，使该半导体芯片与导线架电性连接，之后利用封装胶体包覆该半导体晶、焊线与部分的导线架。此外，也可在将半导体芯片置于导线架的芯片座后，先利用未含金线的打线机在该导线架的打线分布区的焊接层上进行空打，借以在至少一该焊接层中形成凹部结构，再利用含金线的打线机进行焊线作业，以通过焊线电性连接该半导体芯片与该导线架上打线分布区未设置有凹部结构的空间，再进行封装胶体工序。Subsequently, when carrying out the semiconductor packaging process, it is possible to provide a lead frame with a concave structure formed in the soldering layer in advance, and then connect the semiconductor chip on the chip holder of the lead frame, and then perform the wire bonding operation with a wire bonding machine, so that the The semiconductor chip is electrically connected to the lead frame, and then the semiconductor chip, bonding wires and part of the lead frame are covered with packaging colloid. In addition, after the semiconductor chip is placed on the chip holder of the lead frame, a wire bonding machine that does not contain gold wires can be used to perform dummy punching on the soldering layer of the wire bonding distribution area of the lead frame, so that at least one of the soldering wires can be soldered. Form a concave structure in the layer, and then use a wire bonding machine containing gold wires to perform wire bonding operations to electrically connect the semiconductor chip and the space where the wire bonding distribution area on the lead frame is not provided with a concave structure through bonding wires, and then package Colloid process.

因此，本发明的提高封装可靠性的导线架及其封装结构主要是在导线架的打线分布区上要与焊线连接的焊接层上形成有例如金属凸块或凹部等相对凹凸不平整的结构，在后续进行封装工序中，使得封装胶体包覆在该芯片、焊线与部分导线架时，能够使该借由该焊接层的不平整结构，提供其与封装胶体较多接触面积及接合力，避免焊接层与封装胶体产生脱层以及焊线断裂问题，借以提高电性品质及封装可靠性。同时本发明也可避免现有技术在导线架的管脚上形成凹槽或孔洞时，造成管脚结构刚性降低以及工序与打线作业的难度提高的问题，以及避免现有技术在焊线压接部补球导致的工序复杂性及焊线近焊点处的颈部发生断裂的问题。Therefore, the lead frame and its packaging structure for improving packaging reliability of the present invention are mainly formed on the welding layer to be connected with the welding wire on the wiring distribution area of the lead frame, such as metal bumps or concave parts. structure, in the subsequent encapsulation process, when the encapsulation compound is coated on the chip, bonding wires and part of the lead frame, the uneven structure of the solder layer can provide more contact area and bonding with the encapsulation compound Force, to avoid the delamination of the solder layer and the packaging colloid and the problem of wire breakage, so as to improve the electrical quality and packaging reliability. Simultaneously, the present invention can also avoid the problems that the rigidity of the pin structure is reduced and the difficulty of the process and wiring operation is increased when grooves or holes are formed on the pins of the lead frame in the prior art, and the problems of the prior art in the welding wire pressure are avoided. The complexity of the process caused by filling the ball at the joint and the problem of fracture of the neck of the welding wire near the welding point.

Claims (26)

1. a lead frame that improves package reliability is characterized in that, the lead frame of this raising package reliability comprises:
One chip carrier; And
Many the pins that are distributed in around this chip carrier;
This lead frame is laid with weld layer in its routing distributed area, and meets the place of putting and be formed with relative concaveconvex structure for bonding wire at least one this weld layer, and wherein this relative concaveconvex structure is the metal coupling that utilizes wire bonder to plant to put on this weld layer surface.
2. the lead frame of raising package reliability as claimed in claim 1 is characterized in that, the routing distributed area of this lead frame is this pin inside part.
3. the lead frame of raising package reliability as claimed in claim 1 is characterized in that, the routing distributed area of this lead frame is around this chip carrier.
4. the lead frame of raising package reliability as claimed in claim 1 is characterized in that, the material of this lead frame mainly is the copper metal, and the material of this weld layer is a kind of in silver and the nickel/palladium metal.
5. a lead frame encapsulation structure that improves package reliability is characterized in that, this lead frame encapsulation structure comprises:
One lead frame, have a chip carrier and many and be distributed in pin around this chip carrier, this lead frame is laid with weld layer in its routing distributed area, and meet the place of putting and be formed with relative concaveconvex structure for bonding wire at least one this weld layer, wherein this relative concaveconvex structure is the metal coupling that utilizes wire bonder to plant to put on this weld layer surface;
At least one connects the semiconductor chip of putting on this chip carrier;
Many bonding wires are the routing distributed areas that electrically connect this semiconductor chip and lead frame; And
One packing colloid is in order to coat this semiconductor chip, bonding wire and part lead frame.
6. the lead frame encapsulation structure of raising package reliability as claimed in claim 5 is characterized in that, the routing distributed area of this lead frame is this pin inside part.
7. the lead frame encapsulation structure of raising package reliability as claimed in claim 5 is characterized in that, the routing distributed area of this lead frame is around this chip carrier.
8. the lead frame encapsulation structure of raising package reliability as claimed in claim 5 is characterized in that, the material of this lead frame mainly is the copper metal, and the material of this weld layer is a kind of in silver and the nickel/palladium metal.
9. the lead frame encapsulation structure of raising package reliability as claimed in claim 5, it is characterized in that, this metal coupling is to utilize wire bonder to plant in advance to put on the weld layer in the routing distributed area of this lead frame, on the chip carrier of this lead frame, connect again and put semiconductor chip, carry out the bonding wire operation with wire bonder more afterwards, this semiconductor chip and lead frame are electrically connected.
10. the lead frame encapsulation structure of raising package reliability as claimed in claim 5, it is characterized in that, this encapsulating structure is after semiconductor chip is placed the chip carrier of this lead frame, utilize wire bonder to form this metal coupling earlier at the weld layer in the routing distributed area of this lead frame, utilize wire bonder to carry out the bonding wire operation simultaneously, electrically connect on this semiconductor chip and this lead frame routing distributed area by bonding wire and do not plant the space that is equipped with metal coupling.
11. the lead frame encapsulation structure of raising package reliability as claimed in claim 5 is characterized in that, this bonding wire is a signal bond wires, is in order to electrically connect the pin of semiconductor chip and lead frame.
12. the lead frame encapsulation structure of raising package reliability as claimed in claim 5 is characterized in that, this bonding wire is the ground connection bonding wire, is in order to not occupied the pre-defined access area that goes out by chip around the chip carrier that electrically connects semiconductor chip and lead frame.
13. a lead frame that improves package reliability is characterized in that, the lead frame of this raising package reliability comprises:
One chip carrier; And
Many the pins that are distributed in around this chip carrier;
This lead frame is laid with weld layer in its routing distributed area, and meet the place of putting and be formed with relative concaveconvex structure for bonding wire at least one this weld layer, wherein this relative concaveconvex structure is to utilize wire bonder to be arranged on recess structure in this weld layer in the enterprising line space mode of beating of weld layer.
14. the lead frame of raising package reliability as claimed in claim 13 is characterized in that, this recess structure is optionally to expose the ground of this lead frame.
15. the lead frame of raising package reliability as claimed in claim 13 is characterized in that, the routing distributed area of this lead frame is this pin inside part.
16. the lead frame of raising package reliability as claimed in claim 13 is characterized in that, the routing distributed area of this lead frame is around this chip carrier.
17. the lead frame of raising package reliability as claimed in claim 13 is characterized in that, the material of this lead frame mainly is the copper metal, and the material of this weld layer is a kind of in silver and the nickel/palladium metal.
18. a lead frame encapsulation structure that improves package reliability is characterized in that, this lead frame encapsulation structure comprises:
One lead frame, have a chip carrier and many and be distributed in pin around this chip carrier, this lead frame is laid with weld layer in its routing distributed area, and meet the place of putting and be formed with relative concaveconvex structure for bonding wire at least one this weld layer, wherein this relative concaveconvex structure is to utilize wire bonder to be arranged on recess structure in this weld layer in the enterprising line space mode of beating of weld layer;
At least one connects the semiconductor chip of putting on this chip carrier;
Many bonding wires are the routing distributed areas that electrically connect this semiconductor chip and lead frame; And
One packing colloid is in order to coat this semiconductor chip, bonding wire and part lead frame.
19. the lead frame encapsulation structure of raising package reliability as claimed in claim 18 is characterized in that, this recess structure is optionally to expose the ground of this lead frame.
20. the lead frame encapsulation structure of raising package reliability as claimed in claim 18, it is characterized in that, this encapsulating structure provides the lead frame that is formed with recess structure in advance at weld layer, on the chip carrier of this lead frame, connect again and put semiconductor chip, then carry out the bonding wire operation with wire bonder again, this semiconductor chip and lead frame are electrically connected.
21. the lead frame encapsulation structure of raising package reliability as claimed in claim 18, it is characterized in that, this encapsulating structure is after semiconductor chip is placed the chip carrier of lead frame, utilize the wire bonder that does not contain gold thread to beat earlier in the enterprising line space of weld layer in this lead frame routing distributed area, so as in this weld layer, forming recess structure, utilize the wire bonder contain gold thread to carry out the bonding wire operation again, to electrically connect the space that routing distributed area on this semiconductor chip and this lead frame is not provided with recess structure by bonding wire.
22. the lead frame encapsulation structure of raising package reliability as claimed in claim 18 is characterized in that, the routing distributed area of this lead frame is this pin inside part.
23. the lead frame encapsulation structure of raising package reliability as claimed in claim 18 is characterized in that, the routing distributed area of this lead frame is around this chip carrier.
24. the lead frame encapsulation structure of raising package reliability as claimed in claim 18 is characterized in that, the material of this lead frame mainly is the copper metal, and the material of this weld layer is a kind of in silver and the nickel/palladium metal.
25. the lead frame encapsulation structure of raising package reliability as claimed in claim 18 is characterized in that, this bonding wire is a signal bond wires, is in order to electrically connect the pin of semiconductor chip and lead frame.
26. the lead frame encapsulation structure of raising package reliability as claimed in claim 18 is characterized in that, this bonding wire is the ground connection bonding wire, is in order to not occupied the pre-defined access area that goes out by chip around the chip carrier that electrically connects semiconductor chip and lead frame.
CNB2004100690728A 2004-07-16 2004-07-16 Lead frame for improving packaging reliability and packaging structure thereof Expired - Fee Related CN100424864C (en)

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US10727085B2 (en) * 2015-12-30 2020-07-28 Texas Instruments Incorporated Printed adhesion deposition to mitigate integrated circuit package delamination

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