CN201607523U - Battery data intelligent analyzer - Google Patents
Battery data intelligent analyzer Download PDFInfo
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- CN201607523U CN201607523U CN2010201026364U CN201020102636U CN201607523U CN 201607523 U CN201607523 U CN 201607523U CN 2010201026364 U CN2010201026364 U CN 2010201026364U CN 201020102636 U CN201020102636 U CN 201020102636U CN 201607523 U CN201607523 U CN 201607523U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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- Y02E60/10—Energy storage using batteries
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Abstract
The utility model discloses a battery data intelligent analyzer, which is an instrument for measuring battery parameters capable of measuring the normal parameters of batteries, such as voltage, current and the like. The battery data intelligent analyzer has a function for intelligently premeasuring the volume of the batteries. The battery data intelligent analyzer comprises an outer shell base seat and an upper cover shell covered at the top part of the outer shell base seat. A circuit board is arranged in the outer shell base seat, and a power source module for supplying power to each circuit of the circuit board is also arranged in the outer shell base seat. The utility model provides a scientific means for measuring the volume of the batteries, and meanwhile, can make huge contributions for energy saving and emission reduction, and environmental protection.
Description
Technical field
The utility model relates to single-chip microcomputer automatic measure control instrument, a kind of specifically accumulator data intelligence analyser.
Background technology
Telecommunications, move and the communications equipment room of UNICOM's three big communication enterprises, the center can fall in the electric power of industry such as the iron and steel and the energy, use accumulator as standby power supply in large quantities, ensure continual communication and despatching work, in order to ensure these safety and production, must guarantee that accumulator is in good working order.For this reason, national regulation will carry out volume test to online accumulator every year.
The battery pack of the 2000AH48V that generally uses such as the telecommunication path machine room, the general standard station is minimum will to dispose 2 groups, will carry out 10 hours discharge tests of 200 amperes in accordance with regulations.This constant current discharge mode wastes time and energy, and the electric power energy consumption is big, and very big to the working environment and the shabby property of battery basic property of equipment.But in order to ensure the proper communication of network, telecommunications enterprise must carry out the discharge test of accumulator again according to the rules.
The utility model content
The purpose of this utility model provides a kind of accumulator data intelligence analyser, tests consuming time long to the influential problem of power equipment operate as normal to solve battery discharging.
In order to achieve the above object, the technical scheme that the utility model adopted is:
Accumulator data intelligence analyser, include outer casing base, and cover shell of top cover in the shell base top, described outer casing base inside is provided with circuit board, outer casing base inside also is provided with the power module of promising each circuit supply of circuit board, it is characterized in that: described circuit board is integrated with control circuit, accumulator signal acquisition circuit;
Described control circuit comprises cpu chip, be connected to the totalizer chip on the P10 of described cpu chip～P14 pin, be connected to house dog memory chip and clock and date chip on P16～P17 pin, be connected to sheet on P20～P27 pin and select latch, the ALE pin of described cpu chip also selects the LE pin of latch to be connected by Sheffer stroke gate with described, be connected with the RAM module interface on the read-write pin of cpu chip, the P00 of cpu chip～P07 pin, P20～P27 pin is connected to described RAM module interface by lead, the X1 of cpu chip, be connected to crystal oscillator between the X2 pin, the crystal oscillator two ends are connected with ground connection behind the electric capacity respectively; Described is selected the Q0 of latch, Q1 pin to be connected one by one with the RST pin of date chip with CS pin, the clock of house dog storer by lead respectively, Q3～Q5 pin is connected with A, B, the C pin of a code translator one by one by lead respectively, the Q7 pin is connected to described RAM module interface, and described is selected the Q1～Q4 of latch also to be connected one by one with the S1～S4 pin of described totalizer chip by lead; The A1 of described totalizer chip～A4 pin, B1 pin are connected with the P10～P14 pin of cpu chip one by one by lead respectively, B2～B4 pin, CI pin ground connection; The SO of described house dog storer, SI pin are connected with the P16 pin of cpu chip, and the SLK pin is connected with the P17 pin of cpu chip; Described clock is connected with P16, the P17 pin of cpu chip respectively with I/O pin, the CLK pin of date chip;
Described accumulator signal acquisition circuit includes the analog to digital converter chip, two photoelectric relays, two electronic analog swtichs and input interface, a photoelectric relay is reserved with two pins, be connected one by one with the IN-pin with the IN+ of described analog to digital converter chip by lead respectively, the voltage of accumulator, current signal is by described input interface input, described input interface has a plurality of pin outputs, be connected one by one with a plurality of pins of two photoelectric relays by lead respectively, also have a plurality of pins on the described photoelectric relay as output pin, be connected one by one with the I/O1～I/O15 pin of an electronic analog swtich separately respectively, the A of an electronic analog swtich, B, C, the D pin is connected with the P10～P13 pin of described cpu chip one by one by lead, the A of another electronic analog swtich, B, C, the D pin is connected with the S1～S4 pin of described totalizer chip one by one by lead, the INH pin of described two electronic analog swtichs is connected with the Y0 pin of described code translator by lead respectively, the SD0 pin of described analog to digital converter chip, the SCLK pin is the P16 by lead and described cpu chip respectively, the P17 pin connects one by one, and the CS pin of analog to digital converter chip selects the Q2 pin of latch to be connected by lead with described.
Described accumulator data intelligence analyser, it is characterized in that: described cpu chip model is SM5964, described is selected the latch model is HC373, described house dog storer model is X5045, described time and date chip model is DS1302, described totalizer chip model is MC14008, and described code translator model is 74HC138.
Described accumulator data intelligence analyser is characterized in that: described electronic analog swtich model is CD4067, and described analog to digital converter chip model is CS5513.
In the utility model, CPU element circuit control multi-channel switch circuit, analog parameters such as the voltage of accumulator, electric current are switched to the A/D circuit, by high-precision A/D circuit the battery analog parameter is converted to digital signal, the A/D circuit is given CPU element with battery data under the control of CPU element.The humiture collection circuit is converted to the humiture digital signal with battery temperature, environment temperature and humidity, and time and memory circuit are gathered and stored Time of Day and cell arrangement information, and these signals are also given CPU element.CPU analyzes and handles these data, and result is stored in the historical data base, also can directly report the host computer in the monitoring, and the user can carry out exchanges data by the CPU of three kinds of communication modes of RS232/485/422 and analyser.
The utility model effect is:
The utility model can reduce the time of accumulator capacity test significantly, improve the economic benefit of manufacturing enterprises such as communication, iron and steel and the energy, for battery capacity measuring provides a kind of advanced person's scientific method, also will make huge contribution for energy-saving and emission-reduction and environmental protection cause.
Description of drawings
Fig. 1 is the diffusing view of the utility model one-piece construction.
Fig. 2 is the utility model schematic block circuit diagram.
Fig. 3 is the utility model control circuit figure.
Fig. 4 is the utility model accumulator signal acquisition circuit figure.
Fig. 5 is a 12V battery discharging voltage curve.
Fig. 6 is the accumulator capacity curve map.
Fig. 7 is the utility model assembling synoptic diagram.
Fig. 8 is the utility model mainboard electronic component distribution plan.
Embodiment
As Fig. 1, shown in Figure 7, accumulator data intelligence analyser, include outer casing base 1, and cover shell of top cover 2 in shell base top 1, outer casing base 1 inside is provided with circuit board 3, outer casing base 1 inside also is provided with the power module of promising circuit board 3 each circuit supply, and circuit board 3 is integrated with control circuit, accumulator signal acquisition circuit;
As Fig. 2, Fig. 3, shown in Figure 8, control circuit comprises that model is the cpu chip U1 of SM5964, being connected to model on the P10 of cpu chip U1～P14 pin is the totalizer chip U10 of MC14008, being connected to model on P16～P17 pin is the house dog memory chip U4 of X5045 and clock and the date chip U5 that model is DS1302, the sheet that is connected to model on P20～P27 pin and is HC373 selects latch U2, the ALE pin of cpu chip U1 also selects the LE pin of latch U2 to be connected by Sheffer stroke gate U3A with sheet, be connected with RAM module interface JP3 on the read-write pin of cpu chip U1, the P00 of cpu chip U1～P07 pin, P20～P27 pin is connected to RAM module interface JP3 by lead, the X1 of cpu chip U1, be connected to crystal oscillator Y1 between the X2 pin, crystal oscillator Y1 two ends are connected with capacitor C 5 respectively, ground connection behind the C6; Sheet selects the Q0 of latch U2, Q1 pin to be connected one by one with the RST pin of date chip U5 with CS pin, the clock of house dog storer U4 by lead respectively, Q3～Q5 pin is connected one by one by A, B, the C pin of a lead and the model code translator U6 that is 74HC138 respectively, the Q7 pin is connected to RAM module interface JP3, and sheet selects Q1～Q4 of latch U2 also to be connected one by one with S1～S4 pin of totalizer chip U10 by lead; The A1 of totalizer chip U10～A4 pin, B1 pin are connected with P10～P14 pin of cpu chip U1 one by one by lead respectively, B2～B4 pin, CI pin ground connection; The SO of house dog storer U4, SI pin are connected with the P16 pin of cpu chip U1, and the SLK pin is connected with the P17 pin of cpu chip U1; Clock is connected with P16, the P17 pin of cpu chip U1 respectively with I/O pin, the CLK pin of date chip U5;
As Fig. 4, shown in Figure 8, the accumulator signal acquisition circuit includes the analog to digital converter chip U13 that model is CS5513, two photoelectric relay JP1, JP2, two electronic analog swtich U7 that model is CD4067, U8 and input interface P3, a photoelectric relay JP2 is reserved with two pin X, Y, be connected one by one with the IN-pin with the IN+ of analog to digital converter chip U13 by lead respectively, the voltage of accumulator, current signal is by input interface P3 input, input interface P3 has a plurality of pin outputs, respectively by lead and two photoelectric relay JP1, a plurality of pins of JP2 connect one by one, photoelectric relay JP1, also have a plurality of pins on the JP2 as output pin, be connected one by one with the I/O1～I/O15 pin of an electronic analog swtich separately respectively, the A of an electronic analog swtich U8, B, C, the D pin is connected with P10～P13 pin of cpu chip U1 one by one by lead, the A of another electronic analog swtich U7, B, C, the D pin is connected with S1～S4 pin of totalizer chip U10 one by one by lead, two electronic analog swtich U7, the INH pin of U8 is connected with the Y0 pin of code translator U6 by lead respectively, the SD0 pin of analog to digital converter chip U13, the SCLK pin is the P16 by lead and cpu chip U1 respectively, the P17 pin connects one by one, and the CS pin of analog to digital converter chip U13 selects the Q2 pin of latch U2 to be connected by lead and sheet.
CPU finishes the collection and the processing of accumulator basic parameters such as voltage, electric current and temperature by the foregoing circuit institutional framework, provides basic battery data to the user, finishes the function of conventional batteries measuring instrument.
In CTBT-320810 analyser module, CPU not only will finish the collection of battery basic parameter, what is more important utilizes some special formula that these parameters are carried out secondary analysis, form a series of battery capacities and calculate necessary parameter and coefficient, these parameters, coefficient and battery master data are included the accumulator capacity predictor formula together in and are calculated, CTBT-320810 analyser module will provide the capability value of accumulator when each calculation of parameter finishes, finish the prediction work of accumulator capacity.
Be that example is predicted the calculation of capacity explanation with the 12V accumulator below:
As Fig. 5, Fig. 5 is a 12V battery discharge voltage curve, and axis of ordinates unit is V, and the scale of abscissa axis is 10 minutes, and arithemetic unit is 10 seconds.
As Fig. 6, the capacity region that top battery discharging curve is divided into three phases is analyzed:
Phase one: begin non-linear capacity region, i.e. the t0 period, capacity is defined as C
0
Put capacity: C0=I0 * t0
Residual capacity: battery nominal capacity-put capacity=C-C
0
I0 is the mean value (note: following day part electric current carries out same definition) of electric current in the unit period.
Subordinate phase: the calculating in linear capacity district:
The linear merit of definition: W1, W2 is the unwrapping wire merit, and W3 remains linear merit, merit is defined as the electric flux of battery here, i.e. W=C * V, unit be a joule.
C0 is the capacity of beginning nonlinear phase, and C is the battery nominal capacity, and Cs is a non-linear capacity of later stage, and C1 linear capacity, C2 linearity have been put capacity, the linear residual capacity of C3, and each voltage definition is figure as above.
Calculate: W1=(C-C0-Cs) * (V2+V1)/2}
W2＝{(V2+Vt)/2}×{(I2+It)/2}(t-t0)
C2＝{(I2+It)/2}(t-t0)
W3＝W1-W2
C3＝f×W3/{(V2+Vt)/2}
Wherein f is the linear prediction ratio of battery discharge capacity, i.e. f=(t1-t0)/(T1-t0)
T1 is a pairing any time of theoretical linear zone voltage, and t1 is the actual moment identical with theoretical voltage, and span t0≤t1≤T1≤1 hour generally is taken at 0.5 hour of entering linear region of discharge and locates.
Phase III: the reckoning of non-linear capacity of later stage
Battery discharging is during to lower voltage limit, enter non-linear capacity region of later stage, under different discharge rates, the lower voltage limit of accumulator is different with non-linear capacity of later stage, here will introduce empirical value and calculate, tabulation is the lower voltage limit (V1) and the estimated capacity in later stage (Cs) of 12V battery below.
| Discharge rate of battery | Battery lower voltage limit (V1) | Phase III estimated capacity (Cs) | |
| 0.1 | 12V | 10％C | |
| 0.2C | 11.6 |
20％C | |
| 0.3C | 11.2 |
30％C |
The prediction and calculation of the non-linear capacity of later stage accumulator: Cc=f * Cs
Summation at last obtains the prediction capacity of accumulator: C survey=C
0+ C
2+ C
3+ C
c
By the analytical calculation scheme of this accumulator capacity, battery discharge constantly just can dope whole accumulator capacities to T.
The aforementioned calculation scheme can be used for the accumulator of various voltages and capacity, dopes the capacity of accumulator in 1 hour in battery discharging, and predicted value and actual value have relatively reached 95% above degree of accuracy, have reached the purpose of successfully predicting accumulator capacity.
Claims (3)
1. accumulator data intelligence analyser, include outer casing base, and cover shell of top cover in the shell base top, described outer casing base inside is provided with circuit board, outer casing base inside also is provided with the power module of promising each circuit supply of circuit board, it is characterized in that: described circuit board is integrated with control circuit, accumulator signal acquisition circuit;
Described control circuit comprises cpu chip, be connected to the totalizer chip on the P10 of described cpu chip～P14 pin, be connected to house dog memory chip and clock and date chip on P16～P17 pin, be connected to sheet on P20～P27 pin and select latch, the ALE pin of described cpu chip also selects the LE pin of latch to be connected by Sheffer stroke gate with described, be connected with the RAM module interface on the read-write pin of cpu chip, the P00 of cpu chip～P07 pin, P20～P27 pin is connected to described RAM module interface by lead, the X1 of cpu chip, be connected to crystal oscillator between the X2 pin, the crystal oscillator two ends are connected with ground connection behind the electric capacity respectively; Described is selected the Q0 of latch, Q1 pin to be connected one by one with the RST pin of date chip with CS pin, the clock of house dog storer by lead respectively, Q3～Q5 pin is connected with A, B, the C pin of a code translator one by one by lead respectively, the Q7 pin is connected to described RAM module interface, and described is selected the Q1～Q4 of latch also to be connected one by one with the S1～S4 pin of described totalizer chip by lead; The A1 of described totalizer chip～A4 pin, B1 pin are connected with the P10～P14 pin of cpu chip one by one by lead respectively, B2～B4 pin, CI pin ground connection; The SO of described house dog storer, SI pin are connected with the P16 pin of cpu chip, and the SLK pin is connected with the P17 pin of cpu chip; Described clock is connected with P16, the P17 pin of cpu chip respectively with I/O pin, the CLK pin of date chip;
Described accumulator signal acquisition circuit includes the analog to digital converter chip, two photoelectric relays, two electronic analog swtichs and input interface, a photoelectric relay is reserved with two pins, be connected one by one with the IN-pin with the IN+ of described analog to digital converter chip by lead respectively, the voltage of accumulator, current signal is by described input interface input, described input interface has a plurality of pin outputs, be connected one by one with a plurality of pins of two photoelectric relays by lead respectively, also have a plurality of pins on the described photoelectric relay as output pin, be connected one by one with the I/O1～I/O15 pin of an electronic analog swtich separately respectively, the A of an electronic analog swtich, B, C, the D pin is connected with the P10～P13 pin of described cpu chip one by one by lead, the A of another electronic analog swtich, B, C, the D pin is connected with the S1～S4 pin of described totalizer chip one by one by lead, the INH pin of described two electronic analog swtichs is connected with the Y0 pin of described code translator by lead respectively, the SDO pin of described analog to digital converter chip, the SCLK pin is the P16 by lead and described cpu chip respectively, the P17 pin connects one by one, and the CS pin of analog to digital converter chip selects the Q2 pin of latch to be connected by lead with described.
2. accumulator data intelligence analyser according to claim 1, it is characterized in that: described cpu chip model is SM5964, described is selected the latch model is HC373, described house dog storer model is X5045, described time and date chip model is DS1302, described totalizer chip model is MC14008, and described code translator model is 74HC138.
3. accumulator data intelligence analyser according to claim 1 is characterized in that: described electronic analog swtich model is CD4067, and described analog to digital converter chip model is CS5513.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010201026364U CN201607523U (en) | 2010-01-26 | 2010-01-26 | Battery data intelligent analyzer |
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| CN2010201026364U CN201607523U (en) | 2010-01-26 | 2010-01-26 | Battery data intelligent analyzer |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623760A (en) * | 2011-01-26 | 2012-08-01 | 上海樟村电子有限公司 | Battery management system |
| CN105353310A (en) * | 2015-08-28 | 2016-02-24 | 陈宇星 | Method and system of discharge detection of storage battery |
| CN106253412A (en) * | 2016-09-06 | 2016-12-21 | 广州市凯捷电源实业有限公司 | There is the accumulator of detection function |
| CN108882545A (en) * | 2018-07-11 | 2018-11-23 | 昆山仕优威电子科技有限公司 | A kind of UV LED curing system |
-
2010
- 2010-01-26 CN CN2010201026364U patent/CN201607523U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623760A (en) * | 2011-01-26 | 2012-08-01 | 上海樟村电子有限公司 | Battery management system |
| CN105353310A (en) * | 2015-08-28 | 2016-02-24 | 陈宇星 | Method and system of discharge detection of storage battery |
| CN106253412A (en) * | 2016-09-06 | 2016-12-21 | 广州市凯捷电源实业有限公司 | There is the accumulator of detection function |
| CN108882545A (en) * | 2018-07-11 | 2018-11-23 | 昆山仕优威电子科技有限公司 | A kind of UV LED curing system |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101013 Termination date: 20180126 |
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| CF01 | Termination of patent right due to non-payment of annual fee |