CN201378315Y - Integrated circuit with a plurality of transistors - Google Patents

Abstract

The utility model provides an integrated circuit for access to universal serial bus device is carried out through universal serial bus 3.0 socket. The integrated circuit comprises a plurality of pins and a control unit. The plurality of pins comprise a first group for receiving and transmitting a first differential pair signal of the universal serial bus device; a second group for receiving a second differential pair signal from the USB device; and a third group for transmitting the third differential pair signal to the USB device. The second group is arranged between the first group and the third group. The control unit controls the plurality of pins to receive or transmit a first differential pair signal, a second differential pair signal or a third differential pair signal. The utility model discloses a different pins that will correspond to same USB pin group dispose in adjacent position, can avoid the lead wire between different sockets and different the control unit's the USB pin group to have the condition of crisscross interference to take place.

Description

integrated circuit

technical field

The utility model relates to an integrated circuit, in particular to an integrated circuit with a universal serial bus 3.0 function.

Background technique

Universal Serial Bus (USB) is a serial bus standard for connecting external devices, which can support hot plug (Hot plug) and plug and play (Plug and Play) and other functions.

Currently, the USB 2.0 specification can provide low-speed, full-speed and high-speed transmission, which can respectively support maximum data volumes of 1.5 Mbps, 12 Mbps and 480 Mbps. However, with the increase of complex functions, electronic products require a higher USB transfer rate in order to access data from external devices and execute related operating procedures more quickly.

Therefore, the USB Implementers Forum (USB Implementers Forum) has formulated the specification of USB3.0, which can provide both Super Speed (Super Speed) and non-Super Speed (USB2.0) information exchange, among which Super Speed transmission can support a maximum of 5Gbps amount of data.

Utility model content

The utility model provides an integrated circuit for accessing a universal serial bus device through a universal serial bus 3.0 socket. The above-mentioned integrated circuit includes: a plurality of pins, coupled to the above-mentioned USB 3.0 socket through a plurality of leads, including: a first group for receiving and transmitting a first differential signal of the above-mentioned USB device A pair of signals, wherein the above-mentioned first differential pair signal is a signal corresponding to the Universal Serial Bus 2.0 of the above-mentioned Universal Serial Bus device; a second group is used to receive a second differential signal from the above-mentioned Universal Serial Bus device Dynamic pair signals, wherein the second differential pair signal is a signal corresponding to the Universal Serial Bus 3.0 of the aforementioned Universal Serial Bus device; and a third group, used to transmit a third differential pair signal to the above-mentioned universal serial bus A serial bus device, wherein the third differential pair signal is a signal corresponding to the universal serial bus 3.0 of the universal serial bus device, wherein the second group is set in the first group and the third group and a control unit, configured to control the pins to receive or transmit the first differential pair signal, the second differential pair signal, or the third differential pair signal.

Moreover, the utility model provides an integrated circuit configured in a specific package, and the integrated circuit is used to access multiple USB devices through multiple USB 3.0 sockets. The above-mentioned integrated circuit includes: a plurality of pin groups, wherein each pin group is arranged on a different side of the above-mentioned specific package and coupled to the corresponding above-mentioned USB 3.0 socket, wherein each of the above-mentioned pin groups includes : a first subgroup, for receiving and transmitting a first differential pair (differential pair) signal of the above-mentioned universal serial bus device; a second subgroup, for receiving from the above-mentioned universal serial bus device A second differential pair signal; and a third subgroup for transmitting a third differential pair signal to the above-mentioned universal serial bus device, wherein the second subgroup is set in the first subgroup and between the third subgroup; and a plurality of control units, wherein each control unit controls the corresponding pin group to receive or transmit the corresponding first differential pair signal and the second differential pair signal Or the above-mentioned third differential pair signal.

The utility model disposes different pins corresponding to the same USB pin group in adjacent positions, so as to avoid crossing interference between different sockets and USB pin groups of different control units.

Description of drawings

Figure 1A is a socket showing the standard specification-A of USB 3.0;

FIG. 1B is a socket showing the standard specification-B of USB 3.0;

Figure 1C is a micro-profile-B socket showing USB 3.0;

Figure 1D is a receptacle showing Micro-Spec-AB of USB 3.0;

FIG. 2A is a pin diagram showing Standard Specification-A and Standard Specification-B;

FIG. 2B is a pin diagram showing micro-spec-B and micro-spec-AB;

FIG. 3A is a circuit diagram showing an integrated circuit and a standard specification-A socket according to an embodiment of the present invention;

3B to 3D are circuit diagrams respectively showing an integrated circuit according to another embodiment of the present invention and a socket of standard specification-A;

Fig. 4 is a circuit diagram showing an integrated circuit and a standard specification-B socket according to an embodiment of the present invention;

5 is a circuit diagram showing an integrated circuit and a Micro-B socket according to an embodiment of the present invention;

Fig. 6 is a circuit diagram showing an integrated circuit and a socket of micro-size-AB according to an embodiment of the present invention;

7 is a circuit diagram showing an integrated circuit and a plurality of USB 3.0 sockets according to an embodiment of the present invention; and

8 is a circuit diagram showing an integrated circuit and multiple USB 3.0 sockets according to another embodiment of the present invention.

Detailed ways

In order to make the above-mentioned and other purposes, features and advantages of the present utility model more obvious and understandable, the preferred embodiments are specially cited below, together with the accompanying drawings, and are described in detail as follows:

Example:

Figure 1A to Figure 1D show different specifications of USB 3.0 receptacle. FIG. 1A and FIG. 1B respectively show standard-A (Standard-A) and standard-B (Standard-B) sockets, and their detailed pin diagrams are shown in FIG. 2A . FIG. 1C and FIG. 1D respectively show Micro-B (Micro-B) and Micro-AB (Micro-AB) sockets, and their detailed pin diagrams are shown in FIG. 2B . USB 3.0 can provide both Super Speed (Super Speed) and non-Super Speed (ie USB2.0) information exchange. Therefore, a device conforming to the USB 3.0 specification may include the differential pair signal D+/D- of USB 2.0, the differential pair signal of the Super Speed specification, the ground line GND and the power line VBUS, among which the Super Speed The standard differential pair signal can be divided into transmission differential pair signal SSTX+/SSTX- and receiving differential pair signal SSRX+/SSRX-, and the power line VBUS is a signal line that provides a supply voltage to USB 3.0 devices.

FIG. 3A is a circuit diagram showing an integrated circuit and a standard specification-A socket according to an embodiment of the present invention. In FIG. 3A , the integrated circuit 100 and the socket 200 are disposed on a printed circuit board of an electronic device, wherein the integrated circuit 100 can access an external USB device (not shown) through the socket 200 . As shown in FIG. 3A , the integrated circuit 100 includes a control unit 120 , wherein the control unit 120 is a physical layer circuit of the USB, and has a plurality of pins coupled to the socket 200 for accessing external USB devices. The plurality of pins includes a first group consisting of pins 121 and 122, a second group consisting of pins 123 and 124, and a third group consisting of pins 125 and 126. groups, wherein the second group is set between the first group and the third group. In the embodiment of the present invention, the pin 121 and the pin 122 can also be defined as the pin D- and the pin D+ of the integrated circuit 100, which are respectively coupled to the pin D- and the pin D+ of the socket 200. To receive and transmit differential pair signals corresponding to USB2.0 in USB devices. Therefore, when a device supporting USB2.0 is inserted into the socket 200 , the control unit 120 can receive and transmit the differential pair signals D+ and D− through the pins 121 and 122 to access the USB device.

Furthermore, in an embodiment of the present invention, the pin 123 and the pin 124 can also be defined as the pin SSRX+ and the pin SSRX− of the integrated circuit 100 , as shown in FIG. 3A . The pin 123 and the pin 124 are respectively coupled to the pin StdA_SSRX− and the pin StdA_SSRX+ of the receptacle 200 , which are used for receiving the differential pair signal corresponding to USB 3.0 in the USB device. Therefore, when a device supporting the SuperSpeed specification is inserted into the socket 200, the control unit 120 can receive the differential pair signals SSRX+ and SSRX- from the USB device through the pins 123 and 124, so as to receive data from the USB device and Do relevant processing. In an embodiment of the present invention, the pin 125 and the pin 126 can also be defined as the pin SSTX− and the pin SSTX+ of the integrated circuit 100 , as shown in FIG. 3A . The pin 125 and the pin 126 are respectively coupled to the pin StdA_SSTX− and the pin StdA_SSTX+ of the receptacle 200 , which are used to transmit the differential pair signal corresponding to USB3.0 to the USB device. Therefore, when a device supporting the SuperSpeed specification is inserted into the receptacle 200 , the control unit 120 can transmit the differential pair signals SSTX− and SSTX+ through the pins 125 and 126 to transmit data to the USB device. In addition, in the integrated circuit 100, the control unit 120 can also include a ground pin GND, which is coupled to the ground signal line of the socket 200, wherein the ground pin GND can be configured between the pin 122 and the pin 123 or the pin between 124 and pin 125. In one embodiment, the ground signal line of the socket 200 can be directly provided by the ground terminal of the printed circuit board. Furthermore, the control unit 120 may also include a power pin VCC and a power pin VDD for providing an operating voltage to the control unit 120 .

According to the application of USB 3.0, the differential pair signals SSTX- and SSTX+ can be reversed, and the differential pair signals SSRX- and SSRX+ can also be reversed. Therefore, in the integrated circuit 100 , the positions of the pin 123 and the pin 124 can be reversed, and the positions of the pin 125 and the pin 126 can be reversed, as shown in FIGS. 3B to 3D .

FIG. 4 is a circuit diagram showing an integrated circuit and a standard specification-B socket 300 according to an embodiment of the present invention. FIG. 5 is a circuit diagram showing an integrated circuit and a Micro-B socket 400 according to an embodiment of the present invention. FIG. 6 is a circuit diagram showing an integrated circuit and a Micro-AB socket 500 according to an embodiment of the present invention. Similarly, the integrated circuit 100 and the socket 300 , 400 or 500 can be disposed on a printed circuit board of an electronic device, wherein the integrated circuit 100 can access an external USB device through the socket 300 , 400 or 500 . In the embodiment of the present utility model, by configuring the pins of the control unit, the pins 123 and 124 (receiving differential signals) are set in the middle of a group of USB pin groups of the integrated circuit 100, which can be easily compared with different The standard socket is connected, and the crosstalk between the lead wires between the socket and the USB pin group can be avoided.

FIG. 7 is a circuit diagram showing an integrated circuit 700 and a plurality of USB 3.0 sockets according to an embodiment of the present invention. The integrated circuit 700 is configured in a Quad Flat No-lead Package (QFN) or a low profile Quad Flat Package (LQFP). In the embodiment of the present invention, the integrated circuit 700 can be configured with multiple sets of USB pin groups for accessing different USB devices. For example, an integrated circuit can be configured with multiple sets of control units in the same instance, each control unit has a set of USB pin groups, wherein each control unit is a physical layer circuit of USB. As shown in FIG. 7 , the USB pin group 730 of the control unit 710 is coupled to the socket 750 for accessing the first USB device. The USB pin group 740 of the control unit 720 is coupled to the socket 760 for accessing the second USB device, wherein the control units 710 and 720 are both disposed on the same side of the integrated circuit 700 . Therefore, the USB pin groups of different control units can be respectively connected to the corresponding sockets, and the cross interference between different sockets and the USB pin groups of different control units can be avoided. In one embodiment, the socket 750 and the socket 760 may be USB 3.0 sockets of different specifications. For example, receptacle 750 is a gauge-A receptacle and receptacle 760 is a gauge-B receptacle.

FIG. 8 is a circuit diagram showing an integrated circuit 800 and multiple USB 3.0 sockets according to another embodiment of the present invention. The integrated circuit 800 is configured in a Quad Flat No-lead Package (QFN) or a low profile Quad Flat Package (LQFP). In this embodiment, the quadflat no-lead package or the thin quadflat lead package is just an example, but it is not intended to limit the present invention. In one embodiment, the integrated circuit 800 can be configured with multiple sets of USB pin groups for accessing different USB devices. For example, the integrated circuit can configure a control unit and its associated USB pin groups on different sides. As shown in FIG. 8 , the USB pin group 810 of the first control unit is disposed on the first side of the integrated circuit 800 and coupled to the socket 850 for accessing the first USB device. The USB pin group 820 of the second control unit is disposed on the second side of the integrated circuit 800 and coupled to the socket 860 for accessing the second USB device. The USB pin group 830 of the third control unit is disposed on the third side of the integrated circuit 800 and coupled to the socket 870 for accessing the third USB device. The USB pin group 840 of the fourth control unit is configured on the fourth side of the integrated circuit 800 and coupled to the socket 880 for accessing the fourth USB device. Therefore, different pin groups can be respectively connected to the corresponding sockets, and cross interference between leads between different pin groups can be avoided. In one embodiment, the sockets 850, 860, 870, and 880 may be USB 3.0 sockets of different specifications, which may be determined according to actual applications. For example, sockets 850 and 860 are gauge-A sockets and sockets 870 and 880 are gauge-B sockets. Alternatively, receptacle 850 is a standard size-A receptacle, receptacle 860 is a standard size-B receptacle, receptacle 870 is a micro-size-AB receptacle, and receptacle 880 is a micro-size-B receptacle.

Furthermore, the integrated circuit of the present invention can also be configured in other packages, such as flip chip package (Flip Chip) or ball grid array package (Ball Grid Array, BGA). By arranging different pins corresponding to the same USB pin group in adjacent positions, it is possible to avoid crossover interference between different sockets and USB pin groups of different control units.

The above description is only a preferred embodiment of the present utility model, but it is not intended to limit the scope of the present utility model, any person familiar with this technology, without departing from the spirit and scope of the utility model, can Further improvements and changes are made, so the protection scope of the present utility model should be determined by the scope defined in the claims of the present application.

A brief description of the symbols in the drawings is as follows:

1-9, 121-126: pins;

100, 700, 800: integrated circuits;

120, 710, 720: control unit;

200, 300, 400, 500, 750, 760, 850, 860, 870, 880: socket;

730, 740, 810, 820, 830, 840: pin groups.

Claims (20)

1. an integrated circuit is characterized in that, in order to by a USB (universal serial bus) 3.0 sockets one universal serial bus device is carried out access, this integrated circuit comprises:

A plurality of pins are coupled to above-mentioned USB (universal serial bus) 3.0 sockets by a plurality of lead-in wires, comprising:

One first group, in order to one first differential-pair signal that receives and transmit above-mentioned universal serial bus device, wherein above-mentioned first differential-pair signal is the signal corresponding to the USB (universal serial bus) 2.0 of above-mentioned universal serial bus device;

One second group, in order to receive one second differential-pair signal from above-mentioned universal serial bus device, wherein above-mentioned second differential-pair signal is the signal corresponding to the USB (universal serial bus) 3.0 of above-mentioned universal serial bus device; And

One the 3rd group, in order to transmit one the 3rd differential-pair signal to above-mentioned universal serial bus device, wherein above-mentioned the 3rd differential-pair signal is the signal corresponding to the USB (universal serial bus) 3.0 of above-mentioned universal serial bus device, and wherein above-mentioned second group is arranged between above-mentioned first group and above-mentioned the 3rd group; And

One control module receives or transmits above-mentioned first differential-pair signal, above-mentioned second differential-pair signal or above-mentioned the 3rd differential-pair signal in order to control above-mentioned a plurality of pin.

2. integrated circuit according to claim 1 is characterized in that, above-mentioned first group comprises:

One first pin is coupled to the pin D-of above-mentioned USB (universal serial bus) 3.0 sockets; And

One second pin is coupled to the pin D+ of above-mentioned USB (universal serial bus) 3.0 sockets.

3. integrated circuit according to claim 2 is characterized in that, above-mentioned second group comprises:

One the 3rd pin is coupled to the pin SSRX-of above-mentioned USB (universal serial bus) 3.0 sockets; And

One the 4th pin is coupled to the pin SSRX+ of above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned the 3rd pin is disposed between above-mentioned second pin and above-mentioned the 4th pin.

4. integrated circuit according to claim 3 is characterized in that, above-mentioned the 3rd group comprises:

One the 5th pin is coupled to the pin SSTX-of above-mentioned USB (universal serial bus) 3.0 sockets; And

One the 6th pin is coupled to the pin SSTX+ of above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned the 5th pin is disposed between above-mentioned the 4th pin and above-mentioned the 6th pin.

5. integrated circuit according to claim 3 is characterized in that, above-mentioned the 3rd group comprises:

One the 5th pin is coupled to the pin SSTX+ of above-mentioned USB (universal serial bus) 3.0 sockets; And

One the 6th pin is coupled to the pin SSTX-of above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned the 5th pin is disposed between above-mentioned the 4th pin and above-mentioned the 6th pin.

6. integrated circuit according to claim 2 is characterized in that, above-mentioned second group comprises:

One the 3rd pin is coupled to the pin SSRX+ of above-mentioned USB (universal serial bus) 3.0 sockets; And

One the 4th pin is coupled to the pin SSRX-of above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned the 3rd pin is disposed between above-mentioned second pin and above-mentioned the 4th pin.

7. integrated circuit according to claim 6 is characterized in that, above-mentioned the 3rd group comprises:

One the 5th pin is coupled to the pin SSTX+ of above-mentioned USB (universal serial bus) 3.0 sockets; And

One the 6th pin is coupled to the pin SSTX-of above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned the 5th pin is disposed between above-mentioned the 4th pin and above-mentioned the 6th pin.

8. integrated circuit according to claim 6 is characterized in that, above-mentioned the 3rd group comprises:

One the 5th pin is coupled to the pin SSTX-of above-mentioned USB (universal serial bus) 3.0 sockets; And

One the 6th pin is coupled to the pin SSTX+ of above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned the 5th pin is disposed between above-mentioned the 4th pin and above-mentioned the 6th pin.

9. integrated circuit according to claim 1 is characterized in that, above-mentioned USB (universal serial bus) 3.0 sockets are the socket of standard specification-A, standard specification-B, little specification-AB or little specification-B.

10. integrated circuit according to claim 1 is characterized in that, above-mentioned pin more comprises a ground connection pin, is arranged between above-mentioned first group and above-mentioned second group.

11. integrated circuit according to claim 1 is characterized in that, above-mentioned pin more comprises a ground connection pin, is arranged between above-mentioned second group and above-mentioned the 3rd group.

12. an integrated circuit is characterized in that, is disposed in the special package, in order to by a plurality of USB (universal serial bus) 3.0 sockets a plurality of universal serial bus devices are carried out access, this integrated circuit comprises:

A plurality of pin group, wherein each pin group is arranged at the not homonymy of above-mentioned special package and is coupled to corresponding above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned each pin group comprises:

One first subgroup is in order to one first differential-pair signal that receives and transmit above-mentioned universal serial bus device;

One second subgroup comes from one second differential-pair signal of above-mentioned universal serial bus device in order to reception; And

One the 3rd subgroup, in order to transmit one the 3rd differential-pair signal to above-mentioned universal serial bus device, wherein above-mentioned second subgroup is arranged between above-mentioned first subgroup and above-mentioned the 3rd subgroup; And

A plurality of control modules, wherein the corresponding above-mentioned pin group of each control module control receives or transmits corresponding above-mentioned first differential-pair signal, above-mentioned second differential-pair signal or above-mentioned the 3rd differential-pair signal,

Wherein above-mentioned USB (universal serial bus) 3.0 sockets are the socket of standard specification-A, standard specification-B, little specification-AB or little specification-B.

13. integrated circuit according to claim 12 is characterized in that, above-mentioned special package is four flat-sided flat no pin package or slim four flat-sided flat pin package.

14. integrated circuit according to claim 12 is characterized in that, above-mentioned first subgroup comprises:

One first pin is coupled to the pin D-of above-mentioned USB (universal serial bus) 3.0 sockets; And

One second pin is coupled to the pin D+ of above-mentioned USB (universal serial bus) 3.0 sockets.

15. integrated circuit according to claim 14 is characterized in that, above-mentioned second subgroup comprises:

One the 3rd pin is coupled to the pin SSRX-of above-mentioned USB (universal serial bus) 3.0 sockets; And

One the 4th pin is coupled to the pin SSRX+ of above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned the 3rd pin is disposed between above-mentioned second pin and above-mentioned the 4th pin.

16. integrated circuit according to claim 15 is characterized in that, above-mentioned the 3rd subgroup comprises:

One the 5th pin is coupled to the pin SSTX-of above-mentioned USB (universal serial bus) 3.0 sockets; And

One the 6th pin is coupled to the pin SSTX+ of above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned the 5th pin is disposed between above-mentioned the 4th pin and above-mentioned the 6th pin.

17. integrated circuit according to claim 15 is characterized in that, above-mentioned the 3rd subgroup comprises:

One the 5th pin is coupled to the pin SSTX+ of above-mentioned USB (universal serial bus) 3.0 sockets; And

One the 6th pin is coupled to the pin SSTX-of above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned the 5th pin is disposed between above-mentioned the 4th pin and above-mentioned the 6th pin.

18. integrated circuit according to claim 14 is characterized in that, above-mentioned second subgroup comprises:

One the 3rd pin is coupled to the pin SSRX+ of above-mentioned USB (universal serial bus) 3.0 sockets; And

One the 4th pin is coupled to the pin SSRX-of above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned the 3rd pin is disposed between above-mentioned second pin and above-mentioned the 4th pin.

19. integrated circuit according to claim 18 is characterized in that, above-mentioned the 3rd subgroup comprises:

One the 5th pin is coupled to the pin SSTX+ of above-mentioned USB (universal serial bus) 3.0 sockets; And

One the 6th pin is coupled to the pin SSTX-of above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned the 5th pin is disposed between above-mentioned the 4th pin and above-mentioned the 6th pin.

20. integrated circuit according to claim 18 is characterized in that, above-mentioned the 3rd subgroup comprises:

One the 5th pin is coupled to the pin SSTX-of above-mentioned USB (universal serial bus) 3.0 sockets; And

One the 6th pin is coupled to the pin SSTX+ of above-mentioned USB (universal serial bus) 3.0 sockets, and wherein above-mentioned the 5th pin is disposed between above-mentioned the 4th pin and above-mentioned the 6th pin.

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