CN1975948B - Chip Capacitor - Google Patents
Chip Capacitor Download PDFInfo
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- CN1975948B CN1975948B CN2006101567556A CN200610156755A CN1975948B CN 1975948 B CN1975948 B CN 1975948B CN 2006101567556 A CN2006101567556 A CN 2006101567556A CN 200610156755 A CN200610156755 A CN 200610156755A CN 1975948 B CN1975948 B CN 1975948B
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Abstract
Description
本申请是申请日为2003年10月30日、申请号为200310104724.2、发明名称为“片式电容和用它的IC插座、片式电容的制造方法”的申请的分案申请。This application is a divisional application of the application dated October 30, 2003, the application number 200310104724.2, and the title of the invention is "Chip Capacitor, IC Socket Using It, and Manufacturing Method of Chip Capacitor".
技术领域technical field
本发明涉及用于高速IC和处理器的噪声吸收或滤波器等的片式电容和用它的IC插座以及片式电容的制造方法。The present invention relates to chip capacitors used for noise absorption or filters of high-speed ICs and processors, IC sockets using the chip capacitors, and methods for manufacturing chip capacitors.
背景技术Background technique
近年来,个人计算机和通信设备的高速化正在进展中,要求用于它们的电子部件实现小型化和高频响应。与此相伴也需要作为一个电子部件的电容实现大电容量化、低阻抗化。特别是,用于驱动计算机CPU的电源电路,在电路设计上,作为高频响应要求具有噪声和脉动电流的吸收性。因此,强烈要求具有低ESR(等效串联电阻)、低ESL(等效串联阻抗)、耐高脉动电流的大电容量的电解电容。为了与这种要求对应,现状中将多个小形的芯片型电容配置在CPU周边的接近CPU的位置上。In recent years, the speedup of personal computers and communication equipment is progressing, and miniaturization and high-frequency response of electronic components used for them are required. Along with this, it is also necessary to realize large capacitance and low impedance as a capacitor as an electronic component. In particular, power supply circuits for driving computer CPUs are required to absorb noise and pulsating current as a high-frequency response in terms of circuit design. Therefore, there is a strong demand for electrolytic capacitors with low ESR (equivalent series resistance), low ESL (equivalent series impedance), and large capacitance that can withstand high pulsating currents. In order to meet such demands, many small chip-type capacitors are currently arranged around the CPU at positions close to the CPU.
图53表示根据上述已有构成的CPU的周边。将连接用插头(以下,称为插头)402设置在以CPU为代表的IC401的下面。将IC插座(以下,称为插座)403焊接在印刷电路配线板(以下,称为基板)404上。接近这样构成的IC401地安装芯片式电容(以下,称为电容)405。与取代电容而用电阻的上述安装状态类似的结构例如在日本昭和60年公布的60-130150号专利公报中揭示的。Fig. 53 shows the periphery of the CPU according to the above conventional configuration. A connection plug (hereinafter, referred to as a plug) 402 is provided under an IC 401 represented by a CPU. An IC socket (hereinafter referred to as socket) 403 is soldered to a printed wiring board (hereinafter referred to as substrate) 404 . A chip capacitor (hereinafter referred to as capacitor) 405 is mounted close to IC 401 configured in this way. A structure similar to the above mounting state in which a resistor is used instead of a capacitor is disclosed, for example, in Japanese Patent Publication No. 60-130150 published in 1960.
在IC401中具有478个插头402,并且在插座403的基板404上设置从IC401引出用的配线图案(图中未画出)。因此,在这种安装状态中,随着安装部件的增加,IC401周边的电容405和图中未画出的其它电子部件的安装位置远离IC401,并且使安装面积不足。The IC 401 has 478 plugs 402 , and a wiring pattern (not shown) for leading out from the IC 401 is provided on the substrate 404 of the socket 403 . Therefore, in this mounted state, as the number of mounted components increases, the capacitor 405 around the IC 401 and other electronic components not shown in the figure are mounted away from the IC 401 and the mounting area is insufficient.
另一方面,CPU的工作频率正在上升,为了吸收噪声和供给电流必须使大电容量的低ESR并且低ESL的芯片型电容尽可能接近CPU。因此在上述的现行技术中正在失去这种频率响应。On the other hand, the operating frequency of the CPU is increasing. In order to absorb noise and supply current, it is necessary to make a large-capacity low-ESR and low-ESL chip-type capacitor as close as possible to the CPU. This frequency response is thus being lost in the prior art described above.
具体地说,因为插座403的高度约为3mm,从插座403到电容405的距离约为数十mm,所以对于CPU,ESL上升,频率越高阻抗越上升。因此,在高频区域不能够充分发挥低ESL的电容性能。Specifically, because the height of the socket 403 is about 3 mm, and the distance from the socket 403 to the capacitor 405 is about tens of mm, the ESL increases for the CPU, and the higher the frequency, the higher the impedance. Therefore, the capacitive performance of low ESL cannot be fully exhibited in a high frequency region.
发明内容Contents of the invention
本发明中的片式电容,备有:在单面上具有阳极电极部分的阳极片、在单面上具有阴极电极部分的阴极片、配设在上述阳极电极部分和上述阴极电极部分之间,并且含有电解液的分隔器、配设在上述阳极片和上述阴极片之间,设有嵌入上述分隔器的开口部分,与上述阳极片和上述阴极片接合成一体,密封上述分隔器的密封片。The chip capacitor in the present invention is provided with: an anode sheet having an anode electrode part on one side, a cathode sheet having a cathode electrode part on one side, arranged between the above-mentioned anode electrode part and the above-mentioned cathode electrode part, And the separator containing the electrolytic solution is arranged between the above-mentioned anode sheet and the above-mentioned cathode sheet, and an opening part is provided to be embedded in the above-mentioned separator, and the above-mentioned anode sheet and the above-mentioned cathode sheet are joined together to form a sealing sheet for sealing the above-mentioned separator .
附图说明Description of drawings
图1是表示根据本发明的实施形态1的片式电容及其使用状态的分解立体图。Fig. 1 is an exploded perspective view showing a chip capacitor and its usage state according to
图2是表示使IC与图1的片式电容连接的状态的截面图。2 is a cross-sectional view showing a state in which an IC is connected to the chip capacitor of FIG. 1 .
图3A~图3D是表示图1中的接触部分的构成的平面图。3A to 3D are plan views showing the configuration of the contact portion in FIG. 1 .
图4是表示根据本发明的实施形态2的片式电容的构成的分解立体图。Fig. 4 is an exploded perspective view showing the structure of a chip capacitor according to
图5是图4的使用片式电容的电容元件的截面图。FIG. 5 is a cross-sectional view of the capacitive element using the chip capacitor shown in FIG. 4 .
图6是表示图4的片式电容的使用状态的分解立体图。FIG. 6 is an exploded perspective view showing a state of use of the chip capacitor of FIG. 4 .
图7是表示使IC与图4的片式电容连接的状态的截面图。7 is a cross-sectional view showing a state where an IC is connected to the chip capacitor of FIG. 4 .
图8是表示根据本发明的实施形态3的片式电容的构成的分解立体图。Fig. 8 is an exploded perspective view showing the structure of a chip capacitor according to
图9是图8的片式电容的截面图。FIG. 9 is a cross-sectional view of the chip capacitor shown in FIG. 8 .
图10是表示根据本发明的实施形态4的片式电容的构成的分解立体图。Fig. 10 is an exploded perspective view showing the structure of a chip capacitor according to
图11是图10的片式电容的截面图。FIG. 11 is a cross-sectional view of the chip capacitor shown in FIG. 10 .
图12是表示根据本发明的实施形态5的片式电容的构成的分解立体图。Fig. 12 is an exploded perspective view showing the structure of a chip capacitor according to
图13是图12的片式电容的截面图。FIG. 13 is a cross-sectional view of the chip capacitor shown in FIG. 12 .
图14是表示根据本发明的实施形态6的片式电容及其使用状态的截面图。Fig. 14 is a cross-sectional view showing a chip capacitor according to Embodiment 6 of the present invention and its state of use.
图15是表示根据本发明的实施形态7的片式电容及其使用状态的分解立体图。Fig. 15 is an exploded perspective view showing a chip capacitor and its usage state according to Embodiment 7 of the present invention.
图16是图15的片式电容及其周边的截面图。FIG. 16 is a cross-sectional view of the chip capacitor of FIG. 15 and its surroundings.
图17是表示图15的片式电容的构成的分解立体图。FIG. 17 is an exploded perspective view showing the configuration of the chip capacitor of FIG. 15 .
图18是表示根据本发明的实施形态8的片式电容的构成的截面图。Fig. 18 is a cross-sectional view showing the structure of a chip capacitor according to Embodiment 8 of the present invention.
图19是表示根据本发明的实施形态9的片式电容的构成的截面图。Fig. 19 is a cross-sectional view showing the structure of a chip capacitor according to
图20是图19的片式电容的分解立体图。FIG. 20 is an exploded perspective view of the chip capacitor of FIG. 19 .
图21A,图21B是表示根据本发明的实施形态10的片式电容的接触部分的构成的平面图。21A and 21B are plan views showing the configuration of a contact portion of a chip capacitor according to Embodiment 10 of the present invention.
图22A,图22B是表示根据本发明的实施形态10的片式电容的接触部分的其它例子的平面图。图22C,图22D分别是图22A,图22B的截面图。22A and 22B are plan views showing other examples of contact portions of the chip capacitor according to Embodiment 10 of the present invention. Fig. 22C and Fig. 22D are cross-sectional views of Fig. 22A and Fig. 22B respectively.
图23是表示根据本发明的实施形态11的片式电容的构成的分解立体图。Fig. 23 is an exploded perspective view showing the structure of a chip capacitor according to
图24是表示使IC与图23的片式电容连接的状态的截面图。FIG. 24 is a cross-sectional view showing a state in which an IC is connected to the chip capacitor of FIG. 23 .
图25是表示图23的设有片式电容、表示与IC的连接用插头(pin)和非接触的贯通孔的平面图。FIG. 25 is a plan view showing the chip capacitor in FIG. 23 , a pin for connecting to an IC, and a non-contact through-hole.
图26是表示根据本发明的实施形态12的片式电容的构成的分解立体图。Fig. 26 is an exploded perspective view showing the structure of a chip capacitor according to
图27是表示图26的片式电容的截面图。Fig. 27 is a cross-sectional view showing the chip capacitor of Fig. 26 .
图28是表示使IC与图26的片式电容连接的状态的截面图。FIG. 28 is a cross-sectional view showing a state in which an IC is connected to the chip capacitor of FIG. 26 .
图29是表示图26的片式电容的接触部分的构成的平面图。FIG. 29 is a plan view showing the configuration of a contact portion of the chip capacitor of FIG. 26 .
图30是表示多层层积图26的片式电容的电极箔时的构成的分解立体图。FIG. 30 is an exploded perspective view showing the structure when the electrode foil of the chip capacitor of FIG. 26 is laminated in multiple layers.
图31是表示根据本发明的实施形态13的片式电容的构成的截面图。Fig. 31 is a cross-sectional view showing the structure of a chip capacitor according to
图32是表示根据本发明的实施形态14的片式电容的构成的截面图。Fig. 32 is a cross-sectional view showing the structure of a chip capacitor according to
图33是表示根据本发明的实施形态15的片式电容的构成的截面图。Fig. 33 is a cross-sectional view showing the structure of a chip capacitor according to
图34是表示根据本发明的实施形态16的片式电容的构成的分解斜视图。Fig. 34 is an exploded perspective view showing the structure of a chip capacitor according to Embodiment 16 of the present invention.
图35是表示图34的片式电容的截面图。Fig. 35 is a cross-sectional view showing the chip capacitor of Fig. 34 .
图36是表示使IC与图34的片式电容连接的状态的截面图。36 is a cross-sectional view showing a state where an IC is connected to the chip capacitor of FIG. 34 .
图37是表示图34的片式电容的接触部分的构成的平面图。FIG. 37 is a plan view showing the configuration of a contact portion of the chip capacitor of FIG. 34 .
图38是表示多层层积图34的片式电容的电极箔时的构成的分解立体图。FIG. 38 is an exploded perspective view showing the structure when the electrode foil of the chip capacitor of FIG. 34 is laminated in multiple layers.
图39是表示根据本发明的实施形态17的片式电容的构成的截面图。Fig. 39 is a cross-sectional view showing the structure of a chip capacitor according to
图40是表示根据本发明的实施形态18的片式电容的构成的截面图。Fig. 40 is a cross-sectional view showing the structure of a chip capacitor according to
图41是表示根据本发明的实施形态19的片式电容的构成的截面图。Fig. 41 is a cross-sectional view showing the structure of a chip capacitor according to
图42是表示用根据本发明的实施形态20的片式电容的IC插座及其使用状态的分解立体图。Fig. 42 is an exploded perspective view showing an IC socket using a chip capacitor according to Embodiment 20 of the present invention and its usage state.
图43是构成图42中IC插座的滑动部分的分解立体图。FIG. 43 is an exploded perspective view of a sliding portion constituting the IC socket in FIG. 42. FIG.
图44是表示用图42的IC插座的正面截面图。Fig. 44 is a front sectional view showing the IC socket shown in Fig. 42 .
图45A,图45B是表示用根据本发明的实施形态21的片式电容的IC插座的接触部分的构成的平面图。45A and 45B are plan views showing the configuration of a contact portion of an IC socket using a chip capacitor according to
图46A,图46B是表示用根据本发明的实施形态21的IC插座的接触部分的其它例子的平面图。图46C,46D分别是图46A,图46B的截面图。46A and 46B are plan views showing other examples of contact portions of the IC socket according to
图47A是表示根据本发明的实施形态22的片式电容的制造方法中从原材料到冲压加工工序的阳极片的制造工序图。图47B是根据本发明的实施形态22的片式电容的绝缘片的制造工序图。图47C是根据本发明的实施形态22的片式电容的绝缘片的制造工序图。47A is a diagram showing the manufacturing process of the anode chip from the raw material to the pressing process in the manufacturing method of the chip capacitor according to
图48A是用平面图表示根据本发明的实施形态22的片式电容的制造方法中从完成加工的阴极片、绝缘片和阳极片的贴合到凹部形成工序的制造工序图。图48B是用正面图表示图48A的制造工序图。图48C是用下面图表示图48A的制造工序图。Fig. 48A is a plan view showing the manufacturing process from lamination of the finished cathode sheet, insulating sheet and anode sheet to forming the recess in the manufacturing method of the chip capacitor according to
图49A是用平面图表示根据本发明的实施形态22的片式电容的制造方法中在完成加工的配线层叠片上形成接触部分,安装电容元件的工序的制造工序图。图49B是用正面图表示图49A的制造工序图。图49C是用下面图表示图49A的制造工序图。49A is a manufacturing process diagram showing, in plan view, the steps of forming a contact portion on a finished wiring laminate sheet and mounting a capacitor element in a method of manufacturing a chip capacitor according to
图50是表示根据本发明的实施形态22的片式电容的接触部分的平面图。Fig. 50 is a plan view showing a contact portion of a chip capacitor according to
图51是表示根据本发明的实施形态22的片式电容的电容元件的构成的截面图。Fig. 51 is a cross-sectional view showing the configuration of a capacitive element of a chip capacitor according to
图52A是用平面图表示根据本发明的实施形态22的片式电容的制造方法中从保护安装在完成加工的配线层叠片上的电容元件的盖片的贴附工序到切断成最终的各个片的工序的制造工序图。图52B是用正面图表示图52A的制造工序图。Fig. 52A is a plan view showing the process of attaching the cover sheet for protecting the capacitive element mounted on the completed wiring laminate sheet to cutting into final individual sheets in the method of manufacturing a chip capacitor according to
图53是表示根据已有构成的CPU周边状况的分解立体图。Fig. 53 is an exploded perspective view showing the state of the periphery of the CPU according to a conventional configuration.
具体实施方式Detailed ways
下面,我们一面参照附图一面说明本发明的实施形态。此外,在本发明的各个实施形态中,在形成同样构成的部分上附加同一个标号并省略它们的详细说明。Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, in each embodiment of the present invention, the same reference numerals are attached to the parts having the same configuration, and their detailed descriptions are omitted.
(实施形态1)(Embodiment 1)
图1是表示根据本发明的实施形态1的片式电容及其使用状态的分解立体图,图2是表示使IC与图1的片式电容连接的状态的截面图。将连接用插头(以下,称为插头)2设置在以CPU为代表的IC1的下面。将IC插座(以下,称为插座)3焊接在印刷电路配线板(以下,称为基板)4上。在本实施形态中表示用478个插头的IC组件的例子。1 is an exploded perspective view showing a chip capacitor according to
片式电容(以下,称为电容)5,设置IC1的插头2贯通的贯通孔(以下,称为孔)6。而且只在IC1连接所需的插头2贯通的孔6中形成与插头2导通的接触部分(图中的涂黑部分)。电容5是通过将安装了电容元件9的通用的印刷电路基板(以下,称为基板)8贴合在固定基板(以下,称为基板)10上构成的。The chip capacitor (hereinafter referred to as capacitor) 5 is provided with a through hole (hereinafter referred to as hole) 6 through which the
图3A~图3D表示接触部分7的构成。图3A表示与插头2非接触时的孔6,这时的孔6的大小最好具有插头2的外径2倍以上的大小,因为孔6越大,非接触的可靠性越高。3A to 3D show the configuration of the contact portion 7 . 3A shows the hole 6 when it is not in contact with the
图3B表示需要与插头2接触进行导通时的贯通孔6A。孔6A具有大致的星形,最大径比插头2的外径大,最小径比插头2的外径小。因此,因为与插头2接触的突起部(最小径部分)缓和了由于插头2的插入拔出,上下移动产生的应力,所以能够平滑地进行插头2的插入拔出。FIG. 3B shows the through-
图3C表示需要与同一插头2接触进行导通时的贯通孔6B。孔6B具有大致的椭圆形,对于圆形的插头2的外径,长轴方向比插头2的直径大,短轴方向比插头2的直径小。因为在该形状中没有边缘,所以到插入时的接触部分7的应力小,不易发生龟裂,而且能够得到确实的连接。FIG. 3C shows the through
图3D表示需要与同一插头2接触进行导通时的贯通孔6B的周边。除了图3C所示的孔6B外,在孔6B的短轴方向的两端面上平行地邻接设置了用于吸收由于插头2扩大了孔6B时的应力的缝隙6C。因为缝隙6C能够缓和加在孔6B上的应力,所以能够平滑地进行插头2的插入拔出。FIG. 3D shows the periphery of the through-
可以用以上,图3A~图3D所示的任何一种类型的接触部分,但是也可以只用多角形的接触部分。Any of the types of contact portions shown above in FIGS. 3A to 3D may be used, but only polygonal contact portions may be used.
根据这样构成本实施形态的电容5使IC1的插头2贯通电容5的孔6,安装在插座3上,根据这种构成,通过接触部分7,IC1和电容5导通。用这种简单的构成,能够得到薄型的片式电容5。因为将电容5夹入IC1和插座3之间,所以能够确保将电容元件高密度地安装在片式电容5中的面积。又,因为电容5与IC1的距离近,所以能够减少ESL。According to the
(实施形态2)(Embodiment 2)
图4是表示根据本发明的实施形态2的片式电容的构成的分解立体图,图5是表示用于该片式电容的电容元件的构成的截面图。图6是表示图4的片式电容的使用状态的分解立体图,图7是表示使IC与图4的片式电容连接的状态的截面图。4 is an exploded perspective view showing the structure of a chip capacitor according to
在图4中,在导电性阴极片(以下,称为片)11中设置IC1的连接用插头(以下,称为插头)2贯通的贯通孔(以下,称为孔)12。只在IC1连接所需的插头2贯通的孔12中,形成与插头2导通的接触部分13(图中的涂黑部分)。进一步周边部分14具有弯折成大致L字形进行增强的构成。通过这种构成,可以不用增强材料提高片式电容的弯折强度。将绝缘片(以下,称为片)15配设在片11的外(图中的下面)侧。将由高分子材料构成的绝缘片(以下,称为片)16配设在片11的内(图中的上面)侧,在片16的中央部分设置开口部分20A。In FIG. 4 , a through-hole (hereinafter referred to as a hole) 12 through which a plug (hereinafter referred to as plug) 2 of IC1 penetrates is provided in a conductive cathode sheet (hereinafter referred to as sheet) 11 . Only in the
在导电性阳极片(以下,称为片)17中设置IC1的插头2贯通的贯通孔(以下,称为孔)18。而且只在IC1连接所需的插头2贯通的孔18中形成与插头2导通的接触部分19(图中的涂黑部分)。又,在中央部分设置开口部分20B。片状电容元件21具有阳极取出部分22和阴极取出部分23。片16形成使片11、17之间绝缘的绝缘层。将绝缘片(以下,称为片)24配设在片17的上面。在片24上设置IC1的插头2贯通的贯通孔(以下,称为孔)25。此外,与片11相同,也可以通过使片17的周边部分14弯折成大致L字形进行增强。A through-hole (hereinafter, referred to as a hole) 18 through which the
在根据这样构成的本实施形态的片式电容中,在使片15与外侧接合的导电性片11的内侧上,层积地接合片16和导电性片17。又,将电容元件21配设在设置在片16和片17的中央部分重合的开口部分20A、20B内。因为将电容元件21这样地配设在开口部分20A、20B内,所以能够得到薄型的片式电容。而且电容元件21的阳极取出部分22与片17电连接,阴极取出部分23与片11电连接,进一步为了复盖片17而密封片24。在上述说明中,将开口部分20B设置在片17中,但是也可以设置在片11中。In the chip capacitor according to the present embodiment thus constituted, the
此外,开口部分26、27为了能够分别使试验插头直接与导电性的片11和片17接触而分别设置片15、24。通过这种构成,能够不经过接触部分19实施安装部件的电路芯片和电容元件21的老化工序中的供电。又能够在生产工序中保护与插头2连接的接触部分19。通过扩大地形成开口部分26、27,能够平滑地并且确实地进行生产电容元件21时所需的老化工序中的电力供给。In addition, the
此外,片15、16、24也可以用由环氧树脂和密胺等的绝缘胶、聚乙烯对钛酸盐(PET)、聚丙烯(PP)、聚碳酸脂(PC)构成的片等的绝缘材料和聚酰亚胺(PI)、聚酰胺·酰亚胺(PAI)等的耐热绝缘片形成。又,也可以是用粘合剂进行粘合的构造。又,也可以通过由树脂成形进行覆盖形成外包装,或用绝缘片覆盖表面,或用涂敷材料进行涂敷,或印刷绝缘胶。In addition, the
又,具有接触部分13、19的导电性片11、17用实施了镀金的弹簧用磷青铜和不锈钢(SUS)等的具有弹性的材料构成,从连接稳定性这一点来看是令人满意的。但是片11、17也可以用铜·铁·铝片或将弹性膜和金属箔层叠起来得到的片构成。Also, the
图5是详细表示片状的电容元件21的构成的截面图。在设置了阳极取出部分22的电极体的表面上形成电介质氧化表面膜28。进一步在该表面上通过重合形成由功能性高分子构成的固体电解质层29,进一步在该表面上形成由碳和银胶构成的,形成成为阴极取出部分23的阴极层。构成阴极层的厚度在0.1mm以上0.2mm以下,通过设置在侧面的切去部分30阴极取出部分23的上面与下面导通。FIG. 5 is a cross-sectional view showing in detail the configuration of the chip-shaped
如图6所示,将这样构成的片式电容(以下,称为电容)31,使设置在IC1的下面的插头2贯通在电容31中形成的贯通孔32地,安装在IC插座3中。贯通孔32使贯通孔12、18、25一体化。而且,通过接触部分33(图中的涂黑部分)IC1与电容31导通。接触部分33使接触部分13、19一体化。通过这种简单的构成,能够得到薄型的片式电容31。根据这种构成,因为从插头2的根部连接电容元件21,所以能够大幅度地减少由电容元件21和IC1之间的配线引起的ESL。As shown in FIG. 6, chip capacitor (hereinafter referred to as capacitor) 31 configured in this way is mounted in
此外,如图7所示,在将IC1安装在电容31中的状态中,因为在导电性片11、17上形成的孔12、18插头2大,所以孔12、18与插头2不电连接。另一方面,在片11上形成的接触部分13与插头2A接触进行电连接。与此相对,它的上部的片17的孔18形成得较大。因此,孔18不与连接用插头2A接触,只有片11与插头2A电连接。同样,在片17上形成的接触部分19与插头2B接触进行电连接。另一方面,它的下部的片11的贯通孔11A形成得较大。因此,孔11A不与插头2B接触,只有片17与插头2B电连接。In addition, as shown in FIG. 7, in the state where IC1 is mounted in the
又,IC1的连接用阴极插头2A通过接触部分13和片11与电容元件21的阴极取出部分23连接。另一方面,IC1的连接用阳极插头2B通过接触部分19和片17与电容元件21的阳极取出部分22连接。因为一般地片17和阳极取出部分22由金属构成,所以可以通过电或激光等的熔接、铆接和超声波熔接等进行连接。因为片11和阴极取出部分23由金属和导电性材料构成,所以可以通过导电性汁和粘合剂或压接进行连接。Also, the
(实施形态3)(Embodiment 3)
图8是表示根据本发明的实施形态3的片式电容的构成的分解立体图,图9是图8的截面图。在本实施形态中,在2个层积状态中安装实施形态2中的片式电容的电容元件,并且各个电容元件的特性是不同的。除了该构成外都与实施形态2相同。8 is an exploded perspective view showing the structure of a chip capacitor according to
与实施形态2相同,绝缘片(以下,称为片)16和导电性阳极片(以下,称为片)17与导电性阴极片(以下,称为片)11的内侧层积地接合。将电容元件21配设在设置在片16、17的中央部分重合的开口部分20内。电容元件21的阳极取出部分22与片17电连接,阴极取出部分23与片11电连接。这样一来构成层积体。为了覆盖片17而密封绝缘片(以下,称为片)24。这样一来构成第1片式电容。As in
又,在片11的下面,使绝缘片34(以下,称为片)和导电性第2阳极片(以下,称为片)35层积接合。将电容元件37配设在设置在片34、35的中央部分重合的开口部分36内。电容元件37的阳极取出部分38与片35电连接,阴极取出部分39与片11电连接。这样一来构成层积体。为了覆盖片17而密封绝缘片40。这样一来构成第2片式电容。Further, on the lower surface of the
此外,在图9中片11的接触部分13、片17的接触部分19、片35的接触部分41与插头2接触。Furthermore, the
这样在根据本实施形态的片式电容中,在一个片式电容中一体地形成种类或特性不同的多个电容元件。在IC中一般地约1/4~1/3由同一系统的电源线构成。因此根据这种构成能够统括地连接多个电容元件21、37。而且能够将使各个耐电压的电容元件21、37与一个IC1的不同电压的插头2连接。因此,能够使全体更进一步小型·薄型化。In this way, in the chip capacitor according to this embodiment, a plurality of capacitive elements having different types or characteristics are integrally formed in one chip capacitor. Generally, about 1/4 to 1/3 of ICs are constituted by power lines of the same system. Therefore, according to such a configuration, a plurality of
(实施形态4)(Embodiment 4)
图10是表示根据本发明的实施形态4的片式电容的构成的分解立体图,图11是图10的截面图。在本实施形态中,在2个层积状态中安装实施形态2中的片式电容的电容元件,并且各个电容元件的特性是不同的。除了该构成外都与实施形态2相同。10 is an exploded perspective view showing the configuration of a chip capacitor according to
在导电性阴极片(以下,称为片)11的上面,分别在它们之间通过绝缘片(以下,称为片)44、45层积导电性阳极片(以下,称为片)42、43。而且电容元件37的阳极取出部分38与片42连接,阴极取出部分39与片11电连接。进一步耐电压或特性与电容元件37不同的电容元件21的阳极取出部分22与片43连接,阴极取出部分23与片11连接。而且,为了覆盖片43而密封绝缘片46。这样一来构成片式电容。On the conductive cathode sheet (hereinafter referred to as sheet) 11, conductive anode sheets (hereinafter referred to as sheet) 42, 43 are laminated with insulating sheets (hereinafter referred to as sheet) 44, 45 respectively between them. . Furthermore, the
此外在图11中,片11的接触部分47、成为电容元件37的阳极的片42的接触部分48、成为电容元件21的阳极的片43的接触部分49与IC1的插头2接触。11,
这样根据本实施形态的片式电容,与实施形态3相同,在一个片式电容中一体地形成种类或特性不同的多个电容元件。因此与实施形态3相同,能够统括地使各个耐电压的电容元件21、37与与一个IC1的不同电压的插头2连接起来。因此,能够使全体更进一步小型·薄型化。Thus, according to the chip capacitor of the present embodiment, as in the third embodiment, a plurality of capacitive elements having different types or characteristics are integrally formed in one chip capacitor. Therefore, similarly to the third embodiment, it is possible to collectively connect the
(实施形态5)(Embodiment 5)
图12是表示根据本发明的实施形态5的片式电容的构成的分解立体图,图13是图12的截面图。在本实施形态中,安装多个在实施形态2中的片式电容的电容元件。除了该构成外都与实施形态2相同。12 is an exploded perspective view showing the configuration of a chip capacitor according to
在导电性阴极片(以下,称为片)11的上面,通过绝缘片(以下,称为片)16层积导电性阳极片(以下,称为片)17。又多个电容元件50的各阳极取出部分51分别与片17连接,各阴极取出部分52与片11连接。而且绝缘片24、15对它进行密封。这样一来构成片式电容。On the upper surface of the conductive cathode sheet (hereinafter referred to as sheet) 11 , a conductive anode sheet (hereinafter referred to as sheet) 17 is laminated via an insulating sheet (hereinafter referred to as sheet) 16 . In addition, the
此外,在图13中,成为电容元件50的阴极的片11的接触部分53、成为电容元件50的阳极的片17的接触部分54与IC1的连接用插头2接触。In addition, in FIG. 13 , the contact portion 53 of the
这样在根据本实施形态的片式电容中,具有将电容元件分割成多个的构成。因此,能够缓冲由于反转片式电容发生的加在电容元件50上的应力。即,能够抑制当将片式电容插入IC1时加入的应力和由于热膨胀引起的LC的零散。In this way, the chip capacitor according to this embodiment has a structure in which the capacitor element is divided into a plurality of parts. Therefore, the stress applied to the
(实施形态6)(Embodiment 6)
图14是表示根据本发明的实施形态6的片式电容及其使用状态的截面图。将设置在IC1上的连接插头2插入设置在印刷电路配线板4上IC插座3。在片式电容55的中央部分形成嵌入IC插座3的空洞部分内的大的凹部56,将电容元件57安装在凹部56内。Fig. 14 is a cross-sectional view showing a chip capacitor according to Embodiment 6 of the present invention and its state of use. The
这样在根据本实施形态的片式电容中,能够将高度大的电容元件57安装在片式电容55内。又当使片式电容55翻过来组入时不能够将连接用插头2插入IC插座3,又或者与其它电子部件58接触。因此,能够防止逆向地插入片式电容55。In this way, in the chip capacitor according to this embodiment, it is possible to mount the high-
(实施形态7)(Embodiment 7)
图15是表示根据本发明的实施形态7的片式电容及其使用状态的分解立体图,图16是图15的截面图。图17是表示图15的片式电容的构成的分解立体图。Fig. 15 is an exploded perspective view showing a chip capacitor according to Embodiment 7 of the present invention and its usage state, and Fig. 16 is a cross-sectional view of Fig. 15 . FIG. 17 is an exploded perspective view showing the configuration of the chip capacitor of FIG. 15 .
将连接用接合面(以下,称为接合面)59设置在IC1的下面。印刷电路配线板(以下,称为基板)4具有连接用接合面(以下,称为接合面)60。将连接用接合面(以下,称为接合面)62设置在片式电容(以下,称为电容)61的上面,与接合面59连接。同样将与接合面60连接的连接用接合面72设置在下面。用贯通孔71将接合面62、72连接成一体。图15中的涂黑部分是设置在片式电容61上面的供给电源用的接合面63(以下,称为接合面)。接合面63与接合面62同样用贯通孔在上下方向连接成一体,并且也与内装的电容元件67、68电连接。A bonding surface for connection (hereinafter referred to as bonding surface) 59 is provided on the lower surface of IC1. The printed wiring board (hereinafter, referred to as a substrate) 4 has a connection bonding surface (hereinafter, referred to as a bonding surface) 60 . A connection joint surface (hereinafter referred to as a joint surface) 62 is provided on an upper surface of a chip capacitor (hereinafter referred to as a capacitor) 61 to be connected to the
这样构成的片式电容61夹在IC1与基板4之间。根据这种构成,能够确保将电容元件安装在片式电容61中的面积。片式电容61,通过分别与接合面59、60对应地设置的接合面62,用焊料孔等的连接方法同时进行机械地固定和电连接。根据这种构成,能够用与已有相同的方法进行IC1、基板4和片式电容61的各个连接。
在图17中,第1绝缘板((以下,称为基板)64形成与IC1大致相同的形状。阳极连接部分65和阴极连接部分66分别与设置在后述的电容元件上的阳极取出部分和阴极取出部分连接。电容元件67、68各自的种类和特性是不同的。第2绝缘板(以下,称为基板)69形成与IC1大致相同的形状,并且具有其厚度比电容元件67、68的高度大的构成。将方形的切去部分70设置在基板69的中央。将接合面62和接合面63分别设置在基板64、69上。In FIG. 17, the first insulating plate (hereinafter referred to as the substrate) 64 is formed in substantially the same shape as IC1. The anode connection part 65 and the cathode connection part 66 are respectively connected to the anode extraction part and the cathode connection part provided on the capacitive element described later. The cathode extraction part is connected. The respective types and characteristics of the capacitive elements 67, 68 are different. The second insulating plate (hereinafter referred to as the substrate) 69 forms approximately the same shape as IC1, and has a thickness ratio of the capacitive elements 67, 68. A high-height configuration. The square cutout portion 70 is provided at the center of the substrate 69. The
通过这样地分割绝缘基板,在一方的切去部分中配置电容元件67、68的构成,能够使片式电容61成为更薄型。又,能够从IC1的接合面59连接电容元件67、68。因此,能够大幅度地减少由于电容元件67、68与IC1之间的配线引起的ESL的值。又,使绝缘基板64、69与IC1具有大致相同的形状,并且具有使设置在绝缘基板64、69上的连接用接合面的间隔与设置在IC1上的连接用接合面59的间隔对应的构成。因此,能够统括地使一个共同的电子部品元件(大电容量的电容和电源模块)和与形状与IC1相同的IC1的连接用接合面59连接。因此,能够使包含IC1的电路全体小型薄型化。By dividing the insulating substrate in this way and arranging the capacitive elements 67 and 68 in one cutout portion, the
又如图16所示,在电容61中,在使基板64和基板69接合成一体的状态中与接合面59的间隔对应地形成上下方向导通的贯通孔71。通过贯通孔71,在上面配设与IC1连接的接合面62,在下面配设与基板4连接的接合面72。Also as shown in FIG. 16 , in
进一步,在基板64上,并且在设置在基板69上的切去部分70的内部安装电容元件67、68。用橡胶系树脂和聚酰亚胺、聚酰胺亚胺、苯酚等的耐热树脂构成的绝缘部分73覆盖电容元件67、68。Further, capacitive elements 67 and 68 are mounted on the substrate 64 and inside a cutout portion 70 provided on the substrate 69 . Capacitance elements 67 and 68 are covered with insulating portion 73 made of rubber-based resin and heat-resistant resin such as polyimide, polyamideimide, or phenol.
此外,电容元件67是通过在形成电介质氧化表面膜层的阳极电极箔74的外表面上形成功能性高分子层,进一步在该外表面上形成阴极取出部分75构成的。用熔接和银·碳构成的导电性胶等的连接方法将阳极电极箔74与阳极连接部分65接合起来,将阴极取出部分75与阴极连接部分66接合起来,分别进行电导通。同样,电容元件68是通过在形成电介质氧化表面膜层的阳极电极箔76的外表面上形成功能性高分子层,进一步在该外表面上形成阴极取出部分77构成的。用熔接和银·碳构成的导电性胶等的连接方法将阳极电极箔76与阳极连接部分65接合起来,将阴极取出部分77与阴极连接部分66接合起来,分别进行电导通。阴极取出部分75、77是由银胶和碳构成的。In addition, the capacitive element 67 is constituted by forming a functional polymer layer on the outer surface of the anode electrode foil 74 formed with a dielectric oxide surface film layer, and further forming the cathode extraction portion 75 on the outer surface. The anode electrode foil 74 is joined to the anode connection part 65, and the cathode extraction part 75 is joined to the cathode connection part 66 by means of welding, conductive glue made of silver and carbon, etc., and are electrically connected to each other. Similarly, the capacitive element 68 is formed by forming a functional polymer layer on the outer surface of the anode electrode foil 76 formed with a dielectric oxide surface film layer, and further forming the cathode extraction portion 77 on the outer surface. The anode electrode foil 76 is joined to the anode connection part 65, and the cathode extraction part 77 is joined to the cathode connection part 66 by means of connection methods such as welding and silver-carbon conductive glue, and are electrically connected to each other. The cathode extraction parts 75, 77 are made of silver paste and carbon.
此外在图16中,绝缘层78使在电容61上形成的配线部分绝缘。焊料孔79与IC1的接合面59连接,焊料孔80与基板4的接合面60连接。通过这样地设置焊料孔79、80,在IC1与基板4之间夹入电容61进行反转,能够层积基板4、电容61和IC1使它们连接成一体。In addition, in FIG. 16 , the insulating layer 78 insulates the wiring portion formed on the
根据这种构成,能够将种类和特性不同的多个电容元件67、68与IC1的使用电压和容量一致地连接起来。又,能够不改变在基板4上形成的接合面60形状地追加电容。因此,能够不变更基板4上的图案地追加电路和强化噪声对策等。因此,能够大幅度地缩短制品开发期间。According to such a configuration, a plurality of capacitive elements 67 and 68 having different types and characteristics can be connected in accordance with the voltage and capacity used by IC1. In addition, capacitance can be added without changing the shape of the
又在本实施形态中,我们将无引线型作为例子说明了IC1,但是不限定于此。通过用扁平封装型与引线间隔一致地形成与IC连接的接合面,也能够将扁平封装型的IC与本实施形态的片式电容连接起来。Also, in this embodiment, IC1 has been described by taking the leadless type as an example, but it is not limited thereto. It is also possible to connect a flat package type IC to the chip capacitor of the present embodiment by forming the bonding surface to be connected to the IC in a flat package type so as to match the pitch of the leads.
进一步,基板64和基板69也可以用多层构造的印刷电路配线板。Furthermore, printed wiring boards with a multilayer structure may be used for the substrate 64 and the substrate 69 .
(实施形态8)(Embodiment 8)
图18是表示根据本发明的实施形态8的片式电容的构成的截面图。IC81具有连接用的引线82。为了使绝缘基板(以下,称为基板)83上下贯通而设置贯通孔84。将与IC81的引线82连接的连接用接合面(以下,称为接合面)85设置在基板83的上面。接合面86与设置在基板83的下面的印刷电路配线板(以下,称为基板)4的连接用接合面60连接。配线部分88连接接合面85、60和芯片式电容87。焊料孔89用于连接接合面86和接合面60。将芯片式电容87配置在IC81的外周部。这样一来能够构成片式电容(以下,称为电容)90。Fig. 18 is a cross-sectional view showing the structure of a chip capacitor according to Embodiment 8 of the present invention. The IC 81 has lead wires 82 for connection. A through hole 84 is provided to vertically penetrate an insulating substrate (hereinafter referred to as substrate) 83 . On the upper surface of the substrate 83 , a connection bonding surface (hereinafter referred to as bonding surface) 85 to be connected to the lead wire 82 of the IC 81 is provided. The bonding surface 86 is connected to the
在这种构成中,通过使设置在电容90的上面的接合面85与IC81的引线82连接,又使设置在电容90的下面的接合面86与基板4的接合面60连接,实现导通。因此,能够将片式电容90夹入IC81与基板4之间。从而,能够确保将电容元件安装在片式电容90中的面积。进一步能够1块地构成绝缘基板所以也使成本降低。In this configuration, conduction is achieved by connecting the bonding surface 85 provided on the upper surface of the capacitor 90 to the lead 82 of the IC 81 and connecting the bonding surface 86 provided on the lower surface of the capacitor 90 to the
(实施形态9)(Embodiment 9)
图19是表示根据本发明的实施形态9的片式电容的构成的截面图,图20是图19的分解立体图。将电容元件92安装在片式电容的本体部分91内。电容元件92是通过在表面上形成电介质氧化表面膜的阳极电极箔93上层积形成导电性高分子层94和由碳和银胶等构成的阴极层95构成的。Fig. 19 is a cross-sectional view showing the structure of a chip capacitor according to
又,阳极电极箔93,通过与导电性阳极片(以下,称为片)96连接,经过接触部分97与IC1的连接用插头2连接。进一步,阴极层95,通过与阴极片(以下,称为片)98连接,经过接触部分99与其它的IC的连接用插头(以下,称为插头)2连接。片96、98分别兼作阳极取出用配线、阴极取出用配线,由SUS和弹簧用磷青铜等构成。通过用绝缘体的盖片100密闭这样构成的电容元件92,构成根据本实施形态的片式电容的本体部分91。Also, the anode electrode foil 93 is connected to the conductive anode sheet (hereinafter referred to as sheet) 96 and connected to the
使滑板101形成上面开放的箱形。将引导器102互相相对地设置在滑板101的上端。将引导器102载置在本体部分91的上面端部,将滑板101安装在本体部分91中。因此,能够相对本体部分91沿图19中的左右方向自由滑动地保持滑板101。The
在该状态中将弹簧104压缩地插入滑板101内的,在与本体部分91之间形成的弹簧收藏部分103中。因此,滑板101沿图中的右侧方向移动,本体部分91沿左侧方向移动。由于这种力使设置在滑板101中的贯通孔105和接触部分97、99夹入插头2。在该构成中在压缩弹簧的104的状态中比贯通孔2大地形成的贯通孔105向左侧方向移动。因此,能够极其容易地插入拔出本体部分91进行替换。In this state, the
此外,增强部分106支持弹簧104。为了使电容元件92的阴极层95上下贯通而设置贯通孔107。弹簧104是在本体部分91和/或滑板101上加力的加力部分,也可以由弹簧以外的橡胶等的弹性体构成。Furthermore, the reinforcement portion 106 supports the
为了夹入IC1与基板4之间而配设这样构成的本体部分91。而且通过使IC1的插头2贯通本体部分91的贯通孔108,安装在IC插座3中,经过接触部分109导通IC1和本体部分91。用这样简单的构成,能够得到薄型的片式电容。根据这种构成,在使滑板101的贯通孔105和本体部分91的贯通孔108一致的状态中,能够容易地将插头2插入拔出贯通孔。又,在使用状态,因为弹性沿将插头2夹入滑板101的孔105和接触部分109中的方向起作用,所以能够锁定插头2并且能够确实地电连接接触部分109和插头2。又因为接触部分109具有弹性,所以即便当在插头2中存在间隔偏离时,接触部分109的弹性也能够吸收该间隔偏离。The
(实施形态10)(Embodiment 10)
图21A、B是表示根据本发明的实施形态10的片式电容的接触部分的构成的图。除此以外的构成与实施形态9相同。21A and B are diagrams showing the configuration of a contact portion of a chip capacitor according to Embodiment 10 of the present invention. Other configurations are the same as those of the ninth embodiment.
比插头2大地形成插入IC1的连接用插头(以下,称为插头)2的贯通孔108。将贯通孔(以下,称为孔)105设置在滑板101中。在具有弹性的导电性片96、98中形成具有直线部分的半圆状的贯通孔110。与贯通孔110邻接地形成缝隙111。在贯通孔110与缝隙111之间形成具有弹性的接触部分112。A through-
接触部分112,如图21B所示,当插入IC1的插头2使滑板101在图中的箭头方向移动时孔105也在同一方向中移动。因此,夹住插头2具有弹性的接触部分112向滑板111一侧弯曲地形变。由于该形变即便当在插头2中存在间隔偏离时,通过具有弹性的接触部分112也能够确实地使插头2与接触部分112接触。又在图21A的状态中,因为滑板101的孔105不与插头2接触,所以能够容易地插入拔出插头2。The contact portion 112, as shown in FIG. 21B, the
图22A、22B是表示接触部分的其它例子的平面图,图22C、22D分别是图22A,图22B的截面图。在具有弹性的导电性片(以下,称为片)114中形成贯通孔(以下,称为孔)113,在内部具有突起。通过在孔113内插入插头2使上述突起弯折,构成具有弹性的接触部分115。在对极一侧的导电性片116中,为了不与插头2导通形成大的开口部分117。绝缘片118保持一对导电性片114、116之间的绝缘。盖片119覆盖片114。22A and 22B are plan views showing other examples of contact portions, and FIGS. 22C and 22D are cross-sectional views of FIGS. 22A and 22B, respectively. A through-hole (hereinafter, referred to as a hole) 113 is formed in an elastic conductive sheet (hereinafter, referred to as a sheet) 114 and has a protrusion inside. By inserting the
这样构成的接触部分115,如图22B、22D所示,当插入插头2使滑板101在图中的箭头方向移动时孔105也在同一方向中移动。因此,夹住插头2具有弹性的接触部分115向外侧弯曲地形变。由于该形变即便当在插头2中存在间隔偏离时,因为接触部分115具有弹性所以也能够确实地使插头2与接触部分115接触。又,在图22A、22C的状态中,因为滑板101的孔105不与插头2接触,所以能够容易地插入拔出插头2。With the contact portion 115 thus constituted, as shown in FIGS. 22B and 22D, when the
(实施形态11)(Embodiment 11)
图23是表示根据本发明的实施形态11的片式电容的构成的分解立体图。图24是表示使IC与图23的片式电容连接的状态的截面图。图25A、25B是表示图23的接触部分的平面图。Fig. 23 is an exploded perspective view showing the structure of a chip capacitor according to
在导电性的阳极片(以下,称为片)120中设置IC1的连接用插头(以下,称为插头)2贯通的贯通孔(以下,称为孔)121。在孔121中,只在需要与IC1连接的插头2贯通的孔121中,形成与插头2导通的接触部分122(图中的涂黑部分)。又在中央部分设置开口部分123。A through-hole (hereinafter, referred to as a hole) 121 through which a connection pin (hereinafter, referred to as a pin) 2 of the
在第1阴极片(以下,称为片)124中设置插头2贯通的贯通孔(以下,称为孔)125。在孔125中,只在需要与IC1连接的插头2贯通的孔125中,形成与插头2导通的接触部分126(图中的涂黑部分)。进一步在周边(端面)上设置弯折成大致L字形的弯折部分127进行增强。A through-hole (hereinafter, referred to as a hole) 125 through which the
在第2阴极片(以下,称为片)128中设置插头2贯通的贯通孔(以下,称为孔)129。在孔129中,只在需要与IC1连接的插头2贯通的孔129中,形成与插头2导通的接触部分130(图中的涂黑部分)。进一步在周边(端面)上设置弯折成大致L字形的弯折部分131,进行增强。A through-hole (hereinafter, referred to as a hole) 129 through which the
在绝缘片(以下,称为片)132、133中,分别设置插头2贯通的贯通孔134,在中央部分分别设置开口部分135A、135B。在绝缘片(以下,称为片)136、137中,分别设置插头2贯通的贯通孔138。片状的电容元件139具有阳极取出部分140和阴极取出部分141。Insulating sheets (hereinafter, referred to as sheets) 132 and 133 are respectively provided with through-holes 134 through which the
在根据这样构成的本实施形态的片式电容中,在片120的表里面上分别配设片132、133的状态中片124和片128夹入它。而且在分别设置在片120和片132、133的中央部分重合的开口部分123、135A、135B内配设电容元件139。进一步通过导电体142,分别使电容元件139的阳极取出部分140与片120电连接,使阴极取出部分141与片124、128电连接。又,片136覆盖片124,片137覆盖片128。In the chip capacitor according to the present embodiment thus constituted, the
在图24中,接触部分143与插头2和片120连接。接触部分144与插头2和片124、128连接。贯通孔145不与插头2导通。熔接部分146与片124的弯折部分127和片128的弯折部分131电导通,根据这种构成对片120进行屏蔽。这样一来,能够构成根据本实施形态的片式电容。In FIG. 24 , the contact portion 143 is connected with the
此外,片120、124、128最好由弹簧用磷青铜和SUS·镍银合金·铍铜等的导电性的具有弹性的材料构成。它的厚度如果为0.05~0.25mm则插入拔出性很好。又,对于片132、133、136、137,能够利用作为廉价的通用树脂的PET、聚酰胺(PA)、PC和具有耐热性的硫化聚苯(PPS)、PI、聚醚醚酮(PEEK)。或者,也可以是保持片形状的陶瓷和玻璃等的硬基板、丙烯、硅和密胺系的绝缘涂料。此外,基板厚度为0.03~0.2mm容易处理,电极间的绝缘片的厚度越薄ESL越低。又,用绝缘涂料时的厚度最好为5~20μm,片或绝缘涂料的分开使用由制造方法和成本等任意地决定。In addition, the
在根据这样构成的本实施形态的片式电容中,流过电容元件139的电流如图24中的实线所示被二分为第1电流环路147和第2电流环路148地进行流动。在成为图中下面一侧的第1电流环路147中,电流以阳极取出部分140→片120的接触部分122→插头2→IC1→插头2→片124的接触部分126→阴极取出部分141的顺序流动。在成为图中上面一侧的第2电流环路148中,电流以阳极取出部分140→片120的接触部分122→插头2→IC1→插头2→片128的接触部分130→阴极取出部分141的顺序流动。In the chip capacitor according to the present embodiment configured in this way, the current flowing through the
从而,这样通过二分为上面一侧和下面一侧进行流动的电流环路147、148,电流二分为上面一侧和下面一侧回到电容元件139。而且在上面一侧和下面一侧中电流环路方向相反,相互抵消了产生的磁场。因此,使ESL成分变小,使到插头2的ESL极小。Therefore, through the current loops 147 and 148 that flow through the upper side and the lower side in this way, the current is divided into the upper side and the lower side and returned to the
此外在上述构成中,上面一侧的电流环路147和下面一侧的电流环路148的面积相等,能够抑制磁场的发生使ESL变小。又,通过熔接部分146使片124和片128在各自的端面上导通,覆盖片120。因此使ESR和ESL变得极小。In addition, in the above configuration, the upper current loop 147 and the lower current loop 148 have the same area, so that the generation of a magnetic field can be suppressed and the ESL can be reduced. Further, the
此外,也可以在片124和片128中,只在一方设置接触部分,通过熔接部分146使片124和片128在端面上电连接而进行构成。在这种构成中,因为在阴极片中形成的接触部分只是单方面所以容易插入拔出插头2。Alternatively, a contact portion may be provided on only one of the
又,在本实施形态中,除去片124、128的孔125、129和接触部分126、130的部分被由片132、133或绝缘涂装构成的绝缘层覆盖。因为根据这种构成,不能够用手直接接触阴极接合面,所以能够防止安装时由于静电对IC1的破坏等的麻烦。In addition, in this embodiment, the portions excluding the
图25A、25B分别表示与插头2非接触的贯通孔和与插头2接触的接触部分。在图25A中,形成片120、124、128的非接触的贯通孔比插头2的外径大。此外,为了绝缘片的贯通孔150保持插头2与片120、124、128的绝缘性,使它形成得比贯通孔149小。25A and 25B show a through-hole not in contact with the
又在图25B中,设置在片120、124、128上与插头2接触的接触部分151形成短轴比插头2的外径小长轴比插头2的外径大的椭圆形状。这样通过图25A、25B的组合,能够使插头2与片120、124、128任意地接触。Also in FIG. 25B , the
(实施形态12)(Embodiment 12)
图26是表示根据本发明的实施形态12的片式电容的构成的分解立体图,图27是图26的截面图,图28是表示使IC与图26的片式电容连接的状态的截面图。26 is an exploded perspective view showing the structure of a chip capacitor according to
阴极片(以下,称为片)152由在弹簧用磷青铜上镀金的导电体构成。在片152上形成与IC1的连接用插头(以下,称为插头)2的间隔一致的贯通孔153和与IC1的连接用阴极插头(以下,称为插头)2B连接的接触部分154B。阴极电极箔(以下,称为电极箔)155通过用超声波熔接和冷冲压等方法形成的连接部分156A,与片152的大致中央部分电连接并且机械地进行接合。The cathode sheet (hereinafter, referred to as sheet) 152 is composed of a conductive body in which phosphor bronze for springs is plated with gold. Formed in the
阳极片(以下,称为片)157由在弹簧用磷青铜上镀金的导电体构成。在片157上形成与IC1的插头2的间隔一致的贯通孔153和与IC1的连接用阳极插头(以下,称为插头)2A连接的接触部分154A。阳极电极箔(以下,称为电极箔)158通过用超声波熔接和冷冲压等方法形成的连接部分156B,与片157的大致中央部分电连接并且机械地进行接合。电极箔115、158分别作为阴极电极部分、阳极电极部分起作用。The anode piece (hereinafter, referred to as a piece) 157 is composed of a conductor made of phosphor bronze for springs plated with gold. On the
将分隔器159浸含在图中没有画出的凝胶状的电解液中,配设在片152和片157之间。即,电极箔115和电极箔158夹住分隔器159地相对地设置。此外,当通过用凝胶状的电解液,密封电极构成部分时,因为不流出电解液,所以能够防止发生密封不合适的情形。
在中央部分中设置开口部分的密封片160由聚乙烯、PET、环氧树脂、密胺、硅树脂等的具有绝缘性的材料构成。将密封片160配设在片152和157之间通过粘合或热熔接将它们接合成一体,并且密封夹住分隔器159的电极箔155、158。在绝缘片161、162中设置与插头2的间隔一致的贯通孔153,分别贴附在片152和片157的外表面一侧。此外,也可以代替片161、162,在片152、157的外表面上施加绝缘涂敷。The sealing
这样一来,能够构成本实施形态的片式电容(以下,称为电容)163。根据这种构成,从片152、157分别直接向电极箔155、158供电。因此,能够使ESR减少。又,因为密封了由片157和片152构成的电导通路径所以也能够使ESL减少。进一步在构造上,使电容163全体的厚度变薄。In this manner, the chip capacitor (hereinafter, referred to as capacitor) 163 of this embodiment can be configured. According to such a configuration, electric power is directly supplied from the
此外,最好使由电极箔158、分隔器159和电极箔155构成的电极构成部分减压到大气压以下进行密封。如果这样做,则因为各电极通过分隔器159粘合起来所以电极间隔稳定,使特性的变化变小。In addition, it is preferable to depressurize and seal the electrode constituent part composed of the
在这样构成的本实施形态的电容163中,设置IC1的插头2贯通的贯通孔153。又,只在需要与IC1连接的插头2贯通的贯通孔153中,形成与插头2导通的接触部分154A、154B(图中的涂黑部分)。通过使IC1的插头2贯通电容163的贯通孔153并安装在IC插座3中,经过接触部分154A、154B使IC1与电容163导通。根据这种构成,能够在IC1与IC插座3之间夹入电容163。因此,不需要用为了将电容163安装在印刷电路基板上的空间。此外,当IC1为CPU时,一般地约1/4~1/3由同一系统的电源线构成。如果根据本构成则能够统括地连接多个电源用插头。In the
此外,图28中插头2不与贯通孔153A连接。通过接触部分154A插头2A与贯通孔153B连接。通过接触部分154B插头2B与贯通孔153C连接。In addition, in FIG. 28, the
又,片152、157由实施了镀金的具有弹性的导电性金属构成。因此,能够防止由于电解液对片152、157的腐蚀。而且,对于接触部分154A、154B可以使用具有弹性的弹簧材料,能够很大地提高当进行到IC的插入拔出时的可靠性。也可以代替镀金,对片152、157的电极箔155、158以外的,与电解液接合的部分实施绝缘涂敷。此外,通过绝缘涂敷或用绝缘片覆盖片152、157的外表面,能够防止由于与安装在同一印刷电路配线板上的其它电子部件接触引起的漏电。Also, the
图29表示接触部分154A的构成,图中左侧表示插头2A插入前的状态,图中右侧表示插头2A插入后的状态。将椭圆形的贯通孔164设置在与IC1的插头2A连接的接触部分154A中,贯通孔164形成长轴方向比插头2A的直径大,短轴方向比插头2A的直径小的尺寸。因为在该形状中没有边缘部分,所以能够减轻到接触部分154A的应力,难以在接触部分154A中引入龟裂。将贯通孔165设置在密封片160上,以比片152的贯通孔166小的直径进行构成。因此,能够确保绝缘性。将贯通孔167设置在绝缘片162上,为了即便发生粘贴偏离影响也很小,形成得稍微大一些。Fig. 29 shows the structure of the
图30表示多层层积根据本实施形态的片式电容的电极箔时的构成。在该构成中,交替地层积阴极电极箔(以下,称为电极箔)168、分隔器169和阳极电极箔(以下,称为电极箔)170,使各电极箔168,各电极箔170分别电连接。用超声波熔接等方法使电极箔168与片152连接。加长位于电极箔170的最外端的电极的一部分,使形成的接合部分171与片157连接。也可以接合部分171形成在电极箔168的最外端,与片152连接。根据这种构成,能够容易地增加电容的电容量。FIG. 30 shows a structure in which electrode foils of the chip capacitor according to this embodiment are laminated in multiple layers. In this configuration, cathode electrode foils (hereinafter, referred to as electrode foils) 168, separators 169, and anode electrode foils (hereinafter, referred to as electrode foils) 170 are alternately laminated so that each electrode foil 168 and each electrode foil 170 are electrically connected to each other. connect. The electrode foil 168 is connected to the
此外,根据这种构成,设置在电极箔170中的接合部分171在打开片157的状态中用超声波熔接等方法与片157和电极箔170电连接。又通过使接合部分171弯折能够关闭片157和片152。Further, according to this configuration, the joint portion 171 provided in the electrode foil 170 is electrically connected to the
(实施形态13)(Embodiment 13)
图31是表示根据本发明的实施形态13的片式电容的构成的截面图。在本实施形态中,在根据实施形态12的片式电容的阳极/阴极片的一部分上分别形成阳极/阴极电极部分。又,阴极片和阳极片由铝构成。Fig. 31 is a cross-sectional view showing the structure of a chip capacitor according to
阴极电极部分(以下,称为电极部分)173是通过对阴极片(以下,称为片)172的单面的一部分进行刻蚀扩大表面积形成的。阳极电极部分(以下,称为电极部分)175是通过对阳极片(以下,称为片)174的单面的一部分进行刻蚀扩大表面积并且进行形成处理形成的。分隔器176浸含在驱动用电解液中配设在电极部分173和电极部分175之间。电极部分173和电极部分175夹住分隔器176地相对地设置。在设置电极部分173和电极部分175的片172、174的面的,除去电极部分173和电极部分175的部分中层叠由高分子材料构成的密封片177。绝缘片178、179使外包装绝缘。The cathode electrode part (hereinafter referred to as electrode part) 173 is formed by etching a part of one side of cathode sheet (hereinafter referred to as sheet) 172 to enlarge the surface area. The anode electrode portion (hereinafter, referred to as an electrode portion) 175 is formed by etching a part of one side of the anode sheet (hereinafter, referred to as a sheet) 174 to enlarge the surface area and performing a forming process.
如下制作这样构成的本实施形态的片式电容。首先,在由铝构成的片172和片174的各自的一个面上,使形成电极部分173和电极部分175的部分开口,层叠由高分子材料构成的密封片177。在另一个面上分别层叠绝缘片178、179。而且,将片172和片174浸渍在图中未画出的刻蚀槽中进行刻蚀。这样一来形成电极部分173、175。进一步,将在片174上形成的电极部分175浸渍在图中未画出的形成槽中形成电极部分175。此后,通过冲压加工形成贯通孔和接触部分,制作片172和片174。The chip capacitor of the present embodiment having such a configuration is fabricated as follows. First, a sealing
接着,使电极部分173和电极部分175相对地设置地配置片172和片174,在它们之间夹入分隔器176。此后,通过用热压等方法加热分隔器176周边,热熔接密封片177并进行密封。这样一来能够制作片式电容。Next, the
根据这种构成,在由铝构成的片172、174的一部分上一体地形成电极部分173、175。因此,不需要片172、174和电极部分173、175的各个连接并且消除了连接电阻。结果,能够得到ESR低,部件数目少的片式电容。According to this configuration, the
(实施形态14)(Embodiment 14)
图32是表示根据本发明的实施形态14的片式电容的构成的截面图。阴极电极箔(以下,称为电极箔)181与由导电体构成的阴极片(以下,称为片)180的单面接合。阳极电极箔(以下,称为电极箔)183与由导电体构成的阳极片(以下,称为片)182的单面接合。电极箔181、183分别作为阴极电极部分、阳极电极部分起作用。使电极箔181和电极箔183相对地设置地进行配设,在它们之间放入混入驱动用电解液184中的大致球状的垫片185。垫片185的直径例如为5~20μm。Fig. 32 is a cross-sectional view showing the structure of a chip capacitor according to
这样通过用混入垫片185的电解液184,能够一面保持电极箔间的绝缘性,一面增加每单位面积的电极箔间的电解液量。这是因为这种构成的密度比片状的分隔器小。又,根据垫片185的直径能够使电极间隔保持在从数μm到数十μm的任意薄的间隔中。进一步,能够根据垫片185的直径任意地设定用分隔器难以处理的数μm的电极箔间的距离。因此,能够使电解液184的层变薄。从而减小ESR。By using the
密封片186对电极箔181和电极箔183以及混入了垫片185的驱动用电解液184进行密封。阴极连接器(以下,称为连接器)187、阳极连接器(以下,称为连接器)189由具有弹性的导电体形成。设置在连接器187中的IC1的连接用阴极插头2B与接触部分188连接。设置在连接器189中的IC1的连接用阳极插头2A与接触部分190连接。连接部分191分别将片180和连接器187、阳极片182和连接器189电连接起来。Sealing
根据这样的构成,因为接触部分187、189通常不与电解液接触,所以对于接触部分187、189可以使用具有弹性的弹簧材料。因此能够很大地提高当进行到IC1的插入拔出时的可靠性。此外,为了防止电解液引起的腐蚀,所以最好在片180、183的电极箔181、183以外在与电解液接触的部分和连接器187、188上镀金或施加绝缘涂敷。According to such a configuration, since the
(实施形态15)(Embodiment 15)
图33是表示根据本发明的实施形态15的片式电容的构成的截面图。在由导电体构成的阴极片(以下,称为片)192中设置凹部193。阴极电极箔(以下,称为电极箔)194与凹部193内的片192接合。在由导电体构成的阳极片(以下,称为片)195中设置凹部196。阳极电极箔197与凹部196内的阳极片195接合。使电极箔194与电极箔197相对地设置地进行配设,在它们之间放入浸含在驱动用电解液中的分隔器198。密封片199将电极箔194和电极箔197以及分隔器198一起密封起来。除此以外的构成与实施形态12相同。Fig. 33 is a cross-sectional view showing the structure of a chip capacitor according to
根据这样的构成,即便当层积电极箔194、197、分隔器198使它们变厚时也能够毫不勉强地收容它们。又,能够在电极箔194、197、分隔器198的密封工序中防止驱动用电解液流出。又当水平地使用时不用担心液体的泄漏。进一步,能够防止相反方向地插入片式电容。According to such a configuration, even when the electrode foils 194 , 197 and the
(实施形态16)(Embodiment 16)
图34是表示根据本发明的实施形态16的片式电容的构成的分解立体图,图35是图34的截面图,图36是表示使IC与图34的片式电容连接的状态的截面图。34 is an exploded perspective view showing the configuration of a chip capacitor according to
在阴极电极箔(以下,称为电极箔)200中形成与IC1的连接用插头(以下,称为插头)2的间隔一致的贯通孔201、和与IC1的连接用阴极插头(以下,称为插头)2B连接的接触部分202B。在绝缘片203中设置与插头2的间隔一致的贯通孔201。通过在电极箔200的单面上层叠绝缘片203构成阴极片。In the cathode electrode foil (hereinafter, referred to as electrode foil) 200, through-
在阳极电极箔(以下,称为电极箔)204中形成与插头2的间隔一致的贯通孔201、和与IC1的连接用阳极插头(以下,称为插头)2A连接的接触部分202A。在绝缘片205中设置与插头2的间隔一致的贯通孔201。通过在电极箔204的单面上层叠绝缘片205构成阳极片。电极箔200、204分别作为阴极电极部分、阳极电极部分起作用。Anode electrode foil (hereinafter referred to as electrode foil) 204 has through-
使分隔器206浸含在图中未画出的驱动用电解液中,配设在电极箔200与电极箔204之间。这样一来使电极箔200与电极箔204夹住分隔器206地相对设置。在中央部分设置了分隔器206嵌入的开口部分的密封片207由聚乙烯、PET、环氧树脂、密胺、硅树脂等的具有绝缘性的材料构成。也在密封片207中设置与插头2的间隔一致的贯通孔201。密封片207,用配设在电极箔200与电极箔204之间进行粘合等的方法使它们接合成一体并且密封分隔器206。这样一来能够构成本实施形态的片式电容(以下,称为电容)208。
根据这样的构成,连接IC1的插头2A、2B的接触部分202A、202B分别与电极箔204、200形成一体。又因为电极箔204、200和接触部分202A、202B分别由平面构成所以使ESR变小。又因为电极箔200、204相互接近地配置所以也使ESL变小。又,因为电容208能够在插头2的根部进行连接,所以也没有由配线图案引起的ESR和ESL的影响,进一步,能够减少部件数目,使组装变得简单。According to such a structure, contact
此外,最好使介入电极箔200与电极箔204之间的分隔器206减压到大气压以下进行密封。如果这样做,则因为电极箔200、200通过分隔器206进行粘合所以能够使电极间隔稳定,使特性的变化减小。In addition, it is preferable to depressurize the
在这样构成的电容208上设置插头2贯通的贯通孔201。又在贯通孔201中,只在需要与IC1连接的插头2贯通的贯通孔201中,形成与插头2导通的接触部分202A、202B(图中的涂黑部分)。通过使IC1的插头2贯通电容208的贯通孔201地安装在IC插座3中,经过接触部分202A、202B使IC1和电容208导通。A through-
此外在图36中,插头2不与贯通孔201A连接。插头2A通过接触部分202A与贯通孔201B连接。插头2B通过接触部分202B与贯通孔201C连接。In addition, in FIG. 36 , the
图37表示阳极片的接触部分的构成,图中左侧表示插头2A插入前的状态,图中右侧表示插头2A插入后的状态。在与设置在电极箔204中的插头2A导通的接触部分202A中形成大致十字状的缝隙208。缝隙208也可以大致Y字地构成。缝隙208具有用设置比插头2A的直径稍微大一些的开口部分209的具有弹性的绝缘片205覆盖缝隙的构成。Fig. 37 shows the structure of the contact portion of the anode piece, the left side of the figure shows the state before the
根据这样的构成,为了按压扩大在接触部分202A中形成的缝隙208而插入插头2A。这时为了不使接触部分202A扩大而由具有弹性的绝缘片205施加从接触部分202A的周边向着开口部分209的中心压缩的力。因此即便由没有弹性的材料构成电极箔204也能够将适当的接触压力给予插头2A,提高了插头2A与接触部分202A的接触稳定性。此外,也能够同样地构成接触部分202B。According to such a configuration, the
图38表示多层层积根据本实施形态的片式电容的电极箔时的构成。第1阴极电极箔(以下,称为电极箔)210和第1阳极电极箔(以下,称为电极箔)211形成大致相同的大小。第2阴极电极箔(以下,称为电极箔)212、第2阳极电极箔(以下,称为电极箔)213和分隔器214具有大致相同的大小,并且比电极箔210、211小地形成。FIG. 38 shows a structure in which electrode foils of the chip capacitor according to this embodiment are laminated in multiple layers. The first cathode electrode foil (hereinafter referred to as electrode foil) 210 and the first anode electrode foil (hereinafter referred to as electrode foil) 211 are formed to have approximately the same size. Second cathode electrode foil (hereinafter referred to as electrode foil) 212 , second anode electrode foil (hereinafter referred to as electrode foil) 213 , and separator 214 have approximately the same size and are formed smaller than electrode foils 210 and 211 .
在这样形成的电极箔210、211之间,在各个电极箔213、212之间放入分隔器214交替地层积电极箔213、212。用压接等的方法分别使电极箔210、212、电极箔213、211电连接。此后,用图中未画出的密封片密封分隔器214的周边。这样一来能够组装片式电容。根据这种构成能够容易地增大电容量。Between the electrode foils 210 and 211 thus formed, the electrode foils 213 and 212 are alternately laminated with a separator 214 interposed between the respective electrode foils 213 and 212 . The electrode foils 210, 212, and the electrode foils 213, 211 are electrically connected, respectively, by means of crimping or the like. Thereafter, the periphery of the separator 214 is sealed with a sealing sheet not shown in the figure. In this way, chip capacitors can be assembled. According to this configuration, the capacitance can be easily increased.
(实施形态17)(Embodiment 17)
图39是表示根据本发明的实施形态17的片式电容的构成的截面图。在阴极电极箔(以下,称为电极箔)215的单面上层叠绝缘片216。绝缘片216形成比电极箔215小的尺寸,或者通过在周边一部分上设置切去部分露出电极箔215的至少周边的一部分。电极箔215的露出部分构成阴极连接端子部分(以下,称为端子部分)217。这样一来形成阴极片。在阳极电极箔(以下,称为电极箔)218的单面上层叠绝缘片219。与上述阴极片同样地形成绝缘片219,电极箔218露出部分构成阳极连接端子部分(以下,称为端子部分)220。这样一来形成阳极片。电极箔215、218分别作为阴极电极部分、阳极电极部分起作用。Fig. 39 is a cross-sectional view showing the structure of a chip capacitor according to
使电极箔215与电极箔218相对地设置来在它们之间夹入分隔器221。将分隔器221浸含在图中未画出的驱动用电解液中。在夹入阴极电极箔215与阳极电极箔218之间的密封片222中,设置与分隔器221嵌入的开口部分和图36所示的IC1的连接用插头(以下,称为插头)2的间隔一致的贯通孔201。密封片222密封分隔器221并且接合电极箔215和电极箔218,因此形成电极部分。The electrode foil 215 and the electrode foil 218 are arranged to face each other with the separator 221 interposed therebetween. The separator 221 is soaked in an unillustrated driving electrolyte. In the sealing sheet 222 sandwiched between the cathode electrode foil 215 and the anode electrode foil 218, a gap is provided between the opening part into which the separator 221 is fitted and the IC1 connection plug (hereinafter referred to as plug) 2 shown in FIG. 36 . Consistent through
在阴极连接器(以下,称为连接器)223中设置连接与插头2的间隔一致的贯通孔224和IC1的连接用阴极插头2B的接触部分225。用熔合或熔接等的方法使连接器223与设置在上述阴极片中的端子部分217连接。在阳极连接器(以下,称为连接器)226中设置连接与插头2的间隔一致的贯通孔227和IC1的连接用阳极插头2A的接触部分228。用熔合或熔接等的方法使连接器226与设置在上述阳极片中的端子部分220连接。因此,能够构成使电极部分与接触部分分离的根据本实施形态的片式电容。A cathode connector (hereinafter, referred to as a connector) 223 is provided with a contact portion 225 that connects the through hole 224 at the same interval as the
根据这样的构成,可以用具有弹性的弹簧材料构成与插头2B、2A连接的各个接触部分225、228。因此能够很大地提高到IC1的插入拔出的可靠性。又,因为片状的电极箔215、218自身成为端子部分217、220,所以能够减少ESR。又因为电极箔215、218相互近距离地邻接所以也能够减少ESL。又在构造上能够使片式电容全体的厚度变薄。According to such a configuration, the respective contact portions 225, 228 connected to the
(实施形态18)(Embodiment 18)
图40是表示根据本发明的实施形态18的片式电容的构成的截面图。阴极盖(以下,称为盖)230和阳极盖(以下,称为盖)235由具有导电性的弹性金属构成。在盖230中设置与图36所示的IC1的连接用插头(以下,称为插头)2的间隔一致的贯通孔231和与IC1的连接用阴极插头2B连接的接触部分232。在盖230的单面的中央部分,用熔合、熔接和压接等的方法通过连接部分230与阴极电极箔(以下,称为电极箔)229电连接。在盖235中,设置与插头2的间隔一致的贯通孔236和与IC1的连接用阳极插头2A连接的接触部分237。在盖235的单面的中央部分,用熔合、熔接和压接等的方法通过连接部分238与阳极电极箔(以下,称为电极箔)234电连接。电极箔229、234分别作为阴极电极部分、阳极电极部分起作用。Fig. 40 is a cross-sectional view showing the structure of a chip capacitor according to
比电极箔229和电极箔234小地形成分隔器239,将分隔器239浸含在图中未画出的驱动用电解液中。使电极箔229与电极箔234相对地设置,夹入它们之间地配设分隔器239。在密封片240中设置分隔器239嵌入的开口部分和与插头2的间隔一致的贯通孔201。将密封片240配设在电极箔229与电极箔234之间,盖230和与盖235之间,密封分隔器239,并且使电极箔229、234,盖230、235接合成一体。这样一来能够构成本实施形态的片式电解电容。The separator 239 is formed smaller than the electrode foil 229 and the electrode foil 234, and the separator 239 is immersed in an unillustrated driving electrolyte. The electrode foil 229 and the electrode foil 234 are arranged to face each other, and the separator 239 is disposed between them. In the seal sheet 240 , an opening portion into which the spacer 239 is fitted and a through-
根据这样的构成,用电极箔229、234和密封片240密封浸含在驱动用电解液中的分隔器239。根据这种构成,盖230、235不会受到由于驱动用电解液引起的化学反应的影响。因此,对于构成盖230、235的材料,可以优先选定具有弹性适用于接触部分232、237,并且具有引导电极部分的物理特性的材料。例如,能够使用SUS·弹簧用磷青铜·弹簧用镍银合金箔等。因此,能够提高与插头2的插入拔下有关的可靠性和片形电极外的强度。又,能够确实地实现接触部分232、237与插头2的接触,使ESR减小。又因为电极箔229、234相互近距离地邻接所以也能够减少ESL。According to such a configuration, the separator 239 immersed in the driving electrolytic solution is sealed with the electrode foils 229 and 234 and the sealing sheet 240 . According to this configuration, the covers 230 and 235 are not affected by the chemical reaction caused by the electrolytic solution for driving. Therefore, as for the material constituting the cover 230, 235, a material having elasticity suitable for the contact portion 232, 237 and having a physical property of leading the electrode portion can be preferably selected. For example, SUS, phosphor bronze for springs, nickel-silver alloy foil for springs, etc. can be used. Therefore, reliability related to insertion and removal of the
此外,片状的高分子材料适用于作为构成的密封片240的材料。特别是,希望热熔融PET和聚乙烯(PE),由硅、环氧树脂和密胺系的树脂硬化和粘合片(包含附加芯材)进行构成。In addition, a sheet-shaped polymer material is suitably used as a material of the sealing sheet 240 constituting it. In particular, hot-melt PET and polyethylene (PE), hardened and adhesive sheets (including additional core materials) made of silicon, epoxy and melamine-based resins are desired.
(实施形态19)(Embodiment 19)
图41是表示根据本发明的实施形态19的片式电容的构成的截面图。在阴极电极箔(以下,称为电极箔)200中设置与IC1的连接用插头(以下,称为插头)2的间隔一致的贯通孔201和与IC1的连接用阴极插头2B连接的接触部分202B。在绝缘片203中设置与插头2的间隔一致的贯通孔201、层叠在电极箔200的单面上。这样一来构成阴极片。在阳极电极箔(以下,称为电极箔)204中设置与插头2的间隔一致的贯通孔201和与IC1的连接用阳极插头2A连接的接触部分202A。在根据本实施形态的片式电容中,使2块上述阴极片的阴极电极箔200相对地设置在它们之间夹入阳极电极箔204。电极箔200、204分别作为阳极电极部分、阴极电极部分起作用。Fig. 41 is a cross-sectional view showing the structure of a chip capacitor according to
大致球形的绝缘垫片241的直径为5~20μm,在驱动用电解液242中混入绝缘垫片(以下,称为垫片)241。将电解液242分别注入相对地设置的阴极电极箔200与阳极电极箔204之间。在密封片207中,设置混入了垫片241的电解液242嵌入的开口部分和与插头2的间隔一致的贯通孔201。密封片207密封电解液242并且使电极箔200和电极箔204接合成一体。这样一来能够构成根据本实施形态的片式电容。The substantially spherical insulating spacer 241 has a diameter of 5 to 20 μm, and the insulating spacer (hereinafter, referred to as a spacer) 241 is mixed in the electrolytic solution 242 for driving. The electrolytic solution 242 is respectively injected between the
根据这样的构成,通过只层积相同形状的电极箔200、电极箔204和密封片207,就能够容易地使电容的电容量增大到只与层积的数量的倍数相当的量。因此,能够容易地使电容的电容量实现特制化。又,因为通过层积,ESR成为与层积的数量相当的1,所以也容易设计ESR。According to such a configuration, the capacitance of the capacitor can be easily increased by a multiple of the number of layers by only stacking
又,通过用混入垫片241的电解液242,能够一面保持电极箔间的绝缘性,一面增加每单位面积的电极箔间的电解液量。这是因为这种构成的密度比片状的分隔器小。又,也能够根据垫片241的直径任意地设定用分隔器难以处理的数μm的电极箔间的距离。因此,能够使电解液242的层变薄。从而能够减小ESR。In addition, by using the electrolytic solution 242 mixed in the spacer 241, the amount of the electrolytic solution per unit area between the electrode foils can be increased while maintaining the insulation between the electrode foils. This is because the density of this structure is lower than that of a sheet-like separator. In addition, the distance between the electrode foils of several μm, which is difficult to handle with a separator, can also be set arbitrarily according to the diameter of the spacer 241 . Therefore, the layer of the electrolytic solution 242 can be thinned. Thereby, ESR can be reduced.
(实施形态20)(Embodiment 20)
图42是表示用根据本发明的实施形态20的片式电容的IC插座及其使用状态的分解立体图。将连接用插头(以下,称为插头)2设置在以CPU为代表的IC1的下面。在本实施形态中表示用478个插头的IC组件的例子。Fig. 42 is an exploded perspective view showing an IC socket using a chip capacitor according to Embodiment 20 of the present invention and its usage state. Connecting plugs (hereinafter referred to as plugs) 2 are provided under IC1 represented by a CPU. In this embodiment, an example of an IC package using 478 pins is shown.
IC插座(以下,称为插座)3备有具有片式电容(以下,称为电容)253的滑动部分243和焊接在印刷电路配线板(以下,称为基板)4上的覆盖部分244。在滑动部分243中与插头2对应地设置多个插头2贯通的贯通孔245。在贯通孔245中,只在需要与IC1连接的插头2贯通的贯通孔245中,形成与插头2导通的接触部分246(图中的涂黑部分)。IC socket (hereinafter referred to as socket) 3 has sliding
在覆盖部分244中同样地设置与设置在滑动部分243中的贯通孔245对应的贯通孔247。进一步在覆盖部分244中使图中的前面一侧和里面一侧(图中未画出)成为一对地互相相对地设置引导器248。引导器248能够沿图中的左右方向自由滑动地系合保持滑板243。又覆盖部分244作为滑动部分243的驱动机构,具有轴孔249、以轴孔249为中心旋转的凸轮250和使凸轮250旋转的杠杆251。又如图44所示,在贯通孔247中,只在需要与IC1连接的插头2贯通的贯通孔247中,形成与插头2导通的固定接点265。将固定接点265设置在通过后述的驱动机构266的操作,插头移动的一侧。A through-
图43是构成插座3的滑动部分243的分解立体图。将电容元件252安装在电容253内。电容元件252具有在表面上形成电介质氧化表面膜的阳极电极箔(以下,称为电极箔)254。在电极箔254上形成图中未画出的导电性高分子层,在其上层积形成由碳和银胶等构成的阴极层255。FIG. 43 is an exploded perspective view of the sliding
又电极箔254通过熔接、或银和碳胶等的导电性粘合剂与兼作阳极取出用配线的SUS和弹簧用磷青铜等的导电性阳极片(以下,称为片)256连接。因此电极箔254通过阳极一侧的接触部分257与IC1的插头2连接。又,阴极层255通过银和碳胶等的导电性粘合剂与兼作阴极取出用配线的SUS和弹簧用磷青铜等的导电性阴极片(以下,称为片)258连接。因此阴极层255通过阴极一侧的接触部分259与插头2连接。进一步通过配设在它们之间的绝缘片260使片256、258绝缘。绝缘片260由PET、PC、PVC(聚C1乙烯)、PA、PI、PAI等的高分子材料构成。这样一来能够构成电容253。The
电容253被在覆盖部分244上自由滑动地系合保持的滑动盖262和绝缘片263所覆盖。这样一来能够构成滑动部分243。The
我们用图44说明这样包含电容253构成的插座3的工作。首先,将IC1的插头2插入设置在插座3中的贯通孔245内。在这种状态中通过操作构成驱动机构266的杠杆251使凸轮250沿图中箭头方向旋转。因此凸轮250在图中的左方向按压设置在滑动部分243上的突起部264,使滑动部分243沿同一方向移动,一直移动到图中的虚线所示的位置。结果,固定接点部分265和接触部分257、259分别夹入插头2地进行锁定,并且分别连接插头2和接触部分257、259使它们电导通。We illustrate with Fig. 44 the work that comprises the
又,通过进行与上述工作相反的工作,回到分别解除由固定接点部分265和接触部分257、259夹入插头2的锁定状态回到原来状态。在解除锁定的状态中能够容易地从插座3拔取插头2。这样,在使滑动部分243的贯通孔245与片式电容253的贯通孔245一致的状态中能够容易地将插头2插入贯通孔内和从贯通孔拔出。Also, by performing the operation opposite to the above operation, the locked state in which the
此外在图44中,在基板4上安装其它的电子部件268,为了避开IC1的突起而配置设置在电容253中的凹部267。In addition, in FIG. 44 , other
这样构成的插座3能够从IC1的插头2的根部连接电容元件252等的电子部件。因此,使电容元件252等的电子部件与IC1之间的连接距离变短,能够将导线电感(ESL)和导线电阻(ESR)抑制到很低的值。The
(实施形态21)(Embodiment 21)
图45A、45B表示用根据本发明的实施形态21的片式电容的IC插座的接触部分的构成。45A and 45B show the configuration of the contact portion of the IC socket using the chip capacitor according to
插入IC1的连接用插头(以下,称为插头)2的贯通孔(以下,称为孔)245比插头2大地形成。将贯通孔(以下,称为孔)247设置在插座3的覆盖部分244中。在具有弹性的导电性片中形成具有直线部分的半圆状的贯通孔(以下,称为孔)269。与贯通孔269邻接地形成缝隙270。在贯通孔269与缝隙270之间形成具有弹性的接触部分271。A through-hole (hereinafter, referred to as a hole) 245 of a connection plug (hereinafter, referred to as a plug) 2 into which the
接触部分271,如图45B所示,当插入IC1的插头2使如图44所示的滑动部分243沿图中的箭头方向移动时孔245、269也在同一方向中移动。因此,夹住插头2具有弹性的接触部分271的两端向孔269一侧扩张地形变。由于该形变即便当在插头2中存在间隔偏离时,通过具有弹性的接触部分271也能够确实地使插头2与接触部分271接触。又在图21A的状态中,因为覆盖部分244的孔247不与插头2接触,所以能够容易地插入拔出插头2。
图46A、46B是表示接触部分的其它例子的平面图,图46C、46D分别是图46A,图46B的截面图。在具有弹性的导电性阳极片(以下,称为片)256中形成贯通孔(以下,称为孔)272,在内部具有突起。通过在孔272内插入插头2使上述突起弯折,构成具有弹性的接触部分273。在对极一侧的阴极导电性片(以下,称为片)258中,为了不与插头2导通而形成大的开口部分274。绝缘片260保持片256、258之间的绝缘。盖片262覆盖在片256上。将固定接点部分265设置在孔247中。46A and 46B are plan views showing other examples of contact portions, and FIGS. 46C and 46D are cross-sectional views of FIGS. 46A and 46B, respectively. A through-hole (hereinafter, referred to as a hole) 272 is formed in an elastic conductive anode sheet (hereinafter, referred to as a sheet) 256 and has a protrusion inside. By inserting the
这样构成的接触部分273,如图46B、46D所示,当插入插头2使滑动部分243沿图中的箭头方向移动时孔245、272也在同一方向中移动。因此,在与固定接点部分265之间夹住插头2具有弹性的接触部分273向外侧弯曲地形变。由于该形变即便当在插头2中存在间隔偏离时,由于具有弹性的接触部分273能够确实地使插头2与接触部分273接触。又,在图22A、22C的状态中,因为覆盖部分244的孔247和固定接点部分265不与插头2接触,所以能够容易地插入拔出插头2。With the
(实施形态22)(Embodiment 22)
图47A~47C是表示根据本发明的实施形态22的片式电容的制造方法中从原材料到冲压加工工序的阳极片、绝缘片和阴极片的制造工序图。阴极片(以下,称为片)片275由弹簧用磷青铜和SUS等的弹簧材料,或铜·铁·铝,或将弹性膜和金属箔层叠起来得到的导电性片等构成。片275的厚度为0.05~0.3mm。首先,在片275上,用已经描述的实施形态所示的通过冲压加工在所定位置上形成与IC1的连接用插头(以下,称为插头)2不接触的逃逸贯通孔276。47A to 47C are diagrams showing the manufacturing steps of an anode sheet, an insulating sheet, and a cathode sheet from raw materials to a pressing process in a method of manufacturing a chip capacitor according to
绝缘片(以下,称为片)277由厚度为0.01~0.3mm的PET、PP、PC片等的绝缘材料和PI、PAI、PEEK等的耐热绝缘片等的高分子材料构成。在片277上,通过冲压加工在所定位置上形成IC1的全部插头2不接触地贯通的逃逸贯通孔278,在中央部分形成开口部分279。The insulating sheet (hereinafter, referred to as sheet) 277 is composed of insulating materials such as PET, PP, and PC sheets with a thickness of 0.01 to 0.3 mm, and polymer materials such as heat-resistant insulating sheets such as PI, PAI, and PEEK. On the
阳极片(以下,称为片)280是由与片275同样的材料以同样的厚度形成的。在片280中,通过冲压加工在所定位置上形成不与IC1的连接用插头2接触的逃逸贯通孔281,又在中央部分形成开口部分282。The anode sheet (hereinafter referred to as sheet) 280 is formed of the same material as
图48A~48C是用平面图、正面图和下面图表示从图47所示的完成加工的片275、277、280的粘合到凹部形成工序的制造工序图。工序在图中从左到右地进行。首先,用加热器283将完成加工的片275和片280加热到片277熔融的温度。而且,在它们之间夹入成为绝缘层的片277,通过用滚筒284加压进行层叠。接着,为了避开IC1的突起通过成形用的冲压(以下,称为冲压)285在中央部分形成凹部286。这样一来,能够制作备有阴极·阳极配线图案的配线层叠片(以下,称为片)287。FIGS. 48A to 48C are manufacturing process diagrams showing the process from adhesion to concave portion formation of the
此外,最好一面将片277加热到软化的温度一面进行冲压285实现成形。因此能够使凹部286的形状具有良好的保持性。又,也可以在片275与片280之间夹入片277,用超声波熔接进行粘合。又,也可以代替片277,通过印刷热硬化或UV硬化的绝缘涂料形成绝缘层。In addition, it is preferable to press 285 while heating the
图49A~49C是用平面图、正面图和下面图表示在图48所示的完成加工的片287上形成接触部分,安装电容元件的工序的制造工序图。工序在图中从左到右地进行。首先,用冲压机289在片287上形成与IC1的插头2连接的接触部分288(图中的涂黑部分)。这样,通过1次冲压在片275和片280中同时开孔形成接触部分288,极大地减小了与IC1的各插头2接触的各孔的间隔偏离。49A to 49C are manufacturing process diagrams showing the steps of forming a contact portion on the processed
又,在本实施形态中,在片275、280上形成接触部分288前,在除去形成逃逸贯通孔276、278、281和接触部分288的部分的部分中形成凹部286。用这种方法,即便当片275和片280上存在粘合偏离时,也能够形成稳定的凹部286。又,在形成凹部286后通过同时一体地形成接触部分288,能够形成没有间隔偏离的接触部分288。Also, in this embodiment, before the
其次,通过用棉球291拾起银、碳和铜等的导电胶(以下,称为胶)290,转运到在片287上形成的凹部286的底面(阴极),涂敷胶290。接着,使电容元件292的阴极电极部分(以下,称为电极部分)293与涂敷在凹部286的底面上的胶290密切接触。这时,使电容元件292的阳极电极部分(以下,称为电极部分)294与片280的接触部分295接触地配置电容元件292。此后,使胶290干燥。Next, conductive paste (hereinafter, referred to as paste) 290 of silver, carbon, copper, etc. is picked up by
接着,可以用电熔接296和激光熔接等的熔接方法将电容元件292的电极部分294与片280的连接部分连接起来。这样一来,使片287和电容元件292电连接起来。此外,将电容元件292配设在使设置在片277的中央的开口部分279和设置在片280的中央的开口部分282一体化的部分上。用这种方法,能够得到小型·薄型化的紧凑的片式电容。此外,也可以代替片280,在片275的中央部分设置开口部分。Next, the
此外,图50是表示构成接触部分288的孔的形状的平面图。在最上部的片280中,形成直径比插头2的外径大的逃逸贯通孔281。在配置在它下面片275中,形成比逃逸贯通孔281小的逃逸贯通孔278。进一步在配置在它的下面的片265中形成部分地比插头2的外径小的椭圆形的贯通孔276。这样一来,形成阴极一侧的接触部分288A。在阳极一侧的接触部分288B中形成与阴极一侧的接触部分288A相反的贯通孔。即,在片280中形成部分地比插头2的外径小的椭圆形的贯通孔。因此,即便当片275、片280和片277中存在偏离时,通过用片277覆盖非接触的逃逸贯通孔能够增加绝缘性。又,由于片277从逃逸贯通孔露出的部分能够增加连接稳定性。此外,设置在片275、280中的椭圆形的逃逸贯通孔与实施形态1同样,也可以是具有部分地比插头2的外径小的部分的长方形和星形。In addition, FIG. 50 is a plan view showing the shape of the hole constituting the
图51是表示电容元件292的构成的截面图。在由在表面上形成电介质氧化表面膜的铝箔构成的电极部分294的外表面上,形成由噻吩等的功能性高分子构成的固体电解质层299。进一步在它的表面上形成由碳和银胶等构成的电极部分293。这样一来,能够构成片式的电容元件292。此外,如果电容元件292是钽电容元件、陶瓷电容元件、湿式的电解电容元件、电二层电容元件、片电池元件等,能够形成片状的元件,则对电容元件292没有特别的限定。FIG. 51 is a cross-sectional view showing the configuration of the
图52A、52B是用平面图和正面图表示图49所示的从保护安装在完成加工的片287上的电容元件292的盖片的贴附工序到切断成最终的各个片的工序的制造工序图。工序在图中从左到右地进行。首先,将设置了IC1的插头2贯通的逃逸贯通孔300的由绝缘性高分子材料构成的盖片301重叠在片287上。而且将它搬入分割成上下的真空槽302内密闭起来,用真空泵303将真空槽302内抽成真空。而且在真空槽302内部成为真空状态的状态中,用热冲压304将盖片301压叠在片287上。这样一来,为了密封电容元件292而进行熔接,最后用切断冲压机305切断成各个片。这样一来,能够制作片式电容306。盖片301形成绝缘层。此外,也可以代替用真空槽302使盖片301与片287之间形成真空密封电容元件292,在非活性气体中进行密封。用这些方法,能够防止电容元件292的氧化,提高片式电容的可靠性。52A, 52B are plan views and front views showing the manufacturing process from the attaching process of the cover sheet for protecting the
此外,在本实施形态中,我们说明了只在片275的上面配设片277的构成,但是需要时也可以在下面熔接或贴附绝缘片277。In addition, in this embodiment, we have described the configuration in which the
又,由片277、301构成的绝缘层也可以用由环氧树脂、密胺、硅和聚氨基甲酸脂等的绝缘涂料、PET、PP、PC片等的绝缘材料和PI、PAI、PEEK等的耐热绝缘片形成。又,各片的连接也可以是用粘合剂进行粘合的构造。又,也可以通过由树脂成形进行覆盖,或用绝缘片覆盖表面,或用涂敷材料进行涂敷,或印刷绝缘涂料,形成外包装。Also, the insulating layer made of
此外,如果通过印刷热硬化或UV硬化的绝缘涂料构成片277,则没有由滚筒生产中的膜的伸张和收缩引起的片277的贴附偏离那样的问题。又,也可以用热可逆性的绝缘片形成片277,通过加热片275和片280与片277热粘合。如果用这种方法,则通过在热粘合前一直将片277保持在常温中,能够在将热引起的形变抑制到最小限度的状态中,热粘合片275、280。因此,能够得到可靠性高的片式电容。又,代替由加热进行热粘合,用超声波热粘合片275、277、280也能够得到同样的效果。In addition, if the
此外,也可以通过追加绝缘片和阳极片,层积在片275的里面,将特性不同的电容元件连接起来。用这种方法,能够容易地构成统括地搭载了电压不同的电容元件、由陶瓷·功能性高分子·膜等构成的特性不同的电容元件和电池元件的片式电容。In addition, an insulating sheet and an anode sheet may be added and laminated inside the
如上所述根据本发明的第1片式电容具有在IC的连接用插头嵌入的贯通孔中在需要与上述IC的连接用插头电连接的贯通孔内形成的接触部分、和与该接触部分连接的电容元件。又根据本发明的第2片式电容具有分别在上面与IC连接用的接合面,在下面与印刷电路配线板连接用的接合面。而且电容元件与各连接用接合面电连接。根据这些构成中的任何一种构成,通过直接在IC近旁连接大电容量低ESL的电容元件,能够增大IC的周边电路的安装面积。又根据本发明的第3片式电容备有在单面上具有阳极电极部分的阳极片、在单面上具有阴极电极部分的阴极片、配设在它们之间的电解液、和密封电解液的密封片。密封片配设在阳极片和阴极片之间,与阳极片和阴极片接合成一体。根据这种构成,能够从阳极片和阴极片分别直接向阳极电极部分、阴极电极部分供电。又,使与阴极片和阳极片的电导通路径密封。因此,能够得到ESL、ESR减小了的电容。进一步在构造上,因为使电容的厚度变薄所以能够高密度地安装IC的周边电路。As mentioned above, the first chip capacitor according to the present invention has a contact portion formed in the through hole that needs to be electrically connected to the above-mentioned IC connection plug in the through hole into which the IC connection plug is inserted, and a contact portion connected to the contact portion. the capacitive element. Furthermore, the second chip capacitor according to the present invention has joint surfaces for connecting to an IC on the upper surface and joint surfaces for connecting to a printed wiring board on the lower surface. And the capacitive element is electrically connected to each connecting surface. According to any of these configurations, it is possible to increase the mounting area of the peripheral circuits of the IC by directly connecting a capacitive element with a large capacitance and low ESL near the IC. Also according to the 3rd sheet capacitor of the present invention, there is an anode sheet with an anode electrode part on one side, a cathode sheet with a cathode electrode part on one side, an electrolyte solution arranged between them, and a sealed electrolyte solution. seal sheet. The sealing sheet is arranged between the anode sheet and the cathode sheet, and is integrated with the anode sheet and the cathode sheet. According to this configuration, power can be directly supplied to the anode electrode portion and the cathode electrode portion from the anode tab and the cathode tab, respectively. Also, the electrical conduction paths with the cathode sheet and the anode sheet are sealed. Therefore, a capacitance with reduced ESL and ESR can be obtained. Furthermore, in terms of structure, since the thickness of the capacitor is reduced, it is possible to mount the peripheral circuits of the IC with high density.
又根据本发明的IC插座备有具有上述第1片式电容而构成的滑动部分、和能够使滑动部分自由滑动地系合的覆盖部分。覆盖部分与印刷电路配线板接合。在覆盖部分上设置IC的连接用插头嵌入的贯通孔。在该贯通孔中,在需要与上述IC的连接用插头电连接的贯通孔内形成固定接点部分。进一步,覆盖部分具有使滑动部分滑动的凸轮和杠杆。根据这种构成,在使滑动部分的贯通孔和片式电子部件的贯通孔一致的状态中,能够容易地将IC的连接用插头插入贯通孔内或从贯通孔拔出。又,在使用状态,因为由于滑动部分的各贯通孔的接触部分和固定接点使弹性在夹入IC的连接用插头的方向中起作用,所以能够锁定连接用插头并且能够确实地电连接接触部分和连接用插头。Furthermore, the IC socket according to the present invention includes a sliding portion having the above-mentioned first chip capacitor, and a covering portion that is coupled so that the sliding portion can slide freely. The covering portion is bonded to the printed circuit wiring board. The cover part is provided with a through-hole into which the IC connection plug is fitted. In this through hole, a fixed contact portion is formed in the through hole that needs to be electrically connected to the above-mentioned IC connection plug. Further, the covering portion has a cam and a lever for sliding the sliding portion. According to this configuration, the IC connection plug can be easily inserted into or pulled out from the through hole in a state where the through hole of the sliding portion is aligned with the through hole of the chip electronic component. Also, in the state of use, since the contact portion of each through hole of the sliding portion and the fixed contact make the elasticity act in the direction of the connection plug sandwiching the IC, the connection plug can be locked and the contact portion can be reliably electrically connected. and connection plugs.
在本发明的制造片式电容的方法中,首先,将绝缘片夹入导电性阴极片与导电性阳极片之间。此外,在绝缘片上在IC的全部连接用插头预先非接触地嵌入的部分中设置逃逸贯通孔。在阴极片与阳极片上,预先在与连接用插头非接触的部分中分别设置直径比连接用插头的外径大的逃逸贯通孔。其次,在与分别设置在阴极片、绝缘片和阳极片上的逃逸贯通孔一致的状态中进行层叠。而且,与连接用插头连接的接触部分同时与阴极片和阳极片形成一体。在IC的连接用插头嵌入的贯通孔中,在需要与连接用插头电连接的贯通孔内形成接触部分。根据这种方法,能够稳定并提供对于IC的连接用插头间隔偏离少的片式电容。In the method for manufacturing a chip capacitor of the present invention, first, an insulating sheet is sandwiched between a conductive cathode sheet and a conductive anode sheet. In addition, an escape through-hole is provided in the insulating sheet in a portion where all the connection pins of the IC are fitted in advance in a non-contact manner. On the cathode sheet and the anode sheet, escape through holes having a diameter larger than the outer diameter of the connection plug are respectively provided in advance in portions not in contact with the connection plug. Next, lamination is performed in a state corresponding to the escape through-holes respectively provided on the cathode sheet, insulating sheet, and anode sheet. Furthermore, the contact portion to be connected to the connection plug is integrally formed with the cathode tab and the anode tab at the same time. A contact portion is formed in the through-hole to be electrically connected to the connection plug in the through-hole into which the connection plug of the IC is fitted. According to this method, it is possible to stably provide a chip capacitor with little variation in the pitch of the connecting pins to the IC.
此外,能够在可能的范围内将以上说明的根据本发明的各实施形态的特征组合起来加以实施,这种组合在本发明的范畴内。In addition, the features of the embodiments of the present invention described above can be combined and implemented within a possible range, and such combinations are within the scope of the present invention.
Claims (17)
Applications Claiming Priority (24)
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JP2002-315710 | 2002-10-30 | ||
JP2002315710A JP4186589B2 (en) | 2002-10-30 | 2002-10-30 | Sheet-type electronic component module |
JP2002315710 | 2002-10-30 | ||
JP2002329450 | 2002-11-13 | ||
JP2002-329450 | 2002-11-13 | ||
JP2002329450A JP4161686B2 (en) | 2002-11-13 | 2002-11-13 | Sheet-type electronic component module |
JP2002-334824 | 2002-11-19 | ||
JP2002334824 | 2002-11-19 | ||
JP2002334824A JP4093027B2 (en) | 2002-11-19 | 2002-11-19 | Sheet-type electronic component module |
JP2003-004453 | 2003-01-10 | ||
JP2003004453 | 2003-01-10 | ||
JP2003004453A JP4107089B2 (en) | 2003-01-10 | 2003-01-10 | IC socket with sheet-type electronic components |
JP2003-021820 | 2003-01-30 | ||
JP2003021820 | 2003-01-30 | ||
JP2003021820A JP4186638B2 (en) | 2003-01-30 | 2003-01-30 | Sheet type capacitor module |
JP2003023773 | 2003-01-31 | ||
JP2003023773A JP2004235521A (en) | 2003-01-31 | 2003-01-31 | Process for producing sheet capacitor module |
JP2003-023773 | 2003-01-31 | ||
JP2003-134087 | 2003-05-13 | ||
JP2003134087 | 2003-05-13 | ||
JP2003134088A JP2004342647A (en) | 2003-05-13 | 2003-05-13 | Sheet type electrolytic capacitor |
JP2003-134088 | 2003-05-13 | ||
JP2003134088 | 2003-05-13 | ||
JP2003134087A JP4314878B2 (en) | 2003-05-13 | 2003-05-13 | Sheet electrolytic capacitor |
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CNB2003101047242A Division CN1319085C (en) | 2002-10-30 | 2003-10-30 | Flat capacitor and IC socket using same, making method of such capacitor |
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CN1975948B true CN1975948B (en) | 2010-08-04 |
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CN2006101567556A Expired - Fee Related CN1975948B (en) | 2002-10-30 | 2003-10-30 | Chip Capacitor |
CN2006101567560A Expired - Fee Related CN101017733B (en) | 2002-10-30 | 2003-10-30 | Ic socket |
CN2006101567541A Expired - Fee Related CN1975942B (en) | 2002-10-30 | 2003-10-30 | Chip Capacitor |
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KR102048319B1 (en) * | 2018-07-20 | 2019-11-25 | 삼성전자주식회사 | Semiconductor package |
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US5168432A (en) * | 1987-11-17 | 1992-12-01 | Advanced Interconnections Corporation | Adapter for connection of an integrated circuit package to a circuit board |
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GB2176654B (en) * | 1985-06-11 | 1988-08-10 | Avx Corp | Method for optimising the decoupling of integrated circuit devices |
JPH0620882A (en) * | 1992-06-30 | 1994-01-28 | Matsushita Electric Ind Co Ltd | Chip-type solid-state electrolytic capacitor |
TW456074B (en) * | 1998-02-17 | 2001-09-21 | Advantest Corp | IC socket |
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2002
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2003
- 2003-10-30 CN CN2006101567575A patent/CN1975950B/en not_active Expired - Fee Related
- 2003-10-30 CN CN2006101567556A patent/CN1975948B/en not_active Expired - Fee Related
- 2003-10-30 CN CN2006101567560A patent/CN101017733B/en not_active Expired - Fee Related
- 2003-10-30 CN CN2006101567541A patent/CN1975942B/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5168432A (en) * | 1987-11-17 | 1992-12-01 | Advanced Interconnections Corporation | Adapter for connection of an integrated circuit package to a circuit board |
Non-Patent Citations (1)
Title |
---|
JP昭58-133928U 1983.09.09 |
Also Published As
Publication number | Publication date |
---|---|
JP2004152948A (en) | 2004-05-27 |
CN1975950B (en) | 2010-10-20 |
JP4186589B2 (en) | 2008-11-26 |
CN101017733A (en) | 2007-08-15 |
CN101017733B (en) | 2010-08-25 |
CN1975950A (en) | 2007-06-06 |
CN1975942B (en) | 2010-05-19 |
CN1975942A (en) | 2007-06-06 |
CN1975948A (en) | 2007-06-06 |
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