CN217214477U - Electronic component packaging structure and semi-finished product assembly - Google Patents
Electronic component packaging structure and semi-finished product assembly Download PDFInfo
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- 239000003990 capacitor Substances 0.000 claims abstract description 190
- 239000000463 material Substances 0.000 claims abstract description 188
- 230000001681 protective effect Effects 0.000 claims abstract description 109
- 239000000853 adhesive Substances 0.000 claims abstract description 28
- 230000001070 adhesive effect Effects 0.000 claims abstract description 28
- 239000003292 glue Substances 0.000 claims abstract description 23
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 57
- 229910052802 copper Inorganic materials 0.000 claims description 42
- 239000010949 copper Substances 0.000 claims description 42
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 35
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 30
- 229910052725 zinc Inorganic materials 0.000 claims description 30
- 239000011701 zinc Substances 0.000 claims description 30
- 229910052759 nickel Inorganic materials 0.000 claims description 29
- 238000007747 plating Methods 0.000 claims description 17
- 238000009713 electroplating Methods 0.000 claims description 9
- 239000007787 solid Substances 0.000 abstract description 19
- 239000000306 component Substances 0.000 description 85
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- 229910052751 metal Inorganic materials 0.000 description 16
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 15
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- 239000011248 coating agent Substances 0.000 description 12
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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 12
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000748 compression moulding Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
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- 239000003365 glass fiber Substances 0.000 description 1
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- 150000002739 metals Chemical class 0.000 description 1
- 150000002815 nickel Chemical class 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
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- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G9/00—Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
- H01G9/15—Solid electrolytic capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G9/00—Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
- H01G9/0029—Processes of manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G9/00—Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
- H01G9/004—Details
- H01G9/08—Housing; Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G9/00—Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
- H01G9/004—Details
- H01G9/14—Structural combinations or circuits for modifying, or compensating for, electric characteristics of electrolytic capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
本实用新型公开一种电子组件封装结构及半成品组合体。电子组件封装结构包括多个保护基板、一第一电容芯子、一绝缘胶材、一阳极端子以及一阴极端子。多个保护基板彼此间隔地叠放设置,并且相邻的任意两个保护基板之间设置有一导电薄材。第一电容芯子设置于多个保护基板之间并共同形成一夹层结构。第一电容芯子包含一阴极与一阳极。一绝缘胶材填满多个保护基板及第一电容芯子之间的空隙,并与多个保护基板及第一电容芯子共同形成一扁平体结构。阳极端子与阴极端子位于扁平体结构的相对两端。借此,获得低轮廓、低ESR(等效串联电阻)和高可靠性的固体电解电容器。
The utility model discloses an electronic component packaging structure and a semi-finished product assembly. The electronic component packaging structure includes a plurality of protective substrates, a first capacitor core, an insulating glue material, an anode terminal and a cathode terminal. A plurality of protection substrates are stacked and arranged at intervals, and a conductive thin material is arranged between any two adjacent protection substrates. The first capacitor core is disposed between the plurality of protective substrates and forms a sandwich structure together. The first capacitor core includes a cathode and an anode. An insulating adhesive material fills the gaps between the plurality of protection substrates and the first capacitor cores, and forms a flat body structure together with the plurality of protection substrates and the first capacitor cores. Anode terminals and cathode terminals are located at opposite ends of the flat body structure. Thereby, a solid electrolytic capacitor with low profile, low ESR (equivalent series resistance) and high reliability is obtained.
Description
技术领域technical field
本实用新型涉及一种电子组件封装结构及一种适用于电子组件封装结构的半成品组合体,特别是涉及包含电容芯子的一种电子组件封装结构及一种半成品组合体。The utility model relates to an electronic component packaging structure and a semi-finished product assembly suitable for the electronic component packaging structure, in particular to an electronic component packaging structure including a capacitor core and a semi-finished product assembly.
背景技术Background technique
现有的固体电解电容器具有低矮、高电容、低ESR(等效串联电阻)的特点,因此其适合在小尺寸的高频电子系统中进行表面贴装(组装)。进一步地说,现有的固体电解电容组件通常是由一个或多个固体电解电容芯子堆栈在一起,并用绝缘材料包装而成。此外,固体电解电容芯子的电极(阳极和阴极) 将通过多个电触点以连接到封装外表面上的端子。The existing solid electrolytic capacitors have the characteristics of low profile, high capacitance, and low ESR (equivalent series resistance), so they are suitable for surface mounting (assembly) in small-sized high-frequency electronic systems. Further, the existing solid electrolytic capacitor components are usually formed by stacking one or more solid electrolytic capacitor cores and packing them with insulating materials. In addition, the electrodes (anode and cathode) of the solid electrolytic capacitor core will pass through a number of electrical contacts to connect to terminals on the outer surface of the package.
需要说明的是,现有的固体电解电容芯子(以下简称为:电容芯子)通常由铝基形成,并且上述铝基的大部分表面被蚀刻以对应形成多个深孔,进而增加有效表面积。而一层非常薄的氧化铝形成于具有多个深孔的铝基的表面上,以作为电容芯子的介电接口。此外,在电容芯子的电介质接口上,连续的导电聚合物(固体电解质)和导电涂层(通常是碳粉和银颗粒黏合剂)将被沉积下来并对应成为阴极,而铝基的主体将作为阳极。其中,铝基一端未沉积导电聚合物,而涂层的一小部分将用于阳极的外部连接。It should be noted that the existing solid electrolytic capacitor core (hereinafter referred to as: capacitor core) is usually formed of aluminum base, and most of the surface of the above-mentioned aluminum base is etched to form a plurality of deep holes correspondingly, thereby increasing the effective surface area . And a very thin layer of aluminum oxide is formed on the surface of the aluminum base with many deep holes to serve as the dielectric interface of the capacitor core. In addition, on the dielectric interface of the capacitor core, a continuous conductive polymer (solid electrolyte) and conductive coating (usually carbon powder and silver particle binder) will be deposited and correspond to the cathode, while the aluminum-based body will be as the anode. One end of the aluminum base has no conductive polymer deposited, while a small portion of the coating will be used for the external connection of the anode.
进一步地说,如图1所示,图1为一个典型的固体电解电容芯子10的剖面示意图,其自固体电解电容芯子10的阳极11到阴极12进行剖面。其中,电介质接口14在铝基15的表面,并且导电聚合物层16覆盖了电介质接口14,而导电涂层于最外侧表面12以银胶覆盖在导电聚合物层16上。因此,在其外部视图中,如图2A中的组件10A所示,大部分的表面区域被银胶12覆盖在阴极层(图未标)上,而阳极11在一端。Further, as shown in FIG. 1 , FIG. 1 is a schematic cross-sectional view of a typical solid
需要说明的是,在阳极11和阴极12的区域之间通常涂有屏障涂层,以防止阳极11和阴极12这两个区域之间的短路。举例来说,如图2A中的屏障涂层13A所示,并且屏障涂层13A的宽度可以很窄,或者如图2B中的屏障涂层13B所示,屏障涂层13B的宽度也可以很宽以覆盖阳极的大部分区域,除了阳极端的尖端面11B。It should be noted that a barrier coating is usually applied between the regions of the
需要强调的是,现有的固体电解电容装置的封装,是将一个或多个电容芯子10封装在绝缘材料中,并将阳极11和阴极12与外部端子电性连接。然,由于电容芯子10的电容设置于电介质接口14,对于固定尺寸的铝基15来说,电介质接口14覆盖于铝基15的表面积较佳可以是最大化。因此,阳极末端的暴露面积相对较小。此外,为了最大限度地减少包装电容器装置的面积和外形,最好使包装外壳尽可能地靠近电容芯子。It should be emphasized that, in the packaging of the existing solid electrolytic capacitor device, one or
由于上述原因,目前在尽量减少电容器包装方面有两个挑战。首先是第一个挑战,外部终端最好尽可能地靠近阳极和阴极,连接导体的尺寸应最小。但由于阳极区域很小,在这个小区域建立和保持良好的电气连接成为一个挑战。此外,当多个电容芯子堆栈在一起,以增加设备的总电容时,这个阳极连接问题将变得更加关键。举例来说,如图2A至图2C所示,可知阳极连接必须在阳极末端11B的尖端面进行,因为该处是唯一可用于进行电接触的暴露区域。For the above reasons, there are currently two challenges in minimizing capacitor packaging. The first challenge is that the external terminations are preferably as close to the anode and cathode as possible and the size of the connecting conductors should be minimal. But since the anode area is so small, it becomes a challenge to make and maintain good electrical connections in this small area. Furthermore, this anode connection issue becomes even more critical when multiple capacitor cores are stacked together to increase the overall capacitance of the device. For example, as shown in Figures 2A-2C, it is known that the anode connection must be made at the tip face of the
然,使情况进一步复杂化的是,由于金属铝的高活性,在暴露的阳极表面和尖端区域上总是有一层非常薄的氧化铝薄膜。这层氧化膜不仅影响了导电性,而且还妨碍了与任何外部终端的有效等电位化。Of course, to further complicate the situation, there is always a very thin film of aluminum oxide on the exposed anode surface and tip area due to the high activity of metallic aluminum. This oxide film not only affects conductivity, but also prevents effective equipotentialization with any external terminations.
其次是第二个挑战,包裹电容芯子的绝缘材料应尽可能地薄。但是传统的封装工艺(如:通过传递模塑成型的模塑工艺)使用大压力驱使与高黏性材料流动入模成型。而为了制造薄的绝缘材料,必须减少模具壁和电容芯子之间的间距,但在相同的材料流率下,这会增加电容芯子上的黏性应力。使用压缩成型的工艺可以减少压力流,但仍不能将其消除。另外有模压成型的工艺,也涉及到高压力。The second challenge is that the insulating material surrounding the capacitor core should be as thin as possible. But traditional encapsulation processes (eg, molding by transfer molding) use high pressure to force the flow of highly viscous materials into the mold. In order to make thin insulating materials, the spacing between the mold wall and the capacitor core must be reduced, but at the same material flow rate, this increases the viscous stress on the capacitor core. The process of using compression molding can reduce pressure flow, but still cannot eliminate it. In addition, there is a process of compression molding, which also involves high pressure.
承上所述,因为固体电解电容芯子通常缺乏良好的机械强度,并且因为上述种种因素,使得在不损坏电容芯子或电极连接的情况下包装薄型电容器变得极为困难。Having said that, because solid electrolytic capacitor cores generally lack good mechanical strength, and because of the above-mentioned factors, it is extremely difficult to package thin capacitors without damaging the capacitor core or electrode connections.
目前针对上述技术问题,已有许多人针对其而提出对应的解决办法。举例来说,如日本专利号JP 8(1996)-273983A(JPH09273983A)所载,该专利描述了一种在每个电容芯子的阳极表面上形成金属电镀层的方法,并将多个堆栈的电容芯子的阳极连接到进一步连接到另一电镀层。At present, many people have proposed corresponding solutions for the above-mentioned technical problems. For example, as set forth in Japanese Patent No. JP 8(1996)-273983A (JPH09273983A), which describes a method of forming a metal plating layer on the anode surface of each capacitor core, and combining a plurality of stacked The anode of the capacitor core is connected further to another plating layer.
举例来说,如美国专利号6,392,869B2(US6392869B2)所载,并参照该专利中的图1B、图2A、图2B和专利中的相应描述,可知该专利描述了一种用于多个电容芯子的紧凑包装。电容芯子通过导电胶堆栈在一起,并黏合在具有作为阴极外部端子的延伸部分的导体上面;接着,带有阴极导体终端的堆栈物被绝缘材料所包裹;而后,对阳极端进行抛光,以显示出堆栈的电容芯子的阳极端尖端面露出;接着,采用锌置换工艺,去除暴露的尖端面上的氧化铝膜;而后,通过无电镀在尖端面上涂上一层镍;接下来,通过无电镀再涂上一层金;接着,在电容芯子的尖端面上涂上一层导电树脂。通过上述各项制程,已经覆盖了金和镍以及周围的绝缘材料对应形成一个阳极导电弹性体,即阳极终端。For example, as set forth in US Pat. No. 6,392,869B2 (US6392869B2), and with reference to FIGS. 1B , 2A, 2B and the corresponding descriptions in the patent, it can be seen that the patent describes a Sub compact packaging. Capacitor cores are stacked together by conductive glue and adhered to conductors with extensions that serve as cathode external terminals; then, the stack with cathode conductor terminations is wrapped with insulating material; then, the anode ends are polished to The tip surface of the anode end of the stacked capacitor core is shown exposed; then, the aluminum oxide film on the exposed tip surface is removed by a zinc replacement process; then, a layer of nickel is applied to the tip surface by electroless plating; next, Another layer of gold is applied by electroless plating; then, a layer of conductive resin is applied to the tip of the capacitor core. Through the above processes, gold and nickel and surrounding insulating materials have been covered to form an anode conductive elastomer, that is, an anode terminal.
举例来说,如美国专利号10,340,092B2(US10340092B2),所载,该专利描述了另一种用于多个电容芯子的紧密封装。与美国专利号6,392,869B2 (US6392869B2)所载内容相似。美国专利号10,340,092B2(US10340092B2) 所载的电容芯子能通过导电胶堆栈并黏合在一起,而位于基底基板一侧的前导层将被用作阴极。其中,包括前导层在内的组件通过压缩成型,进而被绝缘材料完全包裹和覆盖;接着,带有组装好的电容器体的基座被切割成单个电容器体;而后,对电容器体进行滚压抛光,使每个电容器体的角和边缘都被磨圆,并使阴极前导层的尖端面和电容芯子的阳极都暴露出来;随后,与美国专利号 6,392,869B2(US6392869B2)所载内容类似,采用锌置换工艺与阳极金属铝进行电连接,然后再进行无电解镍电镀。然而,如美国专利号10,340,092B2 (US10340092B2)所载内容及其图2、图8所示,阳极端子不是导电树脂,而是通过无电镀铜、镍和锡制成。For example, as set forth in US Pat. No. 10,340,092B2 (US10340092B2), which describes another compact packaging for multiple capacitive dies. Similar to that described in US Patent No. 6,392,869B2 (US6392869B2). The capacitor cores described in US Patent No. 10,340,092B2 (US10340092B2) can be stacked and bonded together by conductive glue, and the leading layer on one side of the base substrate will be used as a cathode. Among them, the components, including the leading layer, are compression-molded, and then completely wrapped and covered by insulating material; then, the base with the assembled capacitor body is cut into individual capacitor bodies; then, the capacitor body is roll-polished , so that the corners and edges of each capacitor body are rounded, and the tip surface of the cathode leading layer and the anode of the capacitor core are exposed; The zinc replacement process makes electrical connections to the anode metal aluminum, followed by electroless nickel plating. However, as described in US Patent No. 10,340,092B2 (US10340092B2) and its Figures 2 and 8, the anode terminal is not a conductive resin, but is made of electroless copper, nickel and tin.
承上所述,尽管有针对上述问题已发展有上述诸种技术手段,电子工业和市场仍然需要低轮廓、低ESR(等效串联电阻)和高可靠性的固体电解电容器。再者,由于器件组装过程中焊料回流的热效应,微尺度的裂纹或脱落或分层会增加ESR(等效串联电阻)并降低电容器的可靠性。因此,需要更好的封装结构和更具成本效益的制造工艺。As mentioned above, despite the development of the above-mentioned technical means to address the above-mentioned problems, the electronic industry and the market still require solid electrolytic capacitors with low profile, low ESR (equivalent series resistance) and high reliability. Furthermore, micro-scale cracks or peeling or delamination due to the thermal effects of solder reflow during device assembly can increase ESR (equivalent series resistance) and reduce capacitor reliability. Therefore, better packaging structures and more cost-effective manufacturing processes are needed.
实用新型内容Utility model content
本实用新型实施例针对现有技术的不足提供一种电子组件封装结构及一种半成品组合体,其能有效地改善现有的封装结构所可能产生的缺陷。Aiming at the shortcomings of the prior art, the embodiments of the present invention provide an electronic component packaging structure and a semi-finished product assembly, which can effectively improve the possible defects of the existing packaging structure.
本实用新型的其中一个实施例公开一种半成品组合体,适用于一电子组件封装结构,所述半成品组合体包括:多个保护基板,彼此间隔地叠放设置,并且相邻的任意两个所述保护基板之间定义有多个预定位置,而对应于多个所述预定位置的每个所述保护基板的表面上进一步设置有多个导电薄材;其中,相邻的任意两个所述保护基板中的其中一个所述保护基板的边缘,超出另一个所述保护基板对其正投影所形成的一投影区域,并且超出所述投影区域的所述保护基板的部分所述表面定义为一置胶区域;多个电子芯件,位于多个所述保护基板之间,并且多个所述电子芯件设置于多个所述预定位置;其中,每个所述电子芯件包含多个接点;一导电连接材料,连接于多个所述导电薄材及部分所述接点;一绝缘胶材,填满多个所述保护基板及多个所述电子芯件之间的空隙;以及多个槽孔开口,穿过多个所述保护基板以及所述绝缘胶材,并且多个所述槽孔开口能用来使连通于所述电子芯件的部分所述接点的多个所述导电薄材露出。One of the embodiments of the present utility model discloses a semi-finished product assembly, which is suitable for an electronic component packaging structure. A plurality of predetermined positions are defined between the protective substrates, and a plurality of conductive thin materials are further provided on the surface of each of the protective substrates corresponding to the plurality of predetermined positions; The edge of one of the protective substrates exceeds a projection area formed by the orthographic projection of the other protective substrate, and the part of the surface of the protective substrate that exceeds the projection area is defined as a a glue placement area; a plurality of electronic core components located between a plurality of the protective substrates, and a plurality of the electronic core components are arranged at the predetermined positions; wherein, each of the electronic core components includes a plurality of contact points ; a conductive connecting material, connected to a plurality of the conductive thin materials and some of the contacts; an insulating adhesive material, filling the gaps between the plurality of the protective substrates and the plurality of the electronic core pieces; and a plurality of Slot openings pass through a plurality of the protective substrates and the insulating adhesive material, and a plurality of the slot openings can be used to make a plurality of the conductive thin films connected to some of the contacts of the electronic core piece. material exposed.
优选地,每个所述电子芯件进一步包含一电容芯子,并且所述电容芯子的两个所述接点分别被定义为一阳极及一阴极,而所述阴极能用来与多个所述导电薄材结合,而多个所述槽孔开口能用来使部分所述阳极露出;其中,外露的部分所述阳极的表面电镀形成有一锌层。Preferably, each of the electronic core components further includes a capacitor core, and the two contacts of the capacitor core are respectively defined as an anode and a cathode, and the cathode can be used to communicate with a plurality of all The conductive thin material is combined, and a plurality of the slot openings can be used to expose part of the anode; wherein, a zinc layer is formed on the surface of the exposed part of the anode by electroplating.
优选地,每个所述保护基板为全铜基板,并且每个所述保护基板被蚀刻后形成有多个所述导电薄材。Preferably, each of the protective substrates is an all-copper substrate, and each of the protective substrates is etched to form a plurality of the conductive thin materials.
本实用新型的其中一个实施例公开一个电子组件封装结构,其包括:多个保护基板,彼此间隔地叠放设置,并且相邻的任意两个所述保护基板之间定义有一预定位置,而对应于所述预定位置的每个所述保护基板的表面上进一步设置有多个导电薄材;一第一电容芯子,设置于所述预定位置,并与多个所述保护基板共同形成一夹层结构;其中,所述第一电容芯子包含一阴极与一阳极;一绝缘胶材,填满多个所述保护基板及所述第一电容芯子之间的空隙,并与多个所述保护基板及所述第一电容芯子共同形成一扁平体结构;一阳极端子,位于所述扁平体结构的一端;一阴极端子,位于所述扁平体结构位置远离所述阳极端子的另一端;以及一导电连接材料,连接于每个保护基板上的多个所述导电薄材及所述阴极的一部分;其中,多个所述导电薄材的一部分延伸并连接于所述阴极端子,而所述阴极端子是以镀铜的方式连接并形成于多个所述导电薄材;其中,所述阳极的一部分连接于所述阳极端子,并且所述阳极端子是以形成一导电膜的方式连接并形成于所述阳极的一部分。One of the embodiments of the present utility model discloses an electronic component packaging structure, which includes: a plurality of protective substrates, which are stacked and arranged at intervals, and a predetermined position is defined between any two adjacent protective substrates, and a corresponding A plurality of conductive thin materials are further arranged on the surface of each of the protective substrates at the predetermined position; a first capacitor core is arranged at the predetermined position and forms an interlayer together with the plurality of the protective substrates structure; wherein, the first capacitor core includes a cathode and an anode; an insulating adhesive material fills the gaps between a plurality of the protective substrates and the first capacitor core, and is connected with a plurality of the The protective substrate and the first capacitor core together form a flat body structure; an anode terminal is located at one end of the flat body structure; a cathode terminal is located at the other end of the flat body structure away from the anode terminal; and a conductive connection material, connected to a plurality of the conductive thin materials on each protective substrate and a part of the cathode; wherein, a part of the plurality of the conductive thin materials extends and is connected to the cathode terminal, and the The cathode terminal is connected by copper plating and formed on the plurality of conductive thin materials; wherein, a part of the anode is connected to the anode terminal, and the anode terminal is connected and formed in a conductive film. formed on a part of the anode.
优选地,每个所述保护基板为全铜基板,并且每个所述保护基板被蚀刻后形成有多个所述导电薄材。Preferably, each of the protective substrates is an all-copper substrate, and each of the protective substrates is etched to form a plurality of the conductive thin materials.
优选地,所述电子组件封装结构进一步包含一第二电容芯子,并且所述第二电容芯子间隔地叠放设置于所述第一电容芯子,而所述第二电容芯子位于多个所述保护基板之间;其中,多个所述保护基板、所述第一电容芯子以及所述第二电容芯子共同形成一多层芯子结构,并且所述第二电容芯子包含一阴极及一阳极,而所述第一电容芯子以及所述第二电容芯子的两个所述阴极连接于所述阴极端子,而所述第一电容芯子以及所述第二电容芯子的两个所述阳极连接于所述阳极端子。Preferably, the electronic component packaging structure further includes a second capacitor core, and the second capacitor cores are stacked on the first capacitor core at intervals, and the second capacitor cores are located in multiple between the protection substrates; wherein a plurality of the protection substrates, the first capacitor cores and the second capacitor cores together form a multi-layer core structure, and the second capacitor cores include a cathode and an anode, and the two cathodes of the first capacitor core and the second capacitor core are connected to the cathode terminal, and the first capacitor core and the second capacitor core The two anodes of the sub are connected to the anode terminals.
优选地,所述电子组件封装结构进一步包含一中层基板,并且所述中层基板设置于所述第一电容芯子以及所述第二电容芯子之间,而所述中层基板包含彼此相互分离的一阳极端导电薄材组及一阴极端导电薄材组;其中,所述阴极端导电薄材组以所述导电连接材料连接于所述第一电容芯子以及所述第二电容芯子的两个所述阴极,而所述阳极端导电薄材组连接于所述阳极端子。Preferably, the electronic component packaging structure further includes a middle-layer substrate, and the middle-layer substrate is disposed between the first capacitor core and the second capacitor core, and the middle-layer substrate includes mutually separated An anode end conductive thin material group and a cathode end conductive thin material group; wherein the cathode end conductive thin material group is connected to the first capacitor core and the second capacitor core with the conductive connecting material two of the cathodes, and the anode terminal conductive thin material group is connected to the anode terminal.
优选地,所述导电膜包含一锌层及一镍层,并且所述锌层镀于所述阳极的部分表面上,而所述镍层镀于所述锌层上。Preferably, the conductive film includes a zinc layer and a nickel layer, the zinc layer is plated on a part of the surface of the anode, and the nickel layer is plated on the zinc layer.
优选地,所述阳极具有位于相反侧的两侧面,并且两个所述侧面能以所述导电连接材料连接于多个所述保护基板以及所述阳极端子,以增强所述电子组件封装结构的结构强度。Preferably, the anode has two side surfaces on opposite sides, and the two side surfaces can be connected to a plurality of the protective substrates and the anode terminals with the conductive connection material, so as to enhance the packaging structure of the electronic component. Structural strength.
优选地,多个所述保护基板进一步包含一阳极侧导电薄材,其位于多个所述保护基板位置邻近所述阳极端子的多个端部,并且所述阳极端子覆盖于所述阳极侧导电薄材及位置邻近所述阳极端子的所述扁平体结构的端面与侧面,以对应形成五面包覆的所述阳极端子;其中,并增强所述电子组件封装结构的结构强度;其中,多个所述保护基板进一步包含一阴极侧导电薄材,其位于多个所述保护基板位置邻近所述阴极端子的多个端部,并且所述阴极端子包覆所述阴极侧导电薄材及位置邻近所述阴极端子的所述扁平体结构的端面与侧面,并增强所述电子组件封装结构的结构强度。Preferably, a plurality of the protective substrates further comprise an anode-side conductive thin material, which is located at a plurality of end portions of the protective substrates adjacent to the anode terminals, and the anode terminals are covered on the anode side to conduct electricity The thin material and the end surface and side surface of the flat body structure adjacent to the anode terminal to form the anode terminal covered on five sides correspondingly; wherein, the structural strength of the electronic component packaging structure is enhanced; wherein, many Each of the protective substrates further includes a cathode-side conductive thin material, which is located at a plurality of ends of the protective substrate adjacent to the cathode terminals, and the cathode terminals cover the cathode-side conductive thin material and the positions The end surface and the side surface of the flat body structure adjacent to the cathode terminal enhance the structural strength of the electronic component packaging structure.
本实用新型的其中一个实施例公开一种电子组件封装结构的制造方法,其包括:(a)提供一第一板材为底部基板,其上表面的多个预定位置包含导电薄材,并于所述导电薄材的部分面积涂布一结合材料;(b)将多个电子芯件放置于所述上表面的多个预定位置的所述导电薄材上的结合材料上;(c)提供一第二板材为顶部基板,其下表面的多个预定位置包含导电薄材,并于所述导电薄材的部分面积涂布所述结合材料,然后将所述顶部基板叠合于前述底部基板上,使所述多个电子组件置于所述顶部基板与所述底部基板之间,并使所述底部基板的边缘附近的一部分上表面裸露为置胶区域;(d)使所述结合材料硬化而将所述顶部基板与所述底部基板及所述多个电子芯件结合形成一基本组合体,其内部的空间形成与前述置胶区域相连通的信道;(e)将一绝缘胶材由所述置胶区域填入前述信道,将所述多个电子芯件包埋于所述顶部基板与所述底部基板之间;(f)使所述绝缘胶材硬化而使所述基本组合体与所述绝缘胶材形成一第一半成品组合体;(g)在所述第一半成品组合体上以切削制程开出多个槽孔开口,使所述顶部基板与所述底部基板的导电薄材的一部分露出,形成一第二半成品组合体;(h)在所述第二半成品组合体上的特定位置形成导电膜,与前述露出的导电薄材连通,然后在其上形成组件端子,形成一第三半成品组合体; (i)将前述第三半成品组合体切割分开为多个电子组件封装结构。One embodiment of the present invention discloses a manufacturing method of an electronic component packaging structure, which includes: (a) providing a first plate as a base substrate, a plurality of predetermined positions on the upper surface of which include conductive thin materials, and Coating a bonding material on a partial area of the conductive thin material; (b) placing a plurality of electronic core components on the bonding material on the conductive thin material at a plurality of predetermined positions on the upper surface; (c) providing a The second plate is a top substrate, a plurality of predetermined positions on the lower surface of the second plate include a conductive thin material, and the bonding material is coated on a part of the conductive thin material, and then the top substrate is laminated on the bottom substrate , placing the plurality of electronic components between the top substrate and the bottom substrate, and exposing a part of the upper surface near the edge of the bottom substrate as a glue placement area; (d) hardening the bonding material The top substrate is combined with the bottom substrate and the plurality of electronic core components to form a basic assembly, and the internal space forms a channel communicating with the aforementioned glue placement area; (e) an insulating glue material is formed by The glue placement area is filled into the aforementioned channel, and the plurality of electronic core components are embedded between the top substrate and the bottom substrate; (f) hardening the insulating glue material to make the basic assembly forming a first semi-finished product assembly with the insulating adhesive material; (g) cutting a plurality of slot openings on the first semi-finished product assembly, so that the conductive layers of the top substrate and the bottom substrate are thin A part of the material is exposed to form a second semi-finished product assembly; (h) a conductive film is formed at a specific position on the second semi-finished product assembly to communicate with the aforementioned exposed conductive thin material, and then a component terminal is formed thereon to form a third semi-finished product assembly; (i) cutting the aforesaid third semi-finished product assembly into a plurality of electronic component packaging structures.
优选地,所述绝缘胶材的填入过程系于所述置胶区域置胶使所述绝缘胶材因毛细现像流入而充满前述通道。Preferably, the filling process of the insulating adhesive material is to place adhesive in the adhesive placement area so that the insulating adhesive material fills the aforementioned channel due to the inflow of capillary phenomenon.
优选地,所述电子芯件包含电容芯子,其包含一阳极与一阴极;所述阴极由所述结合材料与前述底部基板与顶部基板上的导电薄材结合;所述第二半成品组合体上的多个槽孔开口使所述阳极的一部分露出;所述形成导电膜的过程在前述露出的阳极的一部分表面先镀上一层锌,再镀上一层镍;所述形成组件端子的过程形成阳极端子与阴极端子,所述阳极端子经由前述镍层导电膜连接所述电容芯子的阳极,所述阴极端子经由前述导电薄材连接所述电容芯子的阴极。Preferably, the electronic core component includes a capacitor core, which includes an anode and a cathode; the cathode is combined with the conductive thin material on the bottom substrate and the top substrate by the bonding material; the second semi-finished product assembly A plurality of slot openings on the anode expose a part of the anode; in the process of forming the conductive film, a layer of zinc is first plated on the surface of the exposed part of the anode, and then a layer of nickel is plated; The process forms an anode terminal and a cathode terminal, the anode terminal is connected to the anode of the capacitor core through the aforementioned nickel layer conductive film, and the cathode terminal is connected to the cathode of the capacitor core through the aforementioned conductive thin material.
本实用新型的其中一个实施例公开一种半成品组合体,其包含:底部基板与顶部基板等至少两片上下相叠的保护基板,其表面的多个预定位置包含导电薄材,所述底部基板的边缘附近的一部分上表面裸露为置胶区域;多个电子芯件,置于所述顶部基板与所述底部基板之间的多个预定位置,所述电子芯件的至少一部分接点以一导电结合材料与所述导电薄材结合;一绝缘胶材填入填满所述顶部基板与所述底部基板及所述多个电子芯件之间的空隙通道;多个槽孔开口穿过所述顶部基板与所述底部基板及所述绝缘胶材,使与所述电子芯件的接点相连通的导电部分露出。One of the embodiments of the present invention discloses a semi-finished product assembly, which includes at least two protective substrates, such as a bottom substrate and a top substrate, which are stacked on top of each other, and a plurality of predetermined positions on the surface include conductive thin materials, and the bottom substrate A part of the upper surface near the edge of the electronic core is exposed as a glue placement area; a plurality of electronic core components are placed in a plurality of predetermined positions between the top substrate and the bottom substrate, and at least a part of the contacts of the electronic core components are connected with a conductive The bonding material is combined with the conductive thin material; an insulating adhesive material is filled into the gap channel between the top substrate, the bottom substrate and the plurality of electronic core components; a plurality of slot openings pass through the The top substrate, the bottom substrate and the insulating adhesive material expose the conductive parts connected to the contacts of the electronic core components.
优选地,所述电子芯件包含电容芯子,其接点包含一阳极与一阴极;所述阴极与前述保护基板上的导电薄材结合;所述多个槽孔开口使所述阳极的一部分露出,露出的阳极表面镀有一层锌。Preferably, the electronic core component includes a capacitor core, and its contact includes an anode and a cathode; the cathode is combined with the conductive thin material on the aforementioned protective substrate; the plurality of slot openings expose a part of the anode , the exposed anode surface is plated with a layer of zinc.
优选地,所述保护基板为全铜基板,所述导电薄材为将该全铜基板蚀刻后形成。Preferably, the protective substrate is an all-copper substrate, and the conductive thin material is formed by etching the all-copper substrate.
本实用新型的其中一个实施例公开一种电子组件封装结构,其包括:底部基板与顶部基板等至少两片上下相叠的保护基板,其表面的预定位置包含导电薄材;至少一第一枚电容芯子,置于所述保护基板之间的预定位置,形成一夹层结构;一毛细充填绝缘胶材填满所述保护基板及所述电容芯子之间的空隙,形成一扁平体结构;一阳极端子与一阴极端子,分别位于前述扁平体结构的相对两端;所述电容芯子其接点包含一阳极与一阴极,所述阴极之一部分以一导电结合材料与前述保护基板上的导电薄材结合,该导电薄材延伸到前述扁平体结构的阴极端子一端,所述阴极端子以镀铜与该导电薄材连接形成,所述阳极之一部分位于前述扁平体结构的阳极端子一端,所述阳极端子以与所述阳极之一部分连接的导电膜形成。One of the embodiments of the present utility model discloses an electronic component packaging structure, which includes: at least two protective substrates, such as a bottom substrate and a top substrate, which are stacked on top of each other, and a predetermined position on the surface includes a conductive thin material; at least one first The capacitor core is placed at a predetermined position between the protection substrates to form a sandwich structure; a capillary filling insulating adhesive material fills the gap between the protection substrate and the capacitor core to form a flat body structure; An anode terminal and a cathode terminal are located at opposite ends of the flat body structure, respectively; the contact point of the capacitor core includes an anode and a cathode, and a part of the cathode is connected to a conductive material on the protective substrate with a conductive bonding material. Thin materials are combined, the conductive thin material extends to one end of the cathode terminal of the flat body structure, the cathode terminal is formed by connecting with the conductive thin material by copper plating, and a part of the anode is located at one end of the anode terminal of the flat body structure, so The anode terminal is formed with a conductive film connected to a portion of the anode.
优选地,所述保护基板为全铜基板,所述导电薄材为将该全铜基板蚀刻后形成。Preferably, the protective substrate is an all-copper substrate, and the conductive thin material is formed by etching the all-copper substrate.
优选地,所述电容组件封装结构进一步包含至少一第二枚电容芯子,叠置于所述第一枚电容芯子之上,所述底部基板与所述顶部基板之间,形成一多层芯子结构,两枚电容芯子的阴极连接到同一所述阴极端子,阳极连接到同一所述阳极端子。Preferably, the package structure of the capacitor component further includes at least one second capacitor core, which is stacked on the first capacitor core, and a multilayer is formed between the bottom substrate and the top substrate. In the core structure, the cathodes of the two capacitor cores are connected to the same cathode terminal, and the anodes are connected to the same anode terminal.
优选地,所述电容组件封装结构进一步包含一中层基板,置于所述两枚电容芯子之间,所述中层基板包含相互分离的一组阳极端导电薄材与一组阴极端导电薄材,所述阴极端导电薄材与所述两枚电容芯子的阴极以所述导电结合材料连接,所述阳极端导电薄材与所述阳极端子连接。Preferably, the capacitor component packaging structure further includes a middle-layer substrate placed between the two capacitor cores, and the middle-layer substrate includes a set of anode-end conductive thin materials and a set of cathode-end conductive thin materials separated from each other and the conductive thin material at the cathode end is connected with the cathodes of the two capacitor cores by the conductive bonding material, and the conductive thin material at the anode end is connected with the anode terminal.
优选地,所述导电膜包含直接镀于所述阳极之一部分表面上的锌层及再镀于锌层上的镍层。Preferably, the conductive film includes a zinc layer directly plated on a part of the surface of the anode and a nickel layer plated on the zinc layer.
优选地,所述阳极之上下两面进一步包含阳极侧的导电结合材料将之与所述底部基板与所述顶部基板结合,也与阳极端子结合,以增进结构的强度。Preferably, the upper and lower surfaces of the anode further comprise conductive bonding materials on the anode side to bond with the bottom substrate and the top substrate, as well as with the anode terminals to enhance the strength of the structure.
优选地,所述底部基板与顶部基板靠阳极端进一步包含面向外侧的阳极侧导电薄材,所述导电膜覆盖上述阳极侧导电薄材、前述扁平体结构的阳极端端面与侧面,形成五面包覆的阳极端子,以增进结构的强度;所述底部基板与顶部基板靠阴极端进一步包含面向外侧的阴极侧导电薄材,所述阴极端子包覆上述阴极侧导电薄材、前述扁平体结构的阴极端端面与侧面,以增进结构的强度。Preferably, the bottom substrate and the top substrate further include an anode-side conductive thin material facing outward, and the conductive film covers the anode-side conductive thin material and the anode end face and side surface of the flat body structure to form five sides. A coated anode terminal to improve the strength of the structure; the cathode end of the bottom substrate and the top substrate further includes a cathode side conductive thin material facing outward, and the cathode terminal covers the cathode side conductive thin material and the flat body structure. The end face and side of the cathode end to improve the strength of the structure.
本实用新型的其中一有益效果在于,本实用新型所提供的所述电子组件封装结构及所述半成品组合体,其能通过“所述绝缘胶材填满多个所述保护基板及所述第一电容芯子之间的空隙”的技术方案,以获得低轮廓、低ESR(等效串联电阻)和高可靠性的固体电解电容器。One of the beneficial effects of the present invention is that the electronic component packaging structure and the semi-finished product assembly provided by the present invention can fill a plurality of the protective substrates and the first A space between capacitor cores” technical solution to obtain solid electrolytic capacitors with low profile, low ESR (equivalent series resistance) and high reliability.
为能更进一步了解本实用新型的特征及技术内容,请参阅以下有关本实用新型的详细说明与附图,但是此等说明与附图仅用来说明本实用新型,而非对本实用新型的保护范围作任何的限制。In order to further understand the features and technical content of the present utility model, please refer to the following detailed description and accompanying drawings of the present utility model, but these descriptions and drawings are only used to illustrate the present utility model, not to protect the present utility model. any limitation on the scope.
附图说明Description of drawings
图1为属于先前技术的固体电解电容芯子的剖面示意图。FIG. 1 is a schematic cross-sectional view of a solid electrolytic capacitor core belonging to the prior art.
图2A为属于先前技术的固体电解电容芯子的立体示意图。FIG. 2A is a schematic perspective view of a solid electrolytic capacitor core belonging to the prior art.
图2B为属于先前技术的固体电解电容芯子的另一立体示意图。FIG. 2B is another perspective schematic diagram of a solid electrolytic capacitor core belonging to the prior art.
图2C为属于先前技术的钽电容的立体示意图。FIG. 2C is a schematic perspective view of a tantalum capacitor belonging to the prior art.
图3为本实用新型第一实施例的电子组件封装结构的剖面示意图。3 is a schematic cross-sectional view of an electronic component packaging structure according to the first embodiment of the present invention.
图4为本实用新型第一实施例的电子组件封装结构的分解示意图。4 is an exploded schematic view of the packaging structure of the electronic component according to the first embodiment of the present invention.
图5为本实用新型第一实施例的电子组件封装结构的立体示意图。FIG. 5 is a schematic perspective view of the packaging structure of the electronic component according to the first embodiment of the present invention.
图6A为本实用新型第二实施例的电子组件封装结构的剖面示意图(一)。6A is a schematic cross-sectional view (1) of an electronic component packaging structure according to the second embodiment of the present invention.
图6B为本实用新型第二实施例的电子组件封装结构的另一剖面示意图 (二)。6B is another schematic cross-sectional view (2) of the electronic component packaging structure according to the second embodiment of the present invention.
图6C为本实用新型第二实施例的电子组件封装结构的另一剖面示意图 (三)。6C is another schematic cross-sectional view (3) of the electronic component packaging structure according to the second embodiment of the present invention.
图7A为本实用新型第三实施例的电子组件封装结构的剖面示意图(一)。7A is a schematic cross-sectional view (1) of an electronic component packaging structure according to a third embodiment of the present invention.
图7B为本实用新型第三实施例的电子组件封装结构的另一剖面示意图 (二)。7B is another cross-sectional schematic diagram (2) of the electronic component packaging structure according to the third embodiment of the present invention.
图7C为本实用新型第三实施例的电子组件封装结构的另一剖面示意图 (三)。7C is another schematic cross-sectional view (3) of the electronic component packaging structure according to the third embodiment of the present invention.
图8为本实用新型第四实施例的电子组件封装结构的剖面示意图。8 is a schematic cross-sectional view of an electronic component packaging structure according to a fourth embodiment of the present invention.
图9为本实用新型第五实施例的电子组件封装结构的剖面示意图。9 is a schematic cross-sectional view of an electronic component packaging structure according to a fifth embodiment of the present invention.
图10为本实用新型第六实施例的电子组件封装结构的剖面示意图。10 is a schematic cross-sectional view of an electronic component packaging structure according to a sixth embodiment of the present invention.
图11为本实用新型第六实施例的电子组件封装结构的另一剖面示意图。11 is another schematic cross-sectional view of the electronic component packaging structure according to the sixth embodiment of the present invention.
图12为本实用新型第七实施例的电子组件封装结构的立体示意图。12 is a schematic perspective view of an electronic component packaging structure according to a seventh embodiment of the present invention.
图13为本实用新型第八实施例的电子组件封装结构的制造方法的步骤流程图。13 is a flow chart of the steps of a manufacturing method of an electronic component packaging structure according to an eighth embodiment of the present invention.
图14A为本实用新型第八实施例的电子组件封装结构的俯视示意图(一)。14A is a schematic top view (1) of the packaging structure of an electronic component according to the eighth embodiment of the present invention.
图14B为图14A的XIVB-XIVB剖面的剖面示意图。FIG. 14B is a schematic cross-sectional view of the XIVB-XIVB section of FIG. 14A .
图15A为本实用新型第八实施例的电子组件封装结构的另一俯视示意图 (二)。15A is another schematic top view (2) of the packaging structure of the electronic component according to the eighth embodiment of the present invention.
图15B为图15A的XVB-XVB剖面的剖面示意图。FIG. 15B is a schematic cross-sectional view of the XVB-XVB section of FIG. 15A .
图16为本实用新型第八实施例的电子组件封装结构的另一剖面示意图 (一)。16 is another schematic cross-sectional view (1) of the electronic component packaging structure according to the eighth embodiment of the present invention.
图17A为本实用新型第八实施例的电子组件封装结构的另一剖面示意图 (二)。17A is another cross-sectional schematic diagram (2) of the electronic component packaging structure according to the eighth embodiment of the present invention.
图17B为本实用新型第八实施例的电子组件封装结构的另一剖面示意图 (三)。17B is another schematic cross-sectional view (3) of the electronic component packaging structure according to the eighth embodiment of the present invention.
图17C为本实用新型第八实施例的电子组件封装结构的另一剖面示意图 (四)。17C is another schematic cross-sectional view (4) of the electronic component packaging structure according to the eighth embodiment of the present invention.
图18为本实用新型第八实施例的电子组件封装结构的另一俯视示意图 (三)。18 is another schematic top view (3) of the packaging structure of the electronic component according to the eighth embodiment of the present invention.
具体实施方式Detailed ways
以下是通过特定的具体实施例来说明本实用新型所公开有关“电子组件封装结构、其制造方法及半成品组合体”的实施方式,本领域技术人员可由本说明书所公开的内容了解本实用新型的优点与效果。本实用新型可通过其他不同的具体实施例加以施行或应用,本说明书中的各项细节也可基于不同观点与应用,在不背离本实用新型的构思下进行各种修改与变更。另外,本实用新型的附图仅为简单示意说明,并非依实际尺寸的描绘,事先声明。此外,以下如有指出请参阅特定图式或是如特定图式所示,其仅是用以强调于后续说明中,所述及的相关内容大部分出现于该特定图式中,但不限制该后续说明中仅可参考所述特定图式。以下的实施方式将进一步详细说明本实用新型的相关技术内容,但所公开的内容并非用以限制本实用新型的保护范围。The following are specific embodiments to illustrate the embodiments of the “electronic component packaging structure, its manufacturing method and semi-finished product assembly” disclosed in the present invention. Those skilled in the art can understand the present invention from the content disclosed in this specification. Advantages and Effects. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the accompanying drawings of the present invention are merely schematic illustrations, and are not drawn according to the actual size, and are stated in advance. In addition, if it is indicated below, please refer to a specific drawing or as shown in a specific drawing, it is only used to emphasize in the subsequent description, and most of the related content mentioned appears in the specific drawing, but is not limited In this subsequent description, reference may only be made to the specific drawings. The following embodiments will further describe the related technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention.
应当可以理解的是,虽然本文中可能会使用到“第一”、“第二”、“第三”等术语来描述各种组件或者信号,但这些组件或者信号不应受这些术语的限制。这些术语主要是用以区分一组件与另一组件,或者一信号与另一信号。另外,本文中所使用的术语“或”,应视实际情况可能包括相关联的列出项目中的任一个或者多个的组合。It should be understood that although terms such as "first", "second", "third" and the like may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another component, or one signal from another. In addition, the term "or", as used herein, should include any one or a combination of more of the associated listed items, as the case may be.
[第一实施例][First Embodiment]
请参阅图3至图5所示,其为本实用新型的第一实施例,需先说明的是,本实施例所对应到的附图及其所提及的相关数量与外形,仅用来具体地说明本实用新型的实施方式,以便于了解本实用新型的内容,而非用来局限本实用新型的保护范围。Please refer to FIG. 3 to FIG. 5 , which are the first embodiment of the present invention. It should be noted that the drawings corresponding to this embodiment and the related numbers and shapes mentioned in this embodiment are only used for The embodiments of the present invention are specifically described to facilitate understanding of the content of the present invention, rather than to limit the protection scope of the present invention.
如图3所示,本实用新型第一实施例提供一种电子组件封装结构100,其包括:一第一电容芯子10、多个保护基板20、一阳极端子30、一阴极端子40、一导电连接材料50、一绝缘胶材60、一外部阳极端子70以及一外部阴极端子80,但本实用新型不限于此。举例来说,于本实用新型的其他实施例中,所述电子组件封装结构100也可以不包含有所述外部阳极端子70以及所述外部阴极端子80。As shown in FIG. 3, the first embodiment of the present invention provides an electronic
以下为方便说明与理解,将依次说明多个所述保护基板20、所述第一电容芯子10、所述阳极端子30、所述阴极端子40、所述外部阳极端子70以及所述外部阴极端子80,并适时地说明上述各组件及所述导电连接材料50以及所述绝缘胶材60之间的相对位置关系。In the following, for the convenience of description and understanding, a plurality of the
需要事先声明的是,为方便说明与理解,图4中未绘示有所述阳极端子 30、所述阴极端子40、所述导电连接材料50以及所述绝缘胶材60,但实际上,上述组件仍存在于所述电子组件封装结构100,为避免误会,特此声明。It should be stated in advance that, for the convenience of description and understanding, the
如图3所示,于本实施例中,多个所述保护基板20彼此间隔地叠放设置,本例中每个所述保护基板20为一绝缘板体,而多个所述保护基板20的数量较佳为两个,但本实用新型不限于此。举例来说,于本实用新型的其他实施例中,每个所述保护基板20也可以为其他材料制成的基板,并且多个所述保护基板 20的数量可以依实际需求进行调整。As shown in FIG. 3 , in this embodiment, a plurality of the
需要说明的是,为方便理解与说明,以下将以两个所述保护基板20进行说明,但实际上多个所述保护基板20中的任意两个相邻的所述保护基板20 也能套用以两个所述保护基板20所做的说明,特此声明。It should be noted that, for the convenience of understanding and description, two
进一步地说,相邻的两个所述保护基板20之间定义有一预定位置(图3 未标),并且于本实施例中,对应于所述预定位置的每个所述保护基板20的表面上进一步设置有多个导电薄材21及未覆盖于多个所述导电薄材21的一绝缘材料(图未绘),但本实用新型不限于此。举例来说,于本实用新型的其他实施例中,所述保护基板20也可以是导电材料如铜金属,多个所述导电薄材21 也可以是通过蚀刻导电金属保护基板20后形成。Further, a predetermined position (not marked in FIG. 3 ) is defined between two adjacent
具体来说,如图3及图4所示,于本实施例中,每个所述保护基板20的外表面设置有四个所述导电薄材21,而每个所述保护基板20上的四个所述导电薄材21的分别被定义为:一第一外部导电薄材21AO、一第二外部导电薄材21CO、一内阳极导电薄材21AI、一内阴极导电薄材21CI。其中,上述四个导电薄材21AO、21CO、21AI、21CI于本实施例中较佳为铜制导体垫,并且多个所述导电薄材21的数量也可以依实际需求进行调整,本实用新型不限于此。Specifically, as shown in FIGS. 3 and 4 , in this embodiment, four conductive
更详细地说,所述第一外部导电薄材21AO及所述第二外部导电薄材 21CO设置于所述保护基板20的一上表面22,而所述内阳极导电薄材21AI 及所述内阴极导电薄材21CI设置于所述保护基板20的一下表面23。More specifically, the first outer conductive thin material 21AO and the second outer conductive thin material 21CO are disposed on an
多个所述保护基板20介绍至此,以下将开始介绍所述第一电容芯子10。如图3及图4所示,所述第一电容芯子10设置于相邻的任意两个所述保护基板20之间,并且所述第一电容芯子10包含一阳极11、一阴极12及位于所述阳极11与所述阴极12之间的一屏障涂层13,而所述阴极12的一部分能以所述导电连接材料50(如:银或铜膏)连接于每个所述保护基板20上的多个所述导电薄材。A plurality of the
进一步地说,所述第一电容芯子10设置于所述预定位置,并且所述绝缘胶材60(低黏度的环氧树脂材料)填满两个所述保护基板20及所述第一电容芯子10之间的空隙。其中,所述第一电容芯子10能与两个所述保护基板20 共同形成一夹层结构,并且所述第一电容芯子10也能与所述绝缘胶材60及两个所述保护基板20及共同形成一扁平体结构。Further, the
此外,如图3所示,所述导电连接材料50设置于所述阴极12的相反两侧,并且两个所述保护基板20的两个所述内阴极导电薄材21CI分别能设置于上述导电连接材料50上,并延伸地设置且切齐于所述第一电容芯子10的所述阴极 12的一端,进而使所述阴极12的一部分能通过所述导电连接材料50电性连接于所述内阴极导电薄材21CI。In addition, as shown in FIG. 3 , the conductive connecting
所述第一电容芯子10介绍至此,以下将开始介绍所述阳极端子30以及所述阴极端子40。如图3所示,所述阳极端子30位于所述扁平体结构的一端,并且所述阴极端子40位于所述扁平体结构位置远离所述阳极端子30的另一端,而所述阳极端子30及所述阴极端子40分别呈C字型。换句话说,所述阳极端子30以及所述阴极端子40分别位于多个所述保护基板20的共同且相互对应的两端。The
进一步地说,所述阳极端子30是以形成一导电膜的方式连接并形成于所述阳极11的一部分,并且所述阳极端子30于本实施例中为一铜导电膜且连接所述第一外部导电薄材21AO及所述内阳极导电薄材21AI,进而使所述阳极端子30能电性连接到所述阳极11;所述阴极端子40是以镀铜的方式连接并形成于所述第二外部导电薄材21CO及所述内阴极导电薄材21CI,进而使所述阴极端子40能电性连接到所述阴极12。Further, the
所述阳极端子30及所述阴极端子40介绍至此,以下将开始介绍所述外部阳极端子70以及所述外部阴极端子80。如图3及图5所示,扣除所述外部阳极端子70以及所述外部阴极端子80的所述电子组件封装结构100可被视为一绝缘体101,并且所述外部阳极端子70以及所述外部阴极端子80分别形成于所述阳极端子30以及所述阴极端子40相对远离所述第一电容芯子10的一侧,而所述外部阳极端子70以及所述外部阴极端子80还分别包裹于被视为所述绝缘体101的至少三个侧面。The
进一步地说,于本实施例中,所述外部阳极端子70以及所述外部阴极端子80能用来进一步增加所述阳极端子30或所述阴极端子40的金属厚度和强度,并且所述外部阳极端子70以及所述外部阴极端子80较佳为在所述阳极端子30以及所述阴极端子40上额外电镀所形成的铜金属层,但本实用新型不限于此。于本实用新型的其他实施例中,所述外部阳极端子70以及所述外部阴极端子80也可以由其他金属制成。Further, in this embodiment, the
需要说明的是,当所述第一电容芯子10的所述阳极11与所述阴极12分别连接到所述阳极端子30及所述阴极端子40并覆盖有无电解铜后,就可以再进一步镀上所述铜金属层以对应形成所述外部阳极端子70以及所述外部阴极端子80。此外,当额外电镀的所述铜金属层电镀完毕后,还可进一步镀上一锡金属层(图未绘)以保护所述铜金属层。It should be noted that, after the
需要补充说明的是,于本实施例中,所述内阳极导电薄材21AI也可以选择性地不被设置,但若设置有所述内阳极导电薄材21AI,其可有效帮助增加镀铜后的所述阳级端子30的黏附强度。It should be added that in this embodiment, the inner anode conductive thin material 21AI can also be selectively not provided, but if the inner anode conductive thin material 21AI is provided, it can effectively help increase the number of post-copper plating the adhesion strength of the
上述第一实施例对本实用新型的所述电子组件封装结构100描述,基本上是以片式铝固体电解电容器为例来说明。铝基固体电解电容器以铝为阳极,其氧化膜影响导电性造成向外连结导电端子的困难已如实用新型背景所述。故较佳的方法是采用锌置换法(zinc substitution或zincate treatment),先镀ㄧ层锌,再置换为镍,即可镀铜。方法详述于第二实施例中。但本实用新型不限于封装铝基固体电解电容芯子。举例来说,本实用新型的所述电子组件封装结构100 也可以用于钽电容器(或称钽电解电容器),而对应于上述第一实施例之工艺、电容器结构和中间装配结构也可以应用于其他类型的电子器件的封装。The above-mentioned first embodiment describes the electronic
钽电容芯子是采用多孔钽结构作为阳极,并在多孔钽结构的孔隙表面涂抹氧化锰作为导电电解质阴极,钽阳极结构向外链接则透过一钽丝,如图2C中 11T所示。外部端子与阳极钽丝的连通可以通过对钽丝的尖端表面11TC电镀或真空溅射沉积一层镍或铜的涂层,或者应用银胶粘剂来进行连接。另外,也可以先用焊接或压合方式将一小片镍或铜与阳极钽丝结合,然后外端子的铜可以直接电镀于此镍或铜片上。The tantalum capacitor core uses a porous tantalum structure as the anode, and smears manganese oxide on the surface of the pores of the porous tantalum structure as a conductive electrolyte cathode, and the tantalum anode structure is linked outward through a tantalum wire, as shown by 11T in Figure 2C. The communication between the external terminal and the anode tantalum wire can be made by 11TC electroplating or vacuum sputtering deposition of a nickel or copper coating on the tip surface of the tantalum wire, or by applying a silver adhesive. In addition, a small piece of nickel or copper can also be combined with the anode tantalum wire by welding or pressing, and then the copper of the outer terminal can be directly electroplated on this nickel or copper piece.
[第二实施例][Second Embodiment]
请参阅图6A至图6C所示,其为本实用新型的第二实施例,需先说明的是,本实施例类似于上述第一实施例,所以两个实施例的相同处则不再加以赘述(如:所述保护基板20);再者,本实施例对应附图所提及的相关数量与外形,仅用来具体地说明本实用新型的实施方式,以便于了解本实用新型的内容,而非用来局限本实用新型的保护范围。Please refer to FIG. 6A to FIG. 6C , which are the second embodiment of the present invention. It should be noted that this embodiment is similar to the above-mentioned first embodiment, so the similarities between the two embodiments are omitted. Repeated descriptions (eg: the protective substrate 20 ); furthermore, the relevant numbers and shapes mentioned in the accompanying drawings in this embodiment are only used to specifically describe the embodiments of the present invention, so as to facilitate understanding of the content of the present invention , rather than being used to limit the protection scope of the present invention.
需事先说明的是,为方便理解与说明,本实施例的图6A至图6C未如第一实施例的图3绘示有所述外部阳极端子70以及所述外部阴极端子80,但本实用新型不限于此。本实施例的所述电子组件封装结构100实际上仍包含有所述外部阳极端子70以及所述外部阴极端子80,特此说明。It should be noted in advance that, for the convenience of understanding and description, FIG. 6A to FIG. 6C of this embodiment do not show the
如图6C所示,本实施例相较于上述第一实施例,其主要差别在于详述所述阳极端子30(所述导电膜)进一步包含一锌层(图未绘)及一镍层31,所述锌层镀于所述阳极11的一尖端表面11A上,所述镍层31镀于所述锌层上,而所述第二外部导电薄材21CO及所述内阴极导电薄材21CI的一部分延伸并连接于所述阴极端子30。As shown in FIG. 6C , the main difference between this embodiment and the above-mentioned first embodiment is that the anode terminal 30 (the conductive film) further includes a zinc layer (not shown) and a
以下为进一步帮助理解与说明,将说明所述锌层及所述镍层31的详细形成过程。首先,如图6A所示,所述第一电容芯子10、多个所述保护基板20 以及所述绝缘胶材60共同形成一第一半成品组合体,并且所述第一半成品组合体的两端将分别被加工,以使其表面被平坦化,并使所述第一电容芯子10 的所述阳极11的所述尖端表面11A及多个所述保护基板20上的所述导电薄材21AO、21CO露出。The following describes the detailed formation process of the zinc layer and the
而后,如图6B所示,所述锌层通过锌取代反应(Zinc Substitution process) 先沉积于所述尖端表面11A,所述镍层31再通过无电镀镍轰击反应(Electroless NickelPlating Strike process)镀于所述锌层上。其中,当无电镀镍轰击反应进行时,不会将金属镍镀在属于非导电体的所述保护基板20的所述上表面22 及所述下表面23或所述绝缘胶材60上,也不会镀到属于铜垫的所述第一外部导电薄材21AO及所述第二外部导电薄材21CO上,因为铜对无电镀镍没有催化作用。Then, as shown in FIG. 6B , the zinc layer is first deposited on the
接着,如图6C所示,不导电的所述保护基板20的所述上表面22及所述下表面23将分别被电镀掩膜屏蔽,而后进行预处理(如:镀钯),最后进行化学镀铜,将无电镀铜覆盖于所述扁平体结构的两端及所述第一外部导电薄材 21AO及所述第二外部导电薄材21CO上。需要说明的是,当化学镀铜进行完毕后,镀上的铜金属将与所述镍层31形成良好的电性连接关系,并对应形成有包含所述锌层及所述镍层31的所述阳极端子30(所述导电膜)。Next, as shown in FIG. 6C , the
[第三实施例][Third Embodiment]
请参阅图7A至图7C所示,其为本实用新型的第三实施例,需先说明的是,本实施例类似于上述第一及第二实施例,所以多个实施例的相同处则不再加以赘述(如:所述保护基板20);再者,本实施例对应附图所提及的相关数量与外形,仅用来具体地说明本实用新型的实施方式,以便于了解本实用新型的内容,而非用来局限本实用新型的保护范围。Please refer to FIG. 7A to FIG. 7C , which are the third embodiment of the present invention. It should be noted that this embodiment is similar to the above-mentioned first and second embodiments. No further description (eg: the protective substrate 20) is repeated; furthermore, the relevant numbers and shapes mentioned in the accompanying drawings in this embodiment are only used to specifically describe the embodiments of the present utility model, so as to facilitate understanding of the present utility model. The content of the new model is not used to limit the protection scope of the present invention.
需事先说明的是,为方便理解与说明,本实施例的图7A至图7C未如第一实施例的图3绘示有所述外部阳极端子70以及所述外部阴极端子80,但本实用新型不限于此。本实施例的所述电子组件封装结构100实际上仍包含有所述外部阳极端子70以及所述外部阴极端子80,特此说明。It should be noted in advance that, for the convenience of understanding and description, FIG. 7A to FIG. 7C of this embodiment do not show the
如图7A至图7C所示,本实施例相较于上述第二实施例,其主要差别在于,所述电子组件封装结构100还可以进一步将所述导电连接材料50A设置于所述阳极11的相反侧的两侧面(也就是部分所述尖端表面11A)、多个所述保护基板20以及所述阳极端子30之间,以进一步连接上述三个组件并对应提高所述阳级端子30的黏附强度及所述电子组件封装结构100的结构强度。As shown in FIG. 7A to FIG. 7C , the main difference between this embodiment and the above-mentioned second embodiment is that the electronic
进一步地说,设置于所述阳极11的所述导电连接材料50A能用来将所述内阳极导电薄材21AI连接于所述阳极11,并且设置于所述阳极11的所述导电连接材料50A可以使用不同于连接所述阴极12与所述内阴极导电薄材21CI 的所述导电连接材料50的材料。Further, the
需要说明的是,通过“于所述阳极11设置有所述导电连接材料50A”的技术方案,所述导电连接材料50A能以其相对较大的结合面积和其接近所述阳极11的一端,增加所述阳极端子30的机械强度。It should be noted that, through the technical solution of "disposing the
由于本实施例相较于上述第二实施例的差别仅在于“所述导电连接材料 50A设置于所述阳极11的两个所述侧面”,其他组件或制造过程(如:所述锌层或所述镍层31的形成过程)皆相似,故于此不再赘述。Since the difference between this embodiment and the above-mentioned second embodiment is only that "the conductive connecting
[第四实施例][Fourth Embodiment]
请参阅图8所示,其为本实用新型的第四实施例,需先说明的是,本实施例类似于上述第一实施例,所以两个实施例的相同处则不再加以赘述(如:所述保护基板20);再者,本实施例对应附图所提及的相关数量与外形,仅用来具体地说明本实用新型的实施方式,以便于了解本实用新型的内容,而非用来局限本实用新型的保护范围。Please refer to FIG. 8 , which is the fourth embodiment of the present invention. It should be noted that this embodiment is similar to the above-mentioned first embodiment, so the similarities between the two embodiments will not be repeated here (such as : the protective substrate 20); furthermore, the relevant numbers and shapes mentioned in the accompanying drawings in this embodiment are only used to specifically describe the embodiments of the present invention, so as to facilitate understanding of the content of the present invention, rather than It is used to limit the protection scope of the present invention.
如图8所示,本实施例相较于上述第一实施例,其主要差别在于,所述电子组件封装结构100进一步包含一第二电容芯子10-2,并且于本实施例中,所述第二电容芯子10-2的具体结构大致与所述第一电容芯子10相同,但本实用新型不限于此。举例来说,于本实用新型的其他实施例中,所述第二电容芯子 10-2的具体结构也可以与所述第一电容芯子10不同。As shown in FIG. 8 , the main difference between this embodiment and the above-mentioned first embodiment is that the electronic
进一步地说,所述第二电容芯子10-2间隔地叠放设置于所述第一电容芯子10,并且所述第二电容芯子10-2位于两个所述保护基板20之间,而两个所述保护基板20、所述第一电容芯子10以及所述第二电容芯子10-2共同形成一多层芯子结构。其中,所述第一电容芯子10以及所述第二电容芯子10-2的两个所述阴极(图未标)连接于所述阴极端子40,并且所述第一电容芯子10以及所述第二电容芯子10-2的两个所述阳极(图未标)连接于所述阳极端子30。Further, the second capacitor cores 10 - 2 are stacked on the
需要说明的是,如图8所示,所述第一电容芯子10以及所述第二电容芯子10-2的两个所述阴极之间设置有所述导电连接材料50,而所述第一电容芯子10以及所述第二电容芯子10-2的两个所述阳极之间填充有所述绝缘胶材 60。It should be noted that, as shown in FIG. 8 , the
[第五实施例][Fifth Embodiment]
请参阅图9所示,其为本实用新型的第五实施例,需先说明的是,本实施例类似于上述第一实施例及上述第四实施例,所以多个实施例的相同处则不再加以赘述(如:所述保护基板20);再者,本实施例对应附图所提及的相关数量与外形,仅用来具体地说明本实用新型的实施方式,以便于了解本实用新型的内容,而非用来局限本实用新型的保护范围。Please refer to FIG. 9 , which is the fifth embodiment of the present invention. It should be noted that this embodiment is similar to the above-mentioned first embodiment and the above-mentioned fourth embodiment. No further description (eg: the protective substrate 20) is repeated; furthermore, the relevant numbers and shapes mentioned in the accompanying drawings in this embodiment are only used to specifically describe the embodiments of the present utility model, so as to facilitate understanding of the present utility model. The content of the new model is not used to limit the protection scope of the present invention.
如图9所示,本实施例相较于上述第一及第四实施例,其主要差别在于,所述电子组件封装结构100进一步包含一中层基板20-2,并且所述中层基板 20-2设置于所述第一电容芯子10以及所述第二电容芯子10-2之间,而所述中层基板20-2包含彼此相互分离的一阳极端导电薄材组及一阴极端导电薄材组。其中,所述阴极端导电薄材组以所述导电连接材料50连接于所述第一电容芯子10以及所述第二电容芯子10-2的两个所述阴极(图未标),而所述阳极端导电薄材组连接于所述阳极端子30。As shown in FIG. 9 , the main difference between this embodiment and the above-mentioned first and fourth embodiments is that the electronic
进一步地说,如图9所示,位于所述第一电容芯子10及所述第二电容芯子10-2之间的所述中层基板20-2,其表面上设置有的所述阴极端导电薄材组,其包含两个内阴极导电薄材20-2AM,并且两个所述内阴极导电薄材20-2AM 能通过所述导电连接材料50,电性连接于所述第一电容芯子10以及所述第二电容芯子10-2的两个所述阴极;位于所述第一电容芯子10及所述第二电容芯子10-2之间的所述中层基板20-2,其表面上设置所述阳极端导电薄材组,其包含两个内阳极导电薄材20-2BM,并且两个所述内阳极导电薄材20-2BM电性连接于所述第一电容芯子10以及所述第二电容芯子10-2的两个所述阳极 (图未标)及所述阳极端子30。Further, as shown in FIG. 9 , the middle-layer substrate 20 - 2 located between the
由此,通过“于所述第一电容芯子10及所述第二电容芯子10-2之间设置有一个所述中层基板20-2”的技术方案,有助于提高所述电子组件封装结构100 的结构强度。此外,位于所述第一电容芯子10及所述第二电容芯子10-2之间的所述中层基板20-2,其表面上设置的两个所述内阳极导电薄材20-2AM,其有助于加强所述第一电容芯子10以及所述第二电容芯子10-2的两个所述阳极的黏附力。Therefore, through the technical solution of "arranging the middle-layer substrate 20-2 between the
[第六实施例][Sixth Embodiment]
请参阅图10及图11所示,其为本实用新型的第六实施例,本实施例对应附图所提及的相关数量与外形,仅用来具体地说明本实用新型的实施方式,以便于了解本实用新型的内容,而非用来局限本实用新型的保护范围。Please refer to FIG. 10 and FIG. 11 , which are the sixth embodiment of the present invention. This embodiment corresponds to the relevant numbers and shapes mentioned in the drawings, and is only used to specifically describe the embodiments of the present invention, so that It is used to understand the content of the present invention, but not to limit the protection scope of the present invention.
如图10所示,本实施例相较于上述第一、第四及第五实施例,其主要差别在于,所述保护基板20为全导电体(例如铜基板,为方便可称为全铜基板),并且经由选择性蚀刻方式将全导体板蚀刻成导电垫,并且多个所述导电垫于本实施例中可被进一步定义为两个阳极导电垫20A以及两个阴极导电垫20B,而两个所述阳极导电垫20A以及两个所述阴极导电垫20B可以由薄铜片制成,但本实用新型不限于此。举例来说,于本实用新型的其他实施例中,多个所述导电垫的数量可依实际需求进行调整。As shown in FIG. 10 , the main difference between this embodiment and the above-mentioned first, fourth and fifth embodiments is that the
进一步地说,两个所述阳极导电垫20A以及两个所述阴极导电垫20B分别与所述外部阳极端子70以及所述外部阴极端子80电性连接,并且所述绝缘胶材60填充于所述第一电容芯子10、两个所述阳极导电垫20A以及两个所述阴极导电垫20B之间的空隙。其中,任意两个相邻的所述阳极导电垫20A以及所述阴极导电垫20B之间未有电性连接,并且藉由两个所述阳极导电垫20A 以及两个所述阴极导电垫20B的设置,本实用新型的所述电子组件封装结构 100的整体厚度将能被有效减少。Further, the two anode
需要说明的是,于本实施例中,每个所述阴极导电垫20B很大,其仅比所述阴极(图未标)小。由此,每个所述阴极导电垫20B就能替代所述保护基板20的主要部分,并且所述阴极能以相对较大的接触面积与每个所述阴极导电垫20B相连以提供低电阻抗。此外,所述阴极端子40或者所述外部阴极端子80于本实施例也可以仅覆盖每个所述阴极导电垫20B的一部分。It should be noted that, in this embodiment, each of the cathode
使用全导体保护基板的优点是减少封装的厚度。前述第一实施例中的绝缘保护基板外附导电薄材的实例可以典型的印刷电路板为例,其通常包含有一个为非导电材质的基板,并且其上下表面各覆盖有一铜箔层,而所述基板通常由玻璃纤维增强的环氧树脂制成,并且其厚度介于0.1毫米~0.2毫米之间,而所述铜箔层通常为1/2盎司或1盎司,其厚度相当介于0.018毫米~0.035毫米之间。因此,若使用典型的印刷电路板作为所述保护基板20,则两个所述保护基板20的总厚度约介于0.27毫米~0.54毫米之间。另一方面,如果只用厚0.1毫米的全铜基板,则2个全铜保护基板的总厚度可以减少到0.2毫米。如果只使用印刷电路板铜箔层所用的覆铜板当做全铜保护基板,则2个全铜保护基板的总厚度可以进一步减少到0.035毫米~0.07毫米之间。The advantage of using an all-conductor protective substrate is to reduce the thickness of the package. The example of the conductive thin material attached to the insulating protection substrate in the foregoing first embodiment can be a typical printed circuit board as an example, which usually includes a substrate made of non-conductive material, and its upper and lower surfaces are covered with a copper foil layer, and The substrate is usually made of glass fiber reinforced epoxy resin, and its thickness is between 0.1 mm and 0.2 mm, and the copper foil layer is usually 1/2 ounce or 1 ounce, and its thickness is equivalent to 0.018 mm to 0.035 mm. Therefore, if a typical printed circuit board is used as the
需要说明的是,如图9及图11所示,即使将多个所述保护基板20取代为全导体的多个所述导电垫,所述电子组件封装结构100仍能用来封装所述第一电容芯子10以及所述第二电容芯子10-2。其中,将图9与图11相比,其差别仅在于所述第一电容芯子10以及所述第二电容芯子10-2之间额外设置有一个所述阳极导电垫20A以及一个所述阴极导电垫20B。It should be noted that, as shown in FIG. 9 and FIG. 11 , even if a plurality of the
换句话说,将图11与上述第四实施例的图8相比,其差别仅在于原本位于所述第一电容芯子10以及所述第二电容芯子10-2之间的所述保护基板20 被替换为一个所述阳极导电垫20A以及一个所述阴极导电垫20B。In other words, comparing FIG. 11 with FIG. 8 of the fourth embodiment, the difference is only in the protection originally located between the
[第七实施例][Seventh Embodiment]
请参阅图12所示,其为本实用新型的第七实施例,需先说明的是,本实施例类似于上述第一实施例、上述第四实施例以及上述第五实施例,所以多个实施例的相同处则不再加以赘述(如:所述保护基板20);再者,本实施例对应附图所提及的相关数量与外形,仅用来具体地说明本实用新型的实施方式,以便于了解本实用新型的内容,而非用来局限本实用新型的保护范围。Please refer to FIG. 12 , which is the seventh embodiment of the present invention. It should be noted that this embodiment is similar to the above-mentioned first embodiment, the above-mentioned fourth embodiment and the above-mentioned fifth embodiment, so there are many The same parts of the embodiments will not be repeated (eg: the protective substrate 20 ); furthermore, the relevant numbers and shapes mentioned in the accompanying drawings in this embodiment are only used to specifically describe the embodiments of the present invention. , so as to facilitate understanding of the content of the present invention, rather than limit the protection scope of the present invention.
如图12所示,本实施例相较于上述第一实施例,其主要差别在于,位置邻近所述阳极端子30的多个所述保护基板20的多个端部进一步包含位于其上的一阳极侧导电薄材21AX,并且位置邻近所述阴极端子40的多个所述保护基板20的多个端部进一步包含位于其上的一阴极侧导电薄材21BX。As shown in FIG. 12 , the main difference between this embodiment and the first embodiment is that the ends of the
进一步地说,所述导电膜(所述阳极端子30)覆盖于所述阳极侧导电薄材21AX及位置邻近所述阳极端子30的所述扁平体结构的端面与侧面,并且所述阳极端子30包覆于所述扁平体结构的所述端面与所述侧面以对应形成五面包覆的所述阳极端子30,并增强所述电子组件封装结构100的结构强度;所述阴极端子40包覆所述阴极侧导电薄材21BX及位置邻近所述阴极端子40 的所述扁平体结构的端面与侧面,并增强所述电子组件封装结构100的结构强度。Further, the conductive film (the anode terminal 30 ) covers the anode-side conductive thin material 21AX and the end surface and side surface of the flat structure adjacent to the
[第八实施例][Eighth Embodiment]
请参阅图13至图18所示,其为本实用新型的第八实施例,需先说明的是,本实施例类似于上述第一至第七实施例,所以多个实施例的相同处则不再加以赘述(如:所述保护基板20);再者,本实施例对应附图所提及的相关数量与外形,仅用来具体地说明本实用新型的实施方式,以便于了解本实用新型的内容,而非用来局限本实用新型的保护范围。Please refer to FIG. 13 to FIG. 18 , which are the eighth embodiment of the present invention. It should be noted that this embodiment is similar to the above-mentioned first to seventh embodiments. No further description (eg: the protective substrate 20) is repeated; furthermore, the relevant numbers and shapes mentioned in the accompanying drawings in this embodiment are only used to specifically describe the embodiments of the present utility model, so as to facilitate understanding of the present utility model. The content of the new model is not used to limit the protection scope of the present invention.
如图13所示,本实用新型第八实施例提供一种电子组件封装结构的制造方法S100,其包括:第一提供步骤S101、设置步骤S102、第二提供步骤S103、叠合步骤S104、第一硬化步骤S105、填胶步骤S106、第二硬化步骤S107、切削步骤S108、成膜步骤S109以及切割步骤S110。其中,所述成膜步骤S109 还进一步包含一电镀子步骤及一连接符步骤,但本实用新型不限于此。举例来说,于本实用新型的其他实施例中,所述成膜步骤S109也可以不包含有所述电镀子步骤及所述连接符步骤。As shown in FIG. 13 , the eighth embodiment of the present invention provides a manufacturing method S100 of an electronic component packaging structure, which includes: a first providing step S101 , a setting step S102 , a second providing step S103 , a superimposing step S104 , and a first step S104 . A hardening step S105, a glue filling step S106, a second hardening step S107, a cutting step S108, a film forming step S109 and a cutting step S110. Wherein, the film forming step S109 further includes an electroplating sub-step and a connector step, but the present invention is not limited thereto. For example, in other embodiments of the present invention, the film forming step S109 may not include the electroplating sub-step and the connector step.
如图14A及图14B所示,于所述第一提供步骤S101中,一底部基板20C 被提供,并且所述底部基板20C的一上表面20C1定义有多个第一预定位置(图未标),而对应于多个所述第一预定位置的所述底部基板20C的所述上表面 20C1进一步设置有多个导电薄材21。其中,多个所述导电薄材21上涂布有一导电连接材料50,并且所述底部基板20C的结构与材质与本实用新型第一实施例所公开的所述保护基板20相同。As shown in FIGS. 14A and 14B , in the first providing step S101 , a
如图13、图14A及图14B所示,于所述设置步骤S102中,多个电子芯件(图未标)被放置于多个所述导电薄材21上的所述导电连接材料50上。其中,每个所述电子芯件包含一第一电容芯子10,并且所述第一电容芯子10包含一阳极11、一阴极12及一屏障涂层13。As shown in FIG. 13 , FIG. 14A and FIG. 14B , in the setting step S102 , a plurality of electronic core components (not shown) are placed on the conductive connecting
如图13、图14A及图14B所示,于所述第二提供步骤S103中,一顶部基板20D被提供,并且所述顶部基板20D的一下表面20D1定义有多个第二预定位置(图未标),而对应于多个所述第二预定位置的所述顶部基板20D的所述下表面20D1设置有多个所述导电薄材21,而多个所述导电薄材21上涂布有所述导电连接材料50。其中,所述顶部基板20D的结构与材质与本实用新型第一实施例所公开的所述保护基板20相同。As shown in FIG. 13 , FIG. 14A and FIG. 14B , in the second providing step S103 , a
需要说明的是,所述阴极12能用来配合所述导电连接材料50以与所述底部基板20C上的多个所述导电薄材21及所述顶部基板20D上的多个所述导电薄材21结合。It should be noted that the
如图13、图14A及图14B所示,于所述叠合步骤S104中,所述顶部基板20D被间隔地叠放设置于所述底部基板20C上,使多个所述电子芯件的所述第一电容芯子10位于所述顶部基板20D与所述底部基板20C之间。其中,所述底部基板20C的边缘超出所述顶部基板20D对其正投影所形成的一投影区域(图未标),并且超出所述投影区域的所述底部基板20C的部分所述上表面20C1定义为一置胶区域20CA。As shown in FIG. 13 , FIG. 14A and FIG. 14B , in the stacking step S104 , the
需要说明的是,于本实施例中,多个所述电子芯件的所述第一电容芯子 10是被设置于所述顶部基板20D与所述底部基板20C之间进行封装,但本实用新型不限于此。举例来说,于本实用新型的其他实施例中,多个所述电子芯件的所述第一电容芯子10也可以如第五实施例的图9或如图14A至图14B一般,被设置于两个以上的所述保护基板20之间以共同加工成多个所述电子芯件封装结构100。It should be noted that, in this embodiment, the
如图13、图14A及图14B所示,于所述第一硬化步骤S105中,所述导电连接材料50硬化,进而使所述顶部基板20D与所述底部基板20C及多个所述电子芯件的所述第一电容芯子10连接并对应形成一基本组合体。其中,所述基本组合体的内部空间形成有一通道(图未标),其连通于所述置胶区域 20CA。As shown in FIG. 13 , FIG. 14A and FIG. 14B , in the first curing step S105 , the
如图13、图14A及图14B所示,于所述填胶步骤S106中,一绝缘胶材 60自所述置胶区域20CA填满所述通道以对应将多个所述电子芯件的所述第一电容芯子10包埋于所述顶部基板20D与所述底部基板20C之间。其中,所述绝缘胶材60能通过毛细现象作用而填满所述通道。As shown in FIG. 13 , FIG. 14A and FIG. 14B , in the glue filling step S106 , an insulating
进一步地说,由于每个所述电子芯件的所述第一电容芯子10皆被夹设于所述顶部基板20D与所述底部基板20C之间,并被埋于其中。因此,传统的液体点胶封装不可能被应用封装夹设于所述顶部基板20D与所述底部基板 20C之间的多个所述电子芯件的所述第一电容芯子10,因为传统的液体点胶封装通常是在单个暴露的结构上进行。此外,若要采用复合成型或转移成型的封装方法也很困难,因为在这种情况下,液体必须通过所述顶部基板20D与所述底部基板20C之间的狭窄边缘开口挤进去,所以需要特殊的模具来进行密封以及加压。Further, since the
承上所述,为了将所述绝缘胶材60填充到所述顶部基板20D与所述底部基板20C之间的间隙(所述通道),首选方法是就毛细管填充。进一步地说,所述底部基板20C的面积需比所述顶部基板20D的面积大,进而使所述底部基板20C超出所述投影区域的部分所述上表面20C1被定义为所述置胶区域 20CA。As mentioned above, in order to fill the insulating
未固化的所述绝缘胶材60将通过毛细效应流入间隙(所述通道)。最好是在所述顶部基板20D与所述底部基板20C之间的一端注入液体,使未固化的所述绝缘胶材60从一端流向另一端。毛细管效应能够将液体拉入狭窄的缝隙中,以填满面积至少为100毫米×240毫米的夹层组件。这个过程可以在正常大气压下用简单的液体分配装置进行。The uncured insulating
如图13、图14A及图14B所示,于所述第二硬化步骤S107中,使所述绝缘胶材60被烘烤而硬化,进而使所述基本组合体与所述绝缘胶材60对应形成一第一半成品组合体。As shown in FIG. 13 , FIG. 14A and FIG. 14B , in the second curing step S107 , the insulating
如图13、图15A及图15B所示,于所述切削步骤S108中,所述第一半成品组合体被切削并对应开出多个槽孔开口105,使所述底部基板20C上的多个所述导电薄材21与所述顶部基板20D上的多个所述导电薄材21部分露出,并对应形成一第二半成品组合体。其中,所述阳极11的一部分能通过所述第二半成品组合体上的多个所述槽孔开口105而外露出所述尖端表面11A。As shown in FIG. 13 , FIG. 15A and FIG. 15B , in the cutting step S108 , the first semi-finished product assembly is cut and a plurality of
需要说明的是,如图18所示,于所述切削步骤S108中,还可以进一步多个所述槽孔开口105之外,切割额外的多个次槽孔开口105A,以暴露多个所述第一电容芯子10的多个所述阳极11及多个所述阴极12。由此,将能更加方便地对所述第二半成品组合体的所述顶部基板20D与所述底部基板20C 进行加工,方便进一步沉积金属以覆盖和包裹所述顶部基板20D与所述底部基板20C。It should be noted that, as shown in FIG. 18 , in the cutting step S108 , in addition to the plurality of
需额外说明的是,所述第二半成品组合体在本实用新型未绘示的其他实施例中,所述第二半成品组合体也可以是单独地应用(如:售卖)或是搭配其他构件使用。It should be additionally noted that, in other embodiments of the second semi-finished product assembly not shown in the present invention, the second semi-finished product assembly can also be used alone (eg, sold) or used with other components .
如图13所示,并参酌本实用新型第一实施例的图3以及本实用新型第二实施例的图6A至图6C,于所述成膜步骤S109中,所述第二半成品组合体上形成一导电膜并对应形成多个组件端子(如:本实用新型第一实施例的所述阳极端子30及所述阴极端子40),使所述第二半成品组合体与多个所述组件端子对应形成一第三半成品组合体。其中,多个组件端子连通于露出的多个所述导电薄材21。As shown in FIG. 13 , and referring to FIG. 3 of the first embodiment of the present invention and FIGS. 6A to 6C of the second embodiment of the present invention, in the film forming step S109 , the second semi-finished product assembly is A conductive film is formed and a plurality of component terminals (such as the
需要说明的是,于所述电镀子步骤中,金属锌被电镀于外露的所述阳极 11的部分表面并对应形成一锌层,而后金属镍被电镀于所述锌层并对应形成一镍层31。It should be noted that, in the electroplating sub-step, metal zinc is electroplated on the exposed partial surface of the
需要说明的是,于所述连接符步骤中,所述第一电容芯子10的所述阳极 11经由所述镍层31及所述导电膜连接于一阳极端子30,并将所述第一电容芯子10的所述阴极12经由多个所述导电薄材21连接于一阴极端子40。It should be noted that, in the connector step, the
如图13所示,于所述切割步骤S110中,所述第三半成品组合体被切割以对应形成多个电子组件封装结构100。As shown in FIG. 13 , in the cutting step S110 , the third semi-finished product assembly is cut to form a plurality of electronic
需要说明的是,于上述电子组件封装结构的制造方法S100中,所述电子组件封装结构100也可以如本实用新型的第六实施例的图10及图11,将所述顶部基板20D以及所述底部基板20C取代为全导体的多个导电垫。进一步地说,如图17A所示。首先,多个所述电子芯件的多个所述第一电容芯子10被放置在一上导体片20E及一下导体片20F之间,并通过所述导电连接材料50 粘合到导体片上,形成一个完整的夹层结构。然后,所述绝缘胶材60被填充到所述上导体片20E及所述下导体片20F之间的间隙中并固化。而后,如图 17B所示,所述上导体片20E的选定部分20E1及所述下导体片20F的选定部分20F1被蚀刻掉,所述上导体片20E及所述下导体片20F的剩余的部分形成单独的两个阳极导电垫20A和两个阴极导电垫20B。在此之后,如图17C所示,所述切削步骤S108将进行以开出多个所述槽孔开口105。It should be noted that, in the above-mentioned manufacturing method S100 of the electronic component packaging structure, the electronic
需要说明的是,以下为方便说明与理解,多个所述电子芯件将作为铝电容芯子进行数量生产的说明。举例来说,如图16所示,所述第二半成品组合体额外包含有所述中层基板20-2,并且于本实施例中,每个所述电子芯件的尺寸为7.4毫米×3.7毫米×0.25毫米,并且多个所述电子芯件并联在一起。其中,所述顶部基板20D以及所述底部基板20C的厚度皆为0.075毫米,上面覆盖着1盎司的铜箔,其厚度相当于0.035毫米。It should be noted that, for the convenience of description and understanding below, a plurality of the electronic core components will be used as aluminum capacitor cores to be produced in quantity. For example, as shown in FIG. 16 , the second semi-finished product assembly additionally includes the middle-layer substrate 20 - 2 , and in this embodiment, the size of each of the electronic core components is 7.4 mm×3.7 mm ×0.25 mm, and a plurality of the electronic core pieces are connected in parallel. The
所述顶部基板20D的尺寸为230毫米×110毫米;所述中层基板20-2的尺寸为230毫米×108毫米;所述底部基板20C的尺寸为240毫米×125毫米。由此,上述任意两个所述基板之间可以包含506个电容芯子。而后续的所述切割步骤S110中,多个所述电子组件封装结构100被切割分离出来,并且每个所述电子组件封装结构100的尺寸为7.3毫米×4.4毫米×1.1毫米厚。相比之下,如果使用传统的引线框架和复合成型包装,每个电子组件封装结构100 的尺寸将为7.3毫米×4.3毫米×1.9毫米,明显比本实用新型的产品要厚。The size of the
需要说明的是,以下为方便说明与理解,多个所述电子芯件将作为钽电容芯子进行数量生产的说明。举例来说,如图14B所示,所述第二半成品组合体仅包含有所述顶部基板20D以及所述底部基板20C,并且于本实施例,每个所述电子芯件的尺寸为7.0毫米×3.65毫米×1.0毫米,并且多个所述电子芯件并联在一起。其中,所述顶部基板20D以及所述底部基板20C的厚度皆为0.075毫米,上面覆盖着1盎司的铜箔,其厚度相当于0.035毫米。It should be noted that, for the convenience of description and understanding, a plurality of the electronic core components will be used as tantalum capacitor cores to be produced in quantity. For example, as shown in FIG. 14B , the second semi-finished product assembly only includes the
所述顶部基板20D的尺寸为230毫米×110毫米,所述底部基板20C的尺寸为240毫米×125毫米。由此,上述两个基板20D、20C之间可以包含506 个电容芯子。而后续的所述切割步骤S110中,多个所述电子组件封装结构100 被切割分离出来,并且每个所述电子组件封装结构100的尺寸为7.3毫米×4.4 毫米×1.5毫米厚。相比之下,如果使用传统的引线框架和复合成型包装,每个电子组件封装结构100的尺寸将为7.3毫米×4.3毫米×1.9毫米,明显比本实用新型的产品要厚。The size of the
[实施例的有益效果][Advantageous effects of the embodiment]
本实用新型的其中一有益效果在于,本实用新型所提供的所述电子组件封装结构100、其制造方法S100及所述半成品组合体,其能通过“所述绝缘胶材60填满多个所述保护基板20及所述第一电容芯子10之间的空隙”的技术方案,以获得低轮廓、低ESR和高可靠性的固体电解电容器。One of the beneficial effects of the present invention is that the electronic
以上所公开的内容仅为本实用新型的优选可行实施例,并非因此局限本实用新型的申请专利范围,所以凡是运用本实用新型说明书及图式内容所做的等效技术变化,均包含于本实用新型的申请专利范围内。The contents disclosed above are only preferred and feasible embodiments of the present invention, and are not intended to limit the scope of the patent application of the present invention. Therefore, any equivalent technical changes made by using the contents of the description and drawings of the present invention are included in the present invention. within the scope of the utility model patent application.
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