CN1967869B - Semiconductor device - Google Patents

Abstract

The present invention relates to a semiconductor device and its manufacturing method, which is to prevent thermal damage to a semiconductor device caused in a periphery region, and to obtain a high withstand voltage of the semiconductor device. The semiconductor device has a central region M in which a semiconductor switch element group is formed, and a periphery region N in which a guard ring 38group surrounding the central region M is formed. A body region 34 of the semiconductor switching element formed in an outermost periphery and a guard ring 38 formed in an innermost periphery are formed in an overlapped manner. Gate wiring 48 connected to a gate electrode 35 of the semiconductor switching element group is opposed to an overlapped region 39 between the body region 34 and the guardring 38 through an insulating layer 46. The width of the overlapping region 39 is not less than 1/3 of the depth of either the body region 34 or the guard ring 38 whichever is deeper.

Description

Semiconductor device

technical field

This application is a divisional application of the Chinese invention patent application with the filing date of September 1, 2004 and the application number of No. 200410074196.5. The present invention relates to a technique for increasing the withstand voltage of a semiconductor device. In particular, it relates to a technique related to a guard ring surrounding a central region where a group of semiconductor switching elements has been formed.

Background technique

For application in power control, a semiconductor device including a semiconductor switching element group having a MOS (Metal Oxide Semiconductor) structure or an IGBT (Insulated Gate Bipolar Transistor) structure is being developed. FIG. 12 illustrates a plan view of a semiconductor device including a semiconductor switching element group. In the figure, M is a central area, which is an area where semiconductor switching element groups have been formed. N in the figure is a peripheral area, which encloses the central area M and is located at the periphery of the semiconductor substrate 137 . In the peripheral region N, a guard ring group 138 is formed to surround the semiconductor switching element group. The guard ring group 138 is formed to increase the withstand voltage of the semiconductor device. In the central region M, gate electrode groups (not shown) for turning ON (conduction) the semiconductor switch element group are covered, and the gate wiring 148 connected to the gate electrode group extends across the peripheral region N. .

Fig. 13 is a sectional view taken along line XIII-XIII in Fig. 12 . This sectional view schematically shows the vicinity of the boundary between the central area M and the peripheral area N. As shown in FIG. In addition, generally speaking, more than a dozen guard rings in the peripheral area N are generally formed, but only three guard rings 138a, 138b, and 138c on the inner peripheral side are shown in FIG. a little.

FIG. 13 illustrates an example of a semiconductor device including a semiconductor switching element group having an IGBT structure. It is provided in order from the bottom: a collector electrode 120; a semiconductor substrate 122 of the first conductivity type (p ⁺ type in this example) connected to the collector electrode 120; The buffer layer 124 of the second conductivity type (n ⁺ type in this example); the drift layer 126 of the second conductivity type (n ^- type in this example) that has been stacked on the buffer layer 124; The body region 134 of the first conductivity type (p ^- type in this example) formed in the drift layer 126; the emitter of the second conductivity type (n ⁺ type in this example) formed in the body region 134 region 130; a body contact region 132 of the first conductivity type (p ⁺ type in this example) formed in the body region 134, and the body region 134 existing between the emitter region 130 and the drift layer 126 There is a gate electrode 135 opposite the insulating layer 136 ; an emitter electrode 144 contiguous to the emitter region 130 and the body contact region 132 .

The drift layer 126 extends toward the peripheral region N, and guard ring groups 138 a , 138 b , 138 c are formed in the drift layer 126 .

An emitter region 130, a body region 134, a drift layer 126, a buffer layer 124, and a gate electrode 135 facing the body region 134 existing between the emitter region 130 and the drift layer 126 with an insulating layer 136 interposed therebetween are constituted as The unit IGBT structure, the unit IGBT structure, is repeatedly repeated on the left side of the figure.

The guard ring groups 138a, 138b, and 138c alleviate the phenomenon that the equipotential lines are excessively concentrated on the gate insulating film 136 of the outermost semiconductor switching element, and the equipotential lines are made to cross the guard ring groups 138a, 138b, 138c and drift. The pn junction surface of layer 126 has a wide range. That is, the guard ring groups 138a, 138b, and 138c are designed so that the depletion layer is extended into the peripheral region N, and the withstand voltage is ensured by the widely-extended depletion layer without generating local electric field concentration.

In addition, when the semiconductor switching element is turned on, for example, when a high voltage such as a spike voltage is applied to the semiconductor device, as shown by the arrow in FIG. 13 , the remaining holes existing in the drift layer 126, After breaking down the depletion layer formed in the vicinity of the pn junction surface between the guard ring groups 138a, 138b, 138c and the drift layer 126, it flows into the guard ring groups 138a, 138b, 138c. The incoming holes are discharged from the innermost peripheral guard ring 138 a to the emitter electrode 144 via the body region 134 and the body contact region 132 . The remaining holes then flow through the adjacent guard rings.

The p ⁺ -type guard ring to be formed on the innermost circumference is formed at a position overlapping with the p ^- -type body region 134 of the semiconductor switching element already formed on the outermost circumference so that holes can be smoothly excluded. 138a. The gate wiring 148 faces the overlapping portion of the p ^- -type body region 134 of the outermost semiconductor switching element and the p ⁺ -type guard ring 138a of the innermost circumference with the insulating layer 146 interposed therebetween.

In such a semiconductor device, when a high voltage such as a spike voltage is applied to the semiconductor device, the semiconductor device generates heat in the peripheral region N, and the semiconductor device is often thermally destroyed.

Contents of the invention

An object of the present invention is to find out the cause of heat generation in the peripheral region N and provide a semiconductor device that does not cause thermal damage in the peripheral region.

The inventors of the present invention have studied in detail the phenomenon of heat generation in the peripheral region of a semiconductor device in which a semiconductor switching element group having a MOS structure or an IGBT structure is formed in the central region and a guard ring group is formed in the peripheral region. Finally, it was found that the part that generates the most intense heat is the overlapping region of the body region of the outermost semiconductor switching element and the innermost guard ring. It was also found that, among them, the heat generation is the most intense in the overlapping region where the insulating layer and the gate wiring are opposed to each other.

Then, when searching for the cause, it was found that in the cross-section of the overlapping region of the outermost body region and the innermost guard ring, there is a region where the depth is locally shallow, and the cross-sectional area through which holes cannot pass is reduced. an important factor. In addition, it was also found that when a voltage is applied to the gate wiring, an inversion layer is formed on the upper part of the region facing the gate wiring, and the cross-sectional area through which holes can pass is further reduced, which is another important factor. It has been confirmed that in an actual semiconductor device, since the gate wiring extends across the overlapping region of the outermost body region and the innermost guard ring, two important factors overlap in the overlapping region facing the gate wiring. produced, which would lead to severe fever.

The inventors of the present invention have succeeded in preventing semiconductor devices from being destroyed due to heat generation in the peripheral region due to the above-mentioned new findings.

The semiconductor device created in the present invention has a central region in which a semiconductor switching element group is formed, and a peripheral region in which a guard ring group surrounding the central region is formed. A body region having a semiconductor switching element formed on the outermost periphery is overlapped with a guard ring formed on the innermost periphery, and a gate wiring connected to a gate electrode of the semiconductor switching element group is formed with an insulating layer interposed therebetween. The body region and the repetitive region of the guard ring face each other.

A semiconductor device created in the present invention is characterized in that the width of the overlapping area of the body region and the guard ring (correctly refers to the exposed overlapping area measured from the central area toward the peripheral area) The width of the body region) is more than 1/3 of the depth of the deeper side within the depth of the body region and the depth of the guard ring.

In conventional semiconductor devices, the outermost body region and the innermost guard ring also overlap. However, in conventional semiconductor devices, the body region on the outermost periphery and the guard ring on the innermost periphery only need to be in contact, and since the need to make the overlap large on purpose has not been recognized, it is merely a case where there is a mask. Variations in die alignment also overlap to the extent that contact occurs.

At least it is not the case of overlapping them after recognizing that the formation of the inversion layer on the portion facing the gate wiring will reduce the cross-sectional area through which carriers pass.

Therefore, in the conventional semiconductor device, the repetition is insufficient, and the width of the overlapping region of the body region and the guard ring is not more than 1/3 of the depth of the depth of the body region and the depth of the guard ring, whichever is deeper. . Therefore, in the overlapping region facing the gate wiring, intense heat generation occurs due to the above-mentioned two important factors.

According to the studies of the present inventors, it has been confirmed that if the width of the overlapping region of the body region and the guard ring is set to 1/3 or more of the depth of the depth of the body region and the depth of the guard ring, then for The first important factor can be effectively dealt with, and even if the cross-sectional area of carriers is narrowed by the formation of an inversion layer in the region opposite to the gate wiring, it can be ensured between the body region and the guard ring. Sufficient carrier passing cross-sectional area can suppress intense heat generation.

The depth mentioned here refers to the diffusion depth, and refers to the distance from the surface of the semiconductor region to the depth at which the conductivity type is inverted.

The minimum depth of the overlapping region of the body region and the guard ring is preferably 1/2 or more of the depth of the body region.

If the overlapping region of the body region and the guard ring is taken as a cross-sectional view, there is locally a shallowed region between the body region and the guard ring. According to the studies of the inventors of the present invention, it has been confirmed that if the shallowest depth is ensured, that is, the minimum depth is at least 1/2 of the depth of the body region, the conduction path of the carriers can be sufficiently ensured, and severe heat generation can be suppressed. .

According to normal diffusion conditions, if the width of the overlapping region of the body region and the guard ring is made to be at least 1/3 of the depth of the depth of the body region and the depth of the guard ring, the depth of the body region can be ensured. 1/2 above the minimum depth.

In most cases, the ring side is deeper than the body area. When the guard ring is deeper than the body region, it is desirable that the width of the overlapping region of the body region and the guard ring be 2/3 or more of the depth of the body region and 1/3 or more of the depth of the guard ring

If the above conditions are satisfied, a conduction path for carriers can be ensured, and severe heat generation can be suppressed.

According to the present invention, it was found that it is important that the resistivity of the overlapping region immediately below the gate wiring be 20Ω·cm or less when the gate-on voltage is applied to the gate wiring.

When the upper gate conduction voltage is applied to the gate wiring, an inversion layer will be formed on the upper part of the repeated region of the body region and the guard ring (the region opposite to the gate wiring), and the resistance of the repeated region will increase. Even in the state after the resistance is increased, if the condition of suppressing the resistivity of the overlapping region of the body region and the guard ring to 20Ω·cm or less is satisfied, the conduction path of the carriers can be sufficiently ensured, and the violent resistance can be suppressed. fever.

According to the present invention, it is possible to provide various other methods for securing a conduction path of carriers in the overlapping region directly under the gate wiring.

A semiconductor device created in the present invention is characterized in that: In the upper part of the region including the overlapping region of the body region and the guard ring opposite to the gate wiring, a high-density layer containing the same conductive layer as the body region and the guard ring is formed. Types of layers of impurities.

This high-concentration layer functions as a layer that suppresses or prohibits inversion in the vicinity of the body region and the surface of the guard ring (portion facing the gate wiring). Since the voltage of the gate wiring suppresses or prohibits the formation of an inversion layer near the surface of the body region and the guard ring, it is possible to suppress the occurrence of a phenomenon in which the conduction path of carriers is narrowed. The high-concentration layer is preferably formed on a region facing the gate wiring and also including a region where the body region and the guard ring overlap.

In addition, since the inversion near the surface of the body region and the guard ring can be suppressed or prohibited by using this high-concentration layer, the restriction on the overlapping range of the body region and the guard ring can be relaxed. In this case, even if the width of the overlapping region is less than 1/3 of the depth of the deeper one of the body region and the guard ring, a sufficient conduction path for carriers can be ensured and severe heat generation can be suppressed.

A semiconductor device created in the present invention is characterized in that: In the upper part of the region including the overlapping region of the body region and the guard ring opposite to the gate wiring, a layer having a conductivity type different from that of the body region and the guard ring is formed. layers of impurities.

The impurity layer of the opposite conductivity type can be evaluated as an inversion layer. Therefore, even if a voltage is applied to the gate wiring, the inversion layer can be restricted from extending all the way below it. Therefore, it is only necessary to form an impurity layer of the opposite conductivity type in advance. The voltage due to the gate wiring can limit the formation of an inversion layer near the surface of the body region and guard ring beyond what is conceived. Therefore, it is possible to suppress the occurrence of a narrowing of the conduction path of carriers. The impurity layer of opposite conductivity type is ideally opposed to the gate wiring, and is formed on a region including a region where the body region and the guard ring overlap.

In addition, using the impurity layer of the opposite conductivity type can limit the inversion beyond the assumption in the vicinity of the surface of the body region and the guard ring, so that the restriction on the overlapping range of the body region and the guard ring can be relaxed. Even if the width of the overlapping region is less than 1/3 of the deeper depth of the body region and the guard ring, a sufficient conduction path for carriers can be ensured, and severe heat generation can be suppressed.

When the present invention is applied to a semiconductor device having a semiconductor switching element having a structure capable of discharging a large amount of carriers, particularly useful results will be achieved. The semiconductor switching element included in the semiconductor device has: a collector electrode; a semiconductor substrate of the first conductivity type connected to the collector electrode; a drift layer of the second conductivity type laminated on the semiconductor substrate; A body region of the first conductivity type formed in the drift layer; an emitter region of the second conductivity type formed in the body region; an insulating layer interposed therebetween and a body existing between the emitter region and the drift layer The gate electrode facing the region; the emitter electrode contiguous to the emitter region. It is characterized in that the drift layer extends toward the peripheral region, and a guard ring group of the first conductivity type is formed in the drift layer. In addition, if necessary, a high-concentration buffer layer of the second conductivity type may be formed between the semiconductor substrate and the drift layer. The IGBT structure provided with this buffer layer is generally called a PT (Punch Through) type.

In the semiconductor device described above, a semiconductor switching element using an IGBT structure discharges a large amount of carriers to the outermost body region when a high voltage is applied. With any of the above-mentioned structures, since a wide discharge path can be ensured between the innermost guard ring and the outermost body region, destruction of the semiconductor device due to heat generated in the peripheral region can be suppressed.

The present invention, in addition, leads to a new method of manufacturing semiconductor devices with high withstand voltage. In this method, impurity ions are implanted and diffused at a depth shallower than the implantation depth at the time of forming the body region and guard ring in the upper part of the semiconductor region in the region facing the gate wiring while repeating the body region and the guard ring. process.

If the above steps are carried out, it is possible to manufacture a semiconductor device in which an inversion prevention layer or an inversion confinement layer near the surface of the body region and the guard ring that prohibits or confines inversion can be formed, so that heat generation does not cause damage in the peripheral region. .

According to the semiconductor device of the present invention, it is possible to suppress the occurrence of thermal destruction of the semiconductor device due to heat generation in the peripheral region, and to increase the withstand voltage of the semiconductor device.

Description of drawings

Fig. 1 shows a perspective view of main parts of Embodiment 1 of the present invention.

FIG. 2 shows the relationship between the overlap ratio and the resistivity of the parasitic MOS.

FIG. 3 shows the manufacturing process (1) of Embodiment 1 of the present invention.

FIG. 4 shows the manufacturing process (2) of Embodiment 1 of the present invention.

FIG. 5 shows the manufacturing process (3) of Embodiment 1 of the present invention.

Fig. 6 is a perspective view of main parts of Embodiment 2 of the present invention.

FIG. 7 shows the manufacturing process (1) of Embodiment 2 of the present invention.

FIG. 8 shows a manufacturing process (2) of Embodiment 2 of the present invention.

FIG. 9 shows the manufacturing process (3) of Embodiment 2 of the present invention.

FIG. 10 shows the manufacturing process (4) of Embodiment 2 of the present invention.

Fig. 11 is a perspective view of main parts of Embodiment 3 of the present invention.

FIG. 12 shows a plan view of a conventional semiconductor device.

FIG. 13 is a cross-sectional view of main parts of a conventional semiconductor device.

Detailed ways

The main features of the embodiments described below are listed below.

(Form 1) is a semiconductor device having a central region in which a semiconductor switching element group has been formed, and a peripheral region in which a guard ring group surrounding the central region has been formed, characterized in that:

Each semiconductor switching element has: a collector electrode; a semiconductor substrate of the first conductivity type connected to the collector electrode; a buffer layer of the second conductivity type stacked on the semiconductor substrate; A drift layer of the second conductivity type stacked on the layer; a body region of the first conductivity type formed in the drift layer; an emitter region of the second conductivity type formed in the body region; A body contact region of the first conductivity type; a gate electrode facing the body region existing between the emitter region and the drift layer with an insulating layer in between; an emitter electrode connected to the emitter region and the body contact region ,

The above-mentioned drift layer extends towards the peripheral region,

a set of guard rings of the first conductivity type formed in the drift layer,

The body region of the semiconductor switching element formed on the outermost periphery and the guard ring formed on the innermost periphery are overlapped and formed,

The gate wiring connected to the gate electrode of the semiconductor switching element group faces the overlapping region of the body region and the guard ring with an insulating layer interposed therebetween.

(Aspect 2) is the semiconductor device of Aspect 1, characterized in that the width of the overlapping region of the body region and the guard ring is 1/3 or more of the depth of the deeper one of the body region and the guard ring.

(Aspect 3) is the semiconductor device of Aspect 1, characterized in that the minimum depth of the overlapping region of the body region and the guard ring is 1/2 or more of the depth of the body region.

(Aspect 4) is the semiconductor device of Aspect 1, wherein the width of the overlapping region of the body region and the guard ring is 2/3 or more of the depth of the body region.

(Aspect 5) is the semiconductor device of Aspect 1, characterized in that the resistivity of the overlapping region of the body region and the guard ring immediately below the gate wiring is 20Ω·cm or less when an upper gate-on voltage is applied to the gate wiring.

(Aspect 6) is the semiconductor device of Aspect 1, characterized in that: on the upper part of the region including the overlapping region of the body region and the guard ring facing the gate wiring, a layer containing the same conductive layer as that of the body region and the guard ring is formed at a high concentration. Types of layers of impurities.

(Aspect 7) is the semiconductor device of Aspect 1, characterized in that an impurity containing a conductivity type different from that of the body region and the guard ring is formed in an upper part of a region including an overlapping region of the body region and the guard ring facing the gate wiring. layer.

Example

Hereinafter, various embodiments will be described with reference to FIGS. 1 to 11 .

(Embodiment 1) The semiconductor device of Embodiment 1 has a central region in which a semiconductor switching element group having an IGBT structure is formed, and a peripheral region in which a guard ring group surrounding the central region is formed.

FIG. 1 schematically shows the vicinity of an overlapping region (referred to as an overlapping region) of the IGBT 33 located on the outermost periphery of the central region M and the innermost peripheral guard ring 38 formed in the peripheral region N from an oblique perspective.

The IGBT33 as a unit is equipped with: a collector electrode 20 made of alumina is formed on the back surface; a semiconductor substrate 22 of the first conductivity type (p ⁺ type in this example) connected to the collector electrode 20; A buffer layer 24 of the second conductivity type (n ⁺ type in this example) layered on the semiconductor substrate 22; a second conductivity type (n ⁻ type in this example) that has been stacked on the buffer layer 24 type) drift layer 26; the body region 34 of the first conductivity type (p ^- type in this example) formed in the drift layer 26; the second conductivity type (in this example) formed in the body region 34 The emitter region 30 of the n ⁺ type in this example); the body contact region 32 of the first conductivity type (p ⁺ type in this example) formed in the body region 34, and the emitter region 30 and the drift In the middle of the body region 34 a between the layers 26 there is a gate electrode 35 facing the insulating layer 36 ; an emitter electrode connected to the emitter region 30 and the body contact region 32 . Although not shown, the emitter electrode is electrically connected to the emitter region 30 and the body contact region 32 by using the notched portion of the gate electrode 35 shown in FIG.

The drift layer 26 extends toward the peripheral region N, and a guard ring 38 of the first conductivity type (p ⁺ type in this example) is formed in the drift layer 26 extending to the peripheral region N. The body region 34 of the IGBT 33 formed on the outermost periphery in the central region M and the guard ring 38 formed on the innermost periphery of the peripheral region N are formed to overlap. This overlapping portion is called an overlapping region 39 .

The gate wiring 48 connected to the gate electrode 35 of the IGBT 33 faces the overlapping region 39 of the outermost body region 34 and the innermost guard ring 38 with the insulating layer 46 interposed therebetween (as shown in FIG. 12 ). The planar structure of the prior art is similar, please refer to Fig. 12 for this point). The body region 34 has been doped with boron, the impurity concentration is typically 1×10 ¹⁵ to 1×10 ¹⁸ cm ^-3 , and the thickness in the depth direction is 3 to 6 microns. In addition, the impurity concentration of the body region 34 of Example 1 was 1×10 ¹⁸ cm ⁻³ , and the depth thereof was set to 6 μm.

FIG. 1 exemplifies a type in which switching is performed using a planar gate electrode 35 . However, it may also be a trench gate type. The gate electrode 35 can be formed of metal or polysilicon.

When the semiconductor device is drawn in a top view, a plurality of guard rings are formed in the peripheral area N, and Fig. 1 only shows the innermost p ⁺ type guard for convenience. Ring 38. The guard ring 38 is doped with boron, its impurity concentration is typically 1×10 ¹⁶ to 1×10 ²⁰ cm ^-3 , and its thickness in the depth direction is 4 to 8 microns. In addition, the impurity concentration of the guard ring 38 of Example 1 was 4×10 ¹⁸ cm ⁻³ , and its depth was set to 8 μm. On guard ring 38 , gate wiring 48 is arranged with insulating layer 46 interposed therebetween, and gate wiring 48 is connected to gate electrode 35 . In Embodiment 1, no area division is drawn between the gate electrode 35 and the gate wiring 48 . In a plan view, the gate electrode 35 and the gate wiring 48 can be clearly distinguished.

As shown in FIG. 1 , the outermost body region 34 and the innermost guard ring 38 overlap each other. The contours of the body region 34 and the innermost protective ring 38 are shown by phantom lines in the repetition region 39 . The overlapping region 39 refers to a region where both the impurities forming the body region 34 and the impurities forming the guard ring 38 exist, and refers to a region located between two imaginary lines. According to studies by the inventors of the present invention, it has been found that it is important to optimally design the overlapping region 39 in order to improve the breakdown voltage of the semiconductor device.

The width of the overlapping region 39 refers to the width V of the overlapping region 39 to be exposed on the surface 41 of the semiconductor region. In other words, it refers to the distance between two imaginary lines shown in FIG. 1 exposed on the surface 41 of the semiconductor region. The direction of the width V is evaluated so that it coincides with the direction going from the central region M toward the peripheral region N. Note that the minimum depth W of the overlapping region 39 refers to the distance from the surface 41 of the semiconductor region to the position where the outline of the body region 34 intersects the outline of the guard ring 38 .

In the semiconductor device of Embodiment 1, the guard ring 38 is formed deeper than the body region 34 . The depth of guard ring 38 is indicated as X in FIG. 1 .

In the semiconductor device of the first embodiment, the width V of the surface 41 of the semiconductor region of the overlapping region 39 is formed to be 1/3 or more of the depth X of the guard ring 38 .

FIG. 2 shows the measurement results of the resistivity of the overlapping region 39 immediately below the gate wiring 48 when the width V of the overlapping region 39 of the body region 34 and the guard ring 38 is changed in the semiconductor device of the first embodiment. Here, the resistivity is measured in a state where a gate-on voltage is applied to the gate wiring 48 . 2 is a value obtained by dividing the width V of the overlapping region 39 by the depth X of the guard ring (defined as an overlapping ratio in this specification). The vertical axis of FIG. 2 is the resistivity of the overlapping region 39 . This resistivity is a value measured by forming a pair of electrodes on the outer peripheral end of the body contact region 32 and the guard ring 38 and applying a predetermined voltage between the pair of electrodes. In this case, since the resistivity between a pair of electrodes is mainly composed of the resistivity of the overlapping region 39 , the resistivity between a pair of electrodes can be evaluated as the resistivity of the overlapping region 39 .

As shown in FIG. 2 , it can be known that the larger the overlapping ratio is, the lower the resistivity of the overlapping region 39 is. In addition, the dotted line shown in FIG. 2 is a critical point where thermal destruction occurs in the semiconductor device. In the case where the resistivity of the repeating region 39 is higher than the dotted line, thermal damage occurs in the semiconductor device. If the resistivity of the overlapping region 39 measured in the state where the upper gate-on voltage is applied to the gate wiring 48 is 20 Ω·cm or less, no thermal damage will occur in the semiconductor device. It can be seen from Fig. 2 that if the overlap ratio of 1/3 or more is ensured, the resistivity can be made below 20Ω·cm. This is considered to be because even if the passage cross-sectional area of holes is narrowed due to the formation of an inversion layer on the region facing the gate wiring 48, if the overlapping ratio of 1/3 or more is ensured, the body region 34 and the protective layer can be formed. A sufficient cross-sectional area for passage of holes is ensured between the rings 38, so that the resistivity can be made 20Ω·cm or less.

A method of forming the overlapping region 39 in the semiconductor device will be described with reference to FIGS. 3 to 5 .

FIG. 3 shows a cross section of a semiconductor region in a manufacturing process. This cross section shows a state where a p ⁺ -type guard ring 38 is formed on an upper portion of an n ⁻ -type drift layer 26 , and an oxide film 50 is formed on the surfaces of the guard ring 38 and the drift layer 23 . The illustrated guard ring 38 is the innermost guard ring 38 . In addition, it can be formed by a general epitaxial growth method, an ion implantation method, or other manufacturing methods, and the manufacturing techniques used in conventional manufacturing steps are not particularly limited.

Next, as shown in FIG. 4, a resist film 52 is formed by coating, and openings are formed at predetermined positions to be patterned. Next, boron is ion-implanted from this opening. The amount or depth of boron to be implanted is determined in accordance with the diffusion characteristics based on heat treatment. For example, when the ion to be used is boron, its diffusion characteristics are about 0.8 times the diffusion distance in the lateral direction relative to the diffusion distance in the longitudinal direction. Considering this situation, ion implantation is performed to form a diffusion distance in a desired region.

Next, as shown in FIG. 5, heat treatment is performed to diffuse the ion-implanted boron. The diffused boron enters the body region 34 to form the repeat region 39 . The overlapping region 39 is mainly formed by diffusing the implanted boron in the lateral direction.

In addition, in such a semiconductor device, generally speaking, the guard ring 38 is formed deeper than the body region 34 . Therefore, when the body region 34 is diffused to overlap the guard ring 38 , the minimum depth W of the overlapping region 39 increases as the width V of the surface of the overlapping region 39 increases. If the body region 34 is diffused until the width V of the surface of the repeat region 39 becomes 1/3 or more of the depth X of the guard ring 38, the minimum depth W of the repeat region 39 will often become the body region. 1/2 or more of the depth Y of 34. In addition, the width V of the surface of the overlapping region 39 is often equal to or greater than 2/3 of the depth of the body region 34 . In this case, the resistivity of the overlapping region 39 becomes 20 Ω·cm or less, and thermal damage does not occur in the semiconductor device.

(Embodiment 2) FIG. 6 schematically shows a perspective view of main parts of a semiconductor device according to Embodiment 2. As shown in FIG. Embodiment 2 is characterized in that in the upper part of the region including the overlapping region 39 between the body region 34 formed on the outermost semiconductor switching element in the central region M and the innermost guard ring 38 in the peripheral region N, A high-concentration layer 60 containing impurities of the same conductivity type as that of the body region 34 and the guard ring 38 is provided.

In such a conventional semiconductor device (in the case of not having the high-concentration layer 60 ), there is a gap opposite to the gate wiring 35 corresponding to the gate-on voltage to be applied to the gate electrode 35 . The problem of forming an inversion layer on the repeating region 39 of the body region 34 and the guard ring 38 . Especially when a high gate-on voltage has been applied, since holes supplied from the drain layer 22 on the side of the peripheral region N to be discharged to the body contact region 32 through the repetition region 39 will increase, in the repetition region The width of the inversion layer formed on 39 also becomes wider corresponding to the high gate conduction voltage, so the conduction path of holes in the overlapping region 39 becomes narrower. For this reason, in the conventional semiconductor device of this type, a phenomenon that excessive concentration of holes occurs in the overlapping region 39 remarkably occurs, and the semiconductor device is damaged.

In the semiconductor device of Example 2, layer 60 having the same conductivity type as body region 34 and guard ring 38 and having a high impurity concentration is formed corresponding to the region where the inversion layer is to be formed immediately under gate wiring 48 . Thanks to this layer 60, the formation of an inversion layer on this region can be suppressed or inhibited even when a high gate-on voltage has been applied. Since the formation of the inversion layer is suppressed or prohibited, the conduction path of the holes can be fully ensured, and the element damage caused by the excessive concentration of the holes can be reduced.

In addition, there are no particular limitations on the position or shape where the high-concentration layer 60 is formed, as long as it is formed at least at a position including the upper portion of the overlapping region 39 . As long as it is formed at least at this position, the formation of an inversion layer that causes thermal damage can be suppressed or inhibited.

In addition, using the high-concentration layer 60 suppresses or prohibits inversion near the surface of the body region 34 and the guard ring 38 , thereby relaxing restrictions on the overlapping range of the body region 34 and the guard ring 38 . Therefore, when using the high-concentration layer 60 , a sufficient conduction path for carriers can be ensured and severe heat generation can be suppressed even without consideration of constraints such as the width of the overlapping region 39 .

A method of manufacturing the semiconductor device of the second embodiment will be described with reference to FIGS. 7 to 9 .

FIG. 7 shows a cross section of the semiconductor region in the manufacturing process. This section shows that a p ⁺ -type body region 34 and a p ⁺ -type guard ring 38 are formed on the top of the n ^- -type drift layer 26, an oxide film 50 is formed on the surface, and then on the oxide film 50 The state after the polysilicon film 47 is laminated. In addition, the guard ring 38 is the innermost guard ring 38 . In addition, it can be formed by a general epitaxial growth method, an ion implantation method, or other manufacturing methods, and the manufacturing technology used in the conventional manufacturing process is not particularly limited.

First, as shown in FIG. 7, a gate wiring is formed by doping impurities into the polysilicon film 47 to lower its resistance. As the impurity used at this time, phosphorus can be typically used. Phosphorus has a high diffusion coefficient and is difficult to diffuse outward, so it can be uniformly diffused into polysilicon. Therefore, in the case where the gate electrode in the central region is of a trench type, phosphorus can be satisfactorily used in the case where it is desired to diffuse impurities all the way to a deep region. As shown in FIG. 8, polysilicon 47 can be changed into gate wiring 48 by a usual ion implantation method.

Next, as shown in FIG. 9, a resist film 54 is formed by coating, and openings are formed at predetermined positions to be patterned. Next, boron is ion-implanted into the opening.

Next, as shown in FIG. 10, heat treatment is performed to thermally diffuse the implanted boron. This makes it possible to form the high-concentration layer 60 at a desired position.

It is particularly effective to suppress or inhibit the formation of an inversion layer directly under the gate wiring 48 if the high-concentration layer 60 is formed by the above-mentioned manufacturing method.

As shown in FIG. 7, in the step of reducing the resistance of the polysilicon 47, ions are implanted into the polysilicon with phosphorus. A portion of the implanted phosphorous is implanted over polysilicon 47 into body region 34 or guard ring 38 below it. In the conventional semiconductor device, since the manufacturing is finished at this stage, only a small amount of phosphorus (n-type impurity) remains only on the surface portion of the body region 34 or the guard ring 38 . Therefore, when an upper gate-on voltage is applied to the gate wiring 48, an inversion layer is likely to be formed directly under the gate wiring 48, resulting in a phenomenon in which the conduction path of holes is narrowed.

However, if the manufacturing method of the present invention is adopted, a small amount of phosphorus (n-type impurity) remaining in the body region 34 or the guard ring 38 is due to the fact that boron implanted during the formation of the p+-type layer 60 with a high impurity concentration is substantially carried out. Conversely injected and disappeared. Therefore, since it is difficult to form an inversion layer in the region corresponding to the high-concentration layer 60, the conduction path of holes can be sufficiently ensured, so that a high breakdown voltage semiconductor device can be obtained.

(Embodiment 3) FIG. 11 schematically shows a perspective view of main parts of a semiconductor device according to Embodiment 3. As shown in FIG.

Embodiment 3 is characterized in that the body region 34 and the body region 34 and The guard ring 38 is a highly concentrated layer 62 of a different conductivity type.

As in the semiconductor device of the third embodiment, a layer 62 of a conductivity type different from that of the body region 34 and the guard ring 38 and having a high impurity concentration is formed corresponding to the region where the inversion layer immediately below the gate wiring 48 is to be formed. , forming a conduction path for electrons. In the case of limiting the conduction path of electrons and applying a high gate conduction voltage to the gate wiring 48 , the formed inversion layer can be restricted from extending below the high-concentration layer 62 . Therefore, the conduction path of holes is not narrowed. Since the conduction path of the holes can be sufficiently ensured, it is possible to reduce element damage caused by excessive concentration of holes.

In addition, there are no particular limitations on the position or shape where the high-concentration layer 62 is formed, as long as it is formed at least at a position including the upper portion of the overlapping region 39 . As long as it is formed at least at this position, the formation of an inversion layer that causes thermal damage can be suppressed or inhibited.

In addition, using the high-concentration layer 62 suppresses or prohibits inversion near the surface of the body region 34 and the guard ring 38 , thereby relaxing restrictions on the overlapping range of the body region 34 and the guard ring 38 . Therefore, when the high-concentration layer 69 is used, a sufficient conduction path for carriers can be ensured and intense heat generation can be suppressed even without considering constraints such as the width of the overlapping region 39 .

In the above embodiments, the IGBT semiconductor element is described, but the same effects can be obtained for other elements (thyristor, bipolar transistor, power MOS) and the like.

Although specific examples of the present invention have been described in detail above, these specific examples are merely illustrations and do not limit the scope of the technical solutions. Various modifications and changes of the specific examples illustrated above are included in the technologies described within the scope of the claims.

In addition, the technical elements described in this specification or drawings can exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the technical claims at the time of application. In addition, the techniques exemplified in this specification or drawings may be those that simultaneously achieve a plurality of purposes, or those that are technically useful in achieving one of the purposes itself. technology.

Claims (2)

1. A semiconductor device having a central area forming a semiconductor switching element group and a peripheral area forming a guard ring group surrounding the central area, characterized in that: The body region of the semiconductor switching element formed on the outermost periphery of the central region overlaps with the guard ring formed on the innermost periphery of the peripheral region, The gate wiring connected to the gate electrode of the semiconductor switching element group faces an overlapping region of the body region and the guard ring with an insulating layer interposed therebetween, The resistivity of the overlapping region directly under the gate wiring when an upper gate-on voltage is applied to the gate wiring is 20Ω·cm or less. 2. The semiconductor device according to claim 1, characterized in that: The above-mentioned semiconductor switching element has: a collector electrode; a semiconductor substrate of the first conductivity type connected to the collector electrode; a drift layer of the second conductivity type laminated on the semiconductor substrate; a body region of the first conductivity type; an emitter region of the second conductivity type formed in the body region; and a gate facing the body region existing between the emitter region and the drift layer with an insulating layer interposed therebetween. electrode; the emitter electrode connected to the emitter region, said drift layer extends towards the peripheral region, A guard ring group of the first conductivity type is formed in the drift layer.

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