Embodiment
Relevant characteristics and implementation of the present invention cooperate graphicly to be described in detail as follows as most preferred embodiment now.
Consult Fig. 2 A to Fig. 2 D, be the manufacturing process profile of a preferred embodiment of the multilayer circuit board of built-in passive assembly of the present invention.
Shown in Fig. 2 A, conductive foil 11 at first is provided, have at least one pair of metal salient point 15 in a surperficial 17a (first surface), in order to engage with a passive block.
Above-mentioned conductive foil 11 with at least one pair of metal salient point 15 can be bought from manufacturer, or utilize for example be the Patternized technique of lithography technology with a conductive foil patterning to form this metal salient point 15 on a surface of conductive foil.
Conductive foil 11 materials are copper, silver, aluminium, palladium or silver-colored palladium, are good with Copper Foil.
Shown in Fig. 2 B, a passive block 13 to be gone up corresponding metal salient point 15 with conductive foil 11 1 surperficial 17a (first surface) engage, its juncture for example utilizes hot pressing.In the process of hot pressing, the accuracy of aligning must good control.
Above-mentioned passive block 13 can be capacitor, resistor or inductor.
Shown in Fig. 2 C, core board 19, first organic insulator and the second organic insulator 21a, 21b are arranged, comprise the first conductive foil 11a of passive block 13, and the second conductive foil 11b that comprises passive block or do not comprise passive block is arranged.
The first organic insulator 21a and the second organic insulator 21b are pressed on the both sides of core board simultaneously, again one first conductive foil 11a and one second conductive foil 11b are pressed on the first organic insulator 21a and the second organic insulator 21b simultaneously.Perhaps, with the first organic insulator 21a, the first conductive foil 11a, second organic insulator reaches the both sides that the second conductive foil 11b places core board 18 respectively, carries out pressing more simultaneously.Certainly, also can a pressing first organic insulator 21a, the first conductive foil 11a is in a side of core board, and other lamina of not pressing of opposite side and conductive foil.
The one side that wherein comprises passive block 13 on conductive foil 11a, the 11b contacts with organic insulator.
Organic insulator 21a, 21b can be preimpregnation material (prepreg) or are coated on the aqueous resin on core board 19 surfaces.
Core board 19 can be had a metallic circuit of double-side patternization or for simple patternless core board, can be double-layer circuit board or multilayer circuit board.Can be made up of insulation organic material or ceramic material, for example by epoxy resin, poly-ethanamide, two maleic acid vinegar imines/three nitrogen trap resins, or its glass is formed from the composite material of fiber.For example can be existing FR-4 substrate.This type FR-4 substrate for example is made up of epoxy resin, glass fabric and electro copper foil.Certainly, core board 19 is not limited to only be made up of single organic material, also can be made up of the different insulative material layer.
And above-mentioned superimposed process is to realize by heat-press step, and in superimposed process, the accuracy of aligning must good control.
Therefore, shown in Fig. 2 D, the multilayer circuit board 23 of demonstration behind superimposed program lamination from top to bottom comprises the first conductive foil 11a, the first organic insulator 21a, core board 19, the second organic insulator 21b, second conductive foil 11b with passive block 13 or the second conductive foil 11b with passive block 13 in regular turn.
Shown in Fig. 3 A and Fig. 3 B, an embodiment of the multilayer circuit board circuit forming surface pattern behind the demonstration lamination.
As shown in Figure 3A, run through the first conductive foil 11a and the second conductive foil 11b, form and at least always to bore a hole 25,, be able to by these through holes 25 to be electrically conducted each other to provide follow-up when on the first conductive foil 11a, the second conductive foil 11b, forming circuit.
Then, form metal level 27 so that the hole conducting, another surface (second surface) of the first conductive foil 11a and second another surface of conductive foil 11b (second surface) forms metal level 27a, 27b respectively so that follow-up formation circuit pattern in hole wall.
Metal level 27 can comprise copper.
Form metal level 27, for example form the method for copper metal layer, can utilize physical vapor deposition (PVD), chemical vapor deposition (CVD), electro-coppering, electroless copper, sputter (sputtering), evaporation (evaporation), electric arc steam deposition (arc vapor deposition), ion beam sputter (ion beamsputtering), the molten deposition (laser ablation deposition) of loosing of laser, electricity slurry to promote methods such as chemical vapour deposition (CVD) (PECVD) or organometallic chemical vapour deposition (CVD) to form.
It is preferable for utilizing the electroless plating mode earlier, utilizes plating mode to form metal level again.
Shown in Fig. 3 B, metal level 27a, the 27b of patterning upper and lower surface and conductive foil 11a, 11b are to form circuit pattern 29a, 29b respectively.
Above-mentioned patterning upper and lower surface metal level 27 can utilize existing technology of electroplating through hole with the method that forms 29a, 29b respectively, for example comprises subraction (subtractive), and subraction for example utilizes the panel method.
Though in Fig. 3 B, be presented at up and down and all form circuit pattern on the conductive foil, in fact still can only on a conductive foil wherein, form circuit pattern.
In addition, if the core board 19 in the multilayer circuit board behind the lamination has the circuit pattern of upper and lower surface, or it wherein a surface has circuit pattern up and down, also can form the external circuit pattern that electrically connects with the core board circuit pattern in superficies in another way, shown in Fig. 4 A to Fig. 4 B, another embodiment of the multilayer circuit board circuit forming surface pattern behind the demonstration lamination.
Shown in Fig. 4 A, the first conductive foil 11a, the first organic insulator 21a, the second conductive foil 11b and the second organic insulator 21b that run through upper and lower surface respectively, form at least one blind hole 31a, 31b to expose the circuit 20 that is covered in the core board 19 under organic insulator 21a, the 21b, and provide follow-up when on conductive foil, forming circuit, be able to by these blind holes 31a, 31b to be electrically conducted the circuit 20 of the core board 19 under organic insulator 21a, the 21b.
Then, form the first metal layer 27a, the second metal level 27b respectively in the upper and lower surface of multilayer circuit board 23, wherein the first metal layer 27a cover this first conductive foil 11a and blind hole 31a inwall in case with core board 19 upper surface circuit 20a hole conductings, the second metal level 27b cover this second conductive foil 11b and lower surface blind hole 31b inwall in case with the lower surface circuit 20b hole conducting of core board 19.
The first metal layer or second metal level can comprise copper.
Form metal level, the method that for example forms copper metal layer can utilize physical vapor deposition (PVD), chemical vapor deposition (CVD), electro-coppering, electroless copper, sputter (sputtering), evaporation (evaporation), electric arc steam deposition (arc vapor deposition), ion beam sputter (ion beam sputtering), the molten deposition (laser ablation deposition) of loosing of laser, electricity slurry to promote methods such as chemical vapour deposition (CVD) (PECVD) or organometallic chemical vapour deposition (CVD) to form.
It is preferable for utilizing the electroless plating mode earlier, utilizes plating mode to form copper metal layer again.
Shown in Fig. 4 B, the patterning the first metal layer 27a and the second metal level 27b and conductive foil 11a, 11b are to form circuit pattern 29a, the 29b that electrically connects with core board 19 upper and lower surface circuit 20a, 20b respectively.
Multilayer circuit board behind above-mentioned this lamination also can comprise the buried via hole 39 (figure does not show its access path) that electrically connects with blind hole.
Though displaing core plate upper and lower surface all has circuit pattern in Fig. 4 B, but in fact core board can only have circuit pattern in a surface wherein, certainly, though in Fig. 4 B, show up and down all to form circuit pattern on the conductive foil, in fact still can be only wherein form circuit pattern on the conductive foil in corresponding core board circuit pattern.
In addition, if the core board 19 in the multilayer circuit board among Fig. 4 A and Fig. 4 B behind the lamination has the circuit pattern of upper and lower surface, or it wherein a surface has circuit pattern up and down, also can outside the technology of above-mentioned through hole, cooperate the technology of Fig. 3 A to Fig. 3 B to form blind hole again, to see through the external circuit pattern that this blind hole and core board circuit pattern electrically connect in the follow-up formation of superficies, as shown in Figure 5, another embodiment of the multilayer circuit board circuit forming surface pattern behind the demonstration lamination.
Comprehensive the above, the manufacture method of the multilayer circuit board of a kind of built-in passive assembly of the present invention, because of having metal salient point on the conductive foil, passive block can directly utilize hot press on metal salient point, so need not consider the printing size issue of passive block, reduced and formed the process complexity of passive block, and then reached simplification technology, and improved the purpose of electrical accuracy.
Therefore, the manufacture method of the multilayer circuit board of a kind of built-in passive assembly of the present invention, need not worry resistance or electric capacity technological ability, with and form back and original discrepant problem of design load, and the manufacture method that provides the user to be applied to the multilayer circuit board of different process ability can effectively be simplified its technology and its manufacturing cost.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.