JP2007123940A - Substrate in which capacitor is built and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To build a capacitor of large capacitance and high reliability in a substrate with high mass productivity. <P>SOLUTION: A method of manufacturing the substrate in which the capacitor is built includes a step of forming a first conductor pattern 12 for one of the electrodes of the capacitor on a substrate 11 for pattern transfer, a step of transferring the first conductor pattern so as to embed itself into an insulating member 13 to form a first substrate member, a step of forming a second conductor pattern 22 for the other of the electrodes of the capacitor on a substrate for pattern transfer, a step of transferring the second conductor pattern so as to embed itself into an insulating member 23 to form a second substrate member, a step of arranging a dielectric layer 14a on the surface of the embedded side of the conductor pattern of either the first or the second substrate member, and a step of pressing the first and the second substrate members to integrate them together. The dielectric layer is formed by vacuum-laminating dielectric sheets formed by mixing a filler into a resin. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a substrate with a built-in capacitor and a method for manufacturing the same, and more particularly to a technique for manufacturing a large-capacity and highly reliable built-in capacitor with high productivity.

  As electronic devices such as mobile phones and notebook PCs become smaller, thinner, multifunctional, and more advanced, printed wiring boards used for these devices become multilayered, and functions such as capacitors, inductors, and resistors are built into the board. Various substrate structures with built-in elements have been proposed.

  For example, a large-capacity capacitor has conventionally been often mounted as a surface-mounted component on the surface of a substrate. However, due to the recent demand for high-density mounting, mounting inside the substrate is desired. In order to make such a substrate built-in type capacitor, generally, a lower electrode 2 is first formed on a substrate 1 as shown in FIG. 6 (FIG. 6A), and a resin-coated copper foil 3 is laminated thereon. After that, the upper electrode 3a was formed by selectively removing the copper foil 3a on the surface of the copper foil with resin by wet etching.

  Moreover, there is the following patent document that discloses a method of manufacturing a multilayer substrate using such a copper foil with resin.

JP-A-11-266080

JP 2001-177241 A

  However, the conventional method for forming a substrate built-in capacitor has the following problems, and it has been difficult to form a thin, large-capacity and highly reliable capacitor in the substrate.

  First, in the above method using the copper foil with resin, the etching solution tends to remain on the substrate because the upper electrode is formed by the etching method, which may reduce the reliability of the substrate. In addition, the copper foil with resin has a thin insulating layer formed by roughening (unevening) at least one surface of the copper foil and forming a resin layer on this surface in order to ensure adhesion with the resin. Attempting to do so will increase capacity tolerances and reduce reliability. This is because the thinner the insulating layer (resin layer), the more the influence of the unevenness of the copper foil becomes more negligible, the insulating layer thickness varies, and the withstand voltage decreases due to electric field concentration on the convex part. . For this reason, it has been difficult to form a large-capacity and highly reliable capacitor by a conventional method using a copper foil with resin.

  Furthermore, there is a problem that the copper constituting the electrode diffuses into the resin layer to cause migration, resulting in IR failure. In particular, when the resin layer is thinned to increase the capacity of the capacitor, insulation deterioration and short circuit are likely to occur. Also in this respect, it is not easy to increase the capacity of the capacitor and to ensure its quality and reliability.

  On the other hand, none of the above-mentioned patent documents suggests a method for solving the problem in producing such an in-substrate capacitor.

  Therefore, an object of the present invention is to produce a thin, large-capacity and highly reliable capacitor inside a substrate with high productivity.

  In order to achieve the object and solve the problem, a method of manufacturing a capacitor-embedded substrate according to the present invention includes a step of forming a first conductor pattern serving as one electrode of a capacitor on the surface of a transfer substrate, A step of transferring the first conductor pattern so as to be embedded in an insulating material to form a first substrate constituent material, and a step of forming a second conductor pattern serving as the other electrode of the capacitor on the surface of the transfer substrate; A step of transferring the second conductor pattern so as to be embedded in an insulating material to create a second substrate constituent material, and one of the first substrate constituent material and the second substrate constituent material A step of disposing a dielectric layer on the surface of the conductive pattern embedded side, and the first substrate constituent material so as to sandwich the dielectric layer between the first conductive pattern and the second conductive pattern Press the second substrate component and press However, thereby a step of forming a capacitor.

  Here, embedding means that one surface of the conductor pattern (the surface in contact with the transfer substrate) is substantially flush with the surface of the insulating material that is the transfer destination (the surface of the insulating material and one surface of the conductor pattern). Means that the conductor pattern is reduced in the insulating material (so that they are substantially in the same plane). In the first substrate manufacturing method of the present invention, an electrode pattern is formed in such a buried state using a transfer method, and a dielectric layer is formed on a flat surface. Therefore, a very thin dielectric layer is used. Even if it exists, it becomes possible to arrange this between the electrodes with high accuracy.

In order to form the dielectric layer, it is desirable to use a dielectric sheet formed by mixing a filler with resin. This is because the use of such a composite material makes it possible to form a large-capacity capacitor having a dielectric layer having a high dielectric constant. The step of forming a dielectric layer using such a dielectric sheet is preferably performed by laminating the sheet under vacuum. This is because the adhesion between the dielectric sheet, the insulating material, and the conductor pattern is enhanced, and air between them is eliminated to suppress generation of voids. Therefore, it is desirable that the degree of vacuum in the step of performing the vacuum lamination is higher (a reduced pressure state with a lower atmospheric pressure), but since the effect of suppressing the generation of voids can be obtained even if it is not a complete vacuum, the vacuum according to the present invention is Includes a reduced pressure state of 1 × 10 ⁴ Pa or less.

  The first substrate with built-in capacitor according to the present invention includes a first conductor pattern embedded in the first insulating layer, the first conductor pattern disposed so as to face the first conductor pattern, and the first insulating layer. Comprises a second conductor pattern embedded in another second insulating layer and a dielectric layer disposed between the first insulating layer and the second insulating layer in the substrate.

  According to the structure of the substrate with a built-in capacitor of the present invention, a thin, large-capacity and highly reliable capacitor can be formed inside the substrate, as in the above-described substrate manufacturing method.

  In the substrate, the first conductor pattern may be formed by being transferred to the first insulating layer, and the second conductor pattern may be formed by being transferred to the second insulating layer.

  A second capacitor-embedded substrate according to the present invention includes a first conductor pattern embedded on one surface side of a dielectric layer, and the other conductor layer disposed so as to face the first conductor pattern. A second conductor pattern embedded on the surface side of the first conductor pattern, between the first conductor pattern and the dielectric layer, and between the second conductor pattern and the dielectric layer. A layer is formed.

  By forming the barrier layer, the metal of the conductor pattern can be ionized and diffused in the dielectric layer, and the occurrence of migration can be prevented, and the reliability of the substrate can be improved. In particular, even when the dielectric layer is formed thin in order to form a large-capacitance capacitor, insulation deterioration and short circuit accidents are unlikely to occur, and the reliability of the substrate can be improved in this respect.

  Furthermore, an electronic component according to the present invention is one in which one or more surface-mounted components are mounted on any of the above-described capacitors-embedded substrates.

  According to the present invention, a thin, large-capacity, and highly reliable capacitor can be formed in a substrate with high productivity. Other objects, features, and advantages of the present invention will become apparent from the following description of embodiments and examples of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3 of the accompanying drawings. In the drawings, the same reference numerals denote the same or corresponding parts.

  First Embodiment FIGS. 1A to 1B are process diagrams showing a method for manufacturing a capacitor built-in substrate according to a first embodiment of the present invention. As shown in the figure, in this manufacturing method, first, a conductor pattern 12 to be one electrode of a capacitor is formed on a transfer substrate 11 ((a) in the figure). As the transfer substrate 11, for example, a SUS plate can be used, and the conductor pattern 12 is formed on this surface by, for example, a pattern plating method.

  The conductor pattern 12 is pressed against the insulating material 13 (FIG. 5B), and the transfer substrate 11 is peeled off so that the conductive pattern 12 is embedded in the insulating material 13 (FIG. 5C). )). As the insulating material 13, for example, a prepreg in which a glass cloth is impregnated with a vinyl benzyl ether compound resin (VB) can be used. The vinyl benzyl ether resin has good peelability from the SUS plate, and the yield is improved by using such a resin prepreg.

  Similarly, as shown in FIG. 1B, a conductor pattern 22 to be the other electrode of the capacitor is formed on the transfer substrate 21 (FIG. 1A1), and this conductor pattern 22 is buried by the above transfer method. It transfers to another insulating material 23 (the figure (b1)).

  Then, a dielectric layer 14a is formed on the surface of one of the insulating materials 13 and 23 onto which the electrode conductors 12 and 22 are transferred. The dielectric layer 14a is formed by vacuum laminating the sheet material 14 supporting the dielectric material 14a on the carrier film 14b (FIG. 1A (d)) and peeling the carrier film 14b (FIG. 1 (e)). . By laminating under vacuum, the adhesion between the dielectric layer 14a, the electrode conductor 12 and the insulating layer 13 can be improved, and air between them can be eliminated to prevent the generation of voids.

  As the sheet material 14 for forming the dielectric layer 14a, for example, a sheet material in which a B-stage resin layer is formed and integrated on one surface of a PET film can be used. As the dielectric material 14a, a composite material in which an inorganic filler (a high dielectric constant material powder) is appropriately mixed in a vinyl benzyl ether compound resin (VB) to improve the dielectric constant can be used.

  After the carrier film 14b is peeled off, the other insulating material 23 to which the electrode conductor 22 is transferred is overlaid on the insulating material 13 with the conductor buried surface facing the dielectric layer 14a and the electrodes 12, 22 aligned with each other. A capacitor is formed by pressing and integrating these (figure (f), (g)). In this process, it is desirable to perform pressing under vacuum in order to prevent the generation of voids. Thereafter, it is possible to form a multilayer substrate with a built-in capacitor by appropriately laminating a substrate material using a known method, for example, a prepreg as an adhesive sheet.

  Second Embodiment FIGS. 2A to 2C are process diagrams showing a method for manufacturing a capacitor built-in substrate according to a second embodiment of the present invention. As shown in the figure, in this manufacturing method, first, a conductor pattern 32 to be one electrode of a capacitor is formed on a transfer substrate 31 (for example, a SUS plate) by, for example, a pattern plating method ((a) in the figure). Barrier layer 33 is provided so as to cover 32 ((b) in the figure). The reason why the barrier layer 33 is provided is to prevent the metal constituting the conductor pattern 32 (capacitor electrode) from diffusing into the dielectric layer 34a to be formed in a later step and causing an insulation failure.

  The barrier layer 33 can be formed using a thin film method such as sputtering or vapor deposition. As a material for forming the barrier layer, for example, Ti, TiN, Ta, TaN, Cr, Ni, W, Mo, or the like can be used. Further, as shown in FIG. 2B, a conductor pattern 42 to be the other electrode of the capacitor is formed on the transfer substrate 41 in the same manner as in FIGS. 2A (a) to 2 (b) (FIG. 2 (a1)). In order to prevent metal diffusion into the dielectric layer, a barrier layer 43 is also provided on the conductor pattern 42 ((a2) in the figure).

  After the formation of the barrier layer 33, a dielectric layer 34a is formed thereon. The method of forming the dielectric layer 34a is the same as that described in the first embodiment, and a sheet in which a dielectric material 34a (for example, a composite material in which a filler is mixed in vinyl benzyl ether) is supported on a carrier film 34b. The material 34 may be laminated in a vacuum (FIG. 2A (c)), and the carrier film 34b is peeled off (FIG. 2 (d)).

  Then, the two conductor patterns 32 and 42 including the barrier layers 33 and 43 formed on the transfer substrates 31 and 41 are arranged so as to face each other (FIG. 2C (e)), and both the transfer substrates 31 and 41 are positioned. Then, the other conductor pattern 42 is pressed and integrated with the dielectric layer 34a to form a capacitor (FIG. (F)).

  Thereafter, both transfer substrates 31 and 41 are peeled off (FIG. (G)), and the barrier layers 33a and 43a remaining in the region other than the electrode arrangement region are removed (FIG. (H)). The extra barrier layers 33a and 43a may be removed by, for example, dry etching. Thereafter, as in the first embodiment, for example, a substrate material is appropriately laminated by using a prepreg as an adhesive sheet to form a multilayer substrate with a built-in capacitor.

  3RD EMBODIMENT FIG. 3: is process drawing which shows the manufacturing method of the board | substrate with a built-in capacitor concerning 3rd embodiment of this invention. As shown in the figure, this manufacturing method is similar to the second embodiment (FIGS. 2A (a) to 2C (f)), and the conductor pattern 52 (one electrode of the capacitor) covered with the barrier layer 53 is used. ) And a dielectric layer 54a formed on the surface, and a transfer substrate 61 formed on the surface with a conductor pattern 62 constituting the other electrode of the capacitor together with the barrier layer 63 to form a capacitor. (FIG. 3A).

  Thereafter, in this embodiment, only one transfer substrate 61 is peeled off (FIG. 3B), and the dielectric layer 54a including the capacitor is supported on the other transfer substrate 51. This is to facilitate the subsequent substrate lamination process. In particular, when the dielectric layer 54a is formed very thin in order to form a large-capacity capacitor, the mechanical strength of the dielectric layer 54a is lowered, and the handling becomes difficult. On the other hand, according to the method of this embodiment, since the dielectric layer 54a is supported by the transfer substrate 51, the handling becomes easy and the productivity can be improved. Therefore, the thickness of the transfer substrate is preferably 20 μm or more, more preferably 50 μm or more. The material is preferably metal, stainless steel is most preferable in consideration of rigidity and peelability at the time of transfer. For plating pattern formation on the transfer substrate, the pattern plating method is most preferable in consideration of mass productivity and accuracy. In this case, if a conductive material is used for the transfer substrate, a seed layer (underlying conductor layer) is formed. This is preferable because the process can be omitted.

  After peeling off one of the transfer substrates 61, the excess barrier layer 63a is removed in the same manner as in the second embodiment ((c) in the figure), and an adhesive sheet 71 (for example, vinyl benzyl ether on glass cloth) is formed thereon. The substrate 72 is pressed and laminated with a prepreg impregnated with a compound resin interposed therebetween ((d) in the figure). Thereafter, the other transfer substrate 51 is peeled off (FIG. 5E), and the excess barrier layer 53a is removed (FIG. 5F).

  Examples of the present invention will be described below.

  A capacitor was prepared as follows based on the method according to the first embodiment (hereinafter referred to as Example 1).

A SUS304TA material having a thickness of 0.1 mm was used as the transfer substrates 11 and 21, and electrodes (conductor patterns 12 and 22) were formed on the SUS plate by a pattern plating method. The size of the electrode is 3 mm in length, 4 mm in width, and 20 μm in thickness. For the insulating layers 13 and 23, a glass cloth prepreg made of vinylbenzyl ether compound resin having a thickness of 150 μm was used. In order to form the dielectric layer 14a, a PET film 14 supporting a composite material in which a dielectric powder composed of BaO, TiO ₂ and Nd ₂ O ₃ is mixed with a vinyl benzyl ether compound resin (VB) is used. Was laminated on the insulating material 13 with a vacuum laminator. The thickness of the PET film 14 is 50 μm. Further, the amount of dielectric powder mixed in the composite material is 40 vol% of dielectric powder with respect to VB resin in volume percent. As the film thickness of the dielectric layer 14a, two types of 10 μm and 20 μm were prepared.

  On the other hand, as a comparative control, a PET film 14 (dielectric material 14a) that had been high-pressure laminated without vacuum lamination and a low-pressure laminate were prepared. In the high pressure laminate, the pressure between the rubber rollers of the laminator is set higher than usual, and in the low pressure laminate, the pressure between the rubber rollers is set low. For the control examples relating to these high-pressure and low-pressure laminates, two types of dielectric layers 14a having a film thickness of 10 μm and 20 μm were prepared.

  After the PET film was peeled, each peeled surface (the surface of the dielectric layer 14a) from which the PET film 14 was peeled was observed with a microscope for the substrate of Example 1, the substrate formed by the high pressure laminate, and the substrate formed by the low pressure laminate. . As a result, it was observed that many large voids of several tens of μm were generated in the high pressure laminate. In addition, small voids were found in the low-pressure laminate. On the other hand, no void was observed in the substrate of Example 1 which was vacuum-laminated. When laminating under normal pressure in this way, pinholes are more likely to occur in the dielectric layer as the high pressure laminating is performed, and this also causes a decrease in breakdown voltage.

  Moreover, the test which measures the proof pressure (insulation withstand voltage) of these capacitors, and the moisture-proof load test were done. In the moisture resistance load test, a voltage of 10 V was applied to the capacitor in an environment of a temperature of 85 ° C. and a humidity of 85%. The test results are as shown in FIGS. 4A to 4C and FIGS. 5A to 5B, respectively. In these figures, the above-mentioned high-pressure laminate is “transfer 1”, the low-pressure laminate is “transfer 2”, the vacuum-laminated example 1 is “vacuum laminate”, and a barrier layer is provided and vacuum-laminated. Example 2 (which will be described later) is shown as “vacuum laminate + barrier metal”.

  As is apparent from FIGS. 4A to 4C, it can be seen that the vacuum-laminated capacitor of Example 1 (FIG. 4C) has little variation in both the 10 μm film thickness and the 20 μm film thickness, and good pressure resistance can be obtained. Further, as apparent from FIGS. 5A to 5B showing the results of the moisture resistance load test, in the capacitor created by the method of Example 1 and Example 2 described later, the proportion of non-defective products does not decrease even after a long time has passed. It can be seen that poor insulation hardly occurs.

  Based on the method according to the second embodiment, a capacitor built-in substrate was prepared as follows (referred to as Example 2).

A SUS304TA material having a thickness of 0.1 mm was used as the transfer substrates 31 and 41, and electrode patterns 32 and 42 having a thickness of 2 μm were formed on the SUS plate by copper pyrophosphate plating. The size of the electrode is the same as in Example 1. Barrier layers 33 and 43 made of titanium were formed to a thickness of 0.1 μm by sputtering. The dielectric layer 34a was formed by vacuum lamination using the same composite material as in Example 1. Removal of excess barrier metals (barrier layers) 33a and 43a (FIGS. 2C (g) to (h)) was performed by dry etching with CF ₄ . The results of the moisture resistance load test are as described based on FIGS.

  Although the embodiments and examples of the present invention have been described above, the present invention is not limited to these embodiments, and it will be apparent to those skilled in the art that various modifications can be made within the scope of the claims. it is obvious.

(A) to (g) are cross-sectional views sequentially showing steps of the method of manufacturing the capacitor built-in substrate according to the first embodiment of the present invention. (A1) to (b1) are cross-sectional views sequentially showing steps of the method of manufacturing the capacitor built-in substrate according to the first embodiment of the present invention. (A) to (d) are cross-sectional views sequentially showing steps of a method of manufacturing a capacitor built-in substrate according to the second embodiment of the present invention. (A1) to (b1) are cross-sectional views sequentially showing steps of a method for manufacturing a capacitor built-in substrate according to the second embodiment of the present invention. (E) to (h) are cross-sectional views sequentially showing steps of a method for manufacturing a capacitor built-in substrate according to the second embodiment of the present invention. (A) to (f) are cross-sectional views sequentially showing steps of a method of manufacturing a capacitor built-in substrate according to the third embodiment of the present invention. It is a diagram which shows the pressure | voltage resistant test result of the capacitor | condenser which concerns on the comparative example which carried out the high voltage | pressure lamination, (a) is a case where the film thickness of a dielectric material layer is 10 micrometers, (b) is a case where it is 20 micrometers. It is a diagram which shows the pressure | voltage resistant test result of the capacitor | condenser concerning the comparative example which carried out the low voltage | pressure lamination, (a) is a case where the film thickness of a dielectric material layer is 10 micrometers, (b) is a case where it is 20 micrometers. It is a diagram which shows the pressure | voltage resistant test result of the capacitor | condenser based on Example 1, (a) is a case where the film thickness of a dielectric material layer is 10 micrometers, (b) is a case where it is 20 micrometers. The results of the moisture resistance load test of the capacitors according to Example 1 (vacuum laminating) and Example 2 (vacuum laminating + barrier metal) were compared with the capacitor according to the comparative example (transfer 1: dielectric layer laminated with high pressure) and transfer 2 is a diagram showing the case of low-pressure lamination (when the dielectric layer is 10 μm). The results of the moisture resistance load test of the capacitors according to Example 1 (vacuum laminating) and Example 2 (vacuum laminating + barrier metal) were compared with the capacitor according to the comparative example (transfer 1: dielectric layer laminated with high pressure) and transfer 2: When low-pressure laminated) is a diagram (when the dielectric layer is 20 μm). (A)-(c) is sectional drawing which shows the process in the manufacturing method of the conventional board | substrate with a built-in capacitor | condenser in order.

Explanation of symbols

11, 21, 31, 41, 51, 61 Transfer substrate 12, 22, 32, 42, 52, 62 Conductor pattern (capacitor electrode)
13, 23 Insulating material 14 Sheet 14 with dielectric material 14a, 34a, 54a Dielectric layer 14b, 34b Carrier film 33, 43, 53, 63 Barrier layer 71 Adhesive sheet (prepreg)
72 substrates

Claims (6)

Forming a first conductor pattern to be one electrode of the capacitor on the surface of the transfer substrate;
Transferring the first conductor pattern so as to be embedded in an insulating material and creating a first substrate constituent material;
Forming a second conductor pattern to be the other electrode of the capacitor on the surface of the transfer substrate;
Transferring the second conductor pattern so as to be embedded in an insulating material, and creating a second substrate constituent material;
A step of disposing a dielectric layer on the conductor pattern-embedded side of either the first substrate component or the second substrate component;
The first substrate component and the second substrate component are pressed and integrated so that the dielectric layer is sandwiched between the first conductor pattern and the second conductor pattern. Forming a step;
The manufacturing method of the board | substrate with a built-in capacitor | condenser characterized by including this. The method for producing a capacitor-embedded substrate according to claim 1, wherein the step of arranging the dielectric layer is performed by vacuum laminating a dielectric sheet formed by mixing a filler in a resin. A first conductor pattern embedded in the first insulating layer;
A second conductor pattern disposed so as to face the first conductor pattern and embedded in a second insulating layer different from the first insulating layer;
A dielectric layer disposed between the first insulating layer and the second insulating layer;
A capacitor-embedded substrate, comprising: The first conductor pattern is formed by transferring to the first insulating layer,
The substrate with built-in capacitor according to claim 3, wherein the second conductor pattern is formed by being transferred to the second insulating layer. A first conductor pattern embedded on one surface side of the dielectric layer;
A second conductor pattern disposed to face the first conductor pattern and embedded on the other surface side of the dielectric layer;
Have
A capacitor built-in substrate, wherein a barrier layer is formed between the first conductor pattern and the dielectric layer, and between the second conductor pattern and the dielectric layer.   An electronic component in which one or more surface mount components are mounted on the substrate according to claim 3.

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