CN1821922A - Circuit for speeding up stabilizing low voltage difference linear stabilizer output voltage - Google Patents
Circuit for speeding up stabilizing low voltage difference linear stabilizer output voltage Download PDFInfo
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- 239000003990 capacitor Substances 0.000 abstract 1
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Abstract
This invention relates to a circuit for speeding up the stabilized low voltage difference linear regulator output voltage based on a circuit composed of an output tube, an error amplifier, a primary standard voltage source, a resistor bleeder network and a load including reference voltage output by said primary voltage source and a feed back voltage output by the network characterizing that said resistor bleeder network is composed of four serial bleeder resistors used in providing three feed back voltages, namely, a first feed back voltage, a second voltage and a third feed back voltage, which utilizes the instant controlled current to speed up the discharge to the grating capacitance of the MPX and the discharge of the output capacitor so as to improve the instant response of LDO greatly.
Description
Technical field
The present invention relates to a kind of Analogous Integrated Electronic Circuits technology, especially refer to a kind of circuit of accelerating stabilizing low voltage difference linear stabilizer output voltage.
Background technology
LDO (Low Dropout Regulator; low pressure difference linear voltage regulator) is power supply IC (Integratedcircuit; integrated circuit) important branch in; with based on PWM (Pulse Width Modulation; pulse-length modulation); PFM (Pulse Frequency Modulation; the pulse frequency modulation principle) DC-DC (DC-to-dc) converter is compared; it is low that it has a cost; low and the little advantage of quiescent current of noise; simultaneously owing to need not inductance; also can not bring the problem of EMI, in portable product is used, use the power supply of LDO as system through regular meeting.
As shown in Figure 1, a basic LDO is by efferent duct 103, resistance pressure-dividing network 104, and error amplifier 102 and reference voltage source 101 constitute.The reference voltage generation module is band-gap reference (bandgap) voltage normally, and this module produces a reference voltage that changes with conditions of work such as power supply power supply, chip temperatures hardly.Output voltage VO UT drives load 105, and load comprises a load capacitance CL and a pull-up resistor RL.System samples by resistor network R1, R2 dividing potential drop, and this voltage division signal feeds back to the input end of EA (Error Amplifier, error amplifier).Another input end of error amplifier connects reference voltage, the output VG of error amplifier receives a PMOS driving tube MPX with very big breadth length ratio, when the variation of external loading condition or other conditions makes that output voltage VO UT changes, the output VG voltage of error amplifier also can change thereupon, the conducting degree of control PMOS pipe MPX, thus make the voltage of VOUT remain unchanged.Load capacitance CL is used for auxiliary control makes a such closed loop feedback system keep stable under various application conditions situations.
It is to investigate an important indicator of LDO performance that load variations causes the variation of VOUT and changes in contrast response speed,, wishes when load variations that the variation of VOUT output is the smaller the better from the designing requirement of LDO own.In the practical application, during the rapid variation of external loading, for example equivalent load RL becomes a less resistance by a bigger resistance suddenly, perhaps RL becomes a bigger resistance by a less resistance, so in moment of load variations, output current also can produce rapid big variation, also will cause the rapid variation of output voltage, this changes the positive input terminal that is reflected to error amplifier by feedback resistance, error amplifier just comes the conducting degree of power controlling pipe MPX by the voltage difference that compares Vfb and Vref, thereby comes regulated output voltage VOUT.
Fig. 2 provides the transient response simulation waveform of a kind of structure in typical case (LDO under a certain design as shown in Figure 1).Input voltage 2.5V, output 1.8V.Load on 1mA to switching fast between the 150mA.Wherein: first waveform is a load current among Fig. 2, and second waveform is output voltage, and the 3rd waveform is the grid voltage VG of MPX.
As we know from the figure, when load current by the 1mA transition during to 150mA, output has a process that descends and afterwards rise earlier, this is owing to when output voltage changes, error amplifier in requisition for the regular hour, the variation of the responsive load that the gate voltage of MPX can not be very fast.
When load current by the 150mA transition during to 1mA, the variation of the grid voltage VG of MPX is not the main cause of its output stabilisation delay, grid voltage is by drawing high than morning, MPX ends, too high voltage can only be via the current drain of load RL with 1mA on the load capacitance at this moment, and be the main cause that postpones the discharge time of load capacitance CL herein.
In the factor of many influence output stabilized speeies, play a major role the discharge time of output P being managed gate capacitance and load capacitance.In some design, since stability, the restriction of some parameters such as quiescent current, and when this LDO system did not possess very big drive current to MPX gate capacitance and load capacitance discharge, the response characteristic of LDO will be very poor.
Summary of the invention
The object of the present invention is to provide a kind of circuit of accelerating stabilizing low voltage difference linear stabilizer output voltage, do not influencing under the situation of indexs such as quiescent current, utilize the transient state controlled current flow to accelerate to the discharge of the gate capacitance of output power pipe MPX and the discharge of output capacitance, thereby improved the transient response of LDO greatly, and circuit scale and chip area all there is not too many variation.
A kind of circuit of accelerating stabilizing low voltage difference linear stabilizer output voltage provided by the present invention, based on by efferent duct, error amplifier, reference voltage source, the circuit that resistance pressure-dividing network and load are formed, comprise a reference voltage Vref and the feedback voltage Vfb by described resistance pressure-dividing network output by described reference voltage source output, it is characterized in that: described resistance pressure-dividing network is by four divider resistance Ra, Rd, Re, Rf is in series, be used to provide three feedback voltages, i.e. first feedback voltage Vfb+Δ V, second feedback voltage Vfb and the 3rd feedback voltage Vfb-Δ V.
In above-mentioned circuit, on the node between error amplifier and the efferent duct, also connect one first charge discharging resisting control circuit, be used for gate capacitance rapid discharge to efferent duct.
In above-mentioned circuit, the first charge discharging resisting control circuit is connected and composed successively by one first comparator device comp1, a MOS switch MN1 and a current source, and wherein: the input end of this first comparator device comp1 meets reference voltage Vref and first feedback voltage Vfb+Δ V respectively.
In above-mentioned circuit, it also comprises second a charge discharging resisting control circuit that is connected on the connected node of described load and resistance pressure-dividing network, is used for the electric capacity of load is carried out rapid discharge.
In above-mentioned circuit, the second charge discharging resisting control circuit is by one second comparator device comp2, one the 2nd MOS switch MN2 and a resistance R b connect and compose successively, and wherein: the input of this second comparer meets reference voltage Vref and the 3rd feedback voltage Vfb-Δ V respectively.
Owing to adopted above-mentioned technical solution, the present invention is not influencing under the situation of indexs such as quiescent current, utilize the transient state controlled current flow to accelerate to the discharge of the gate capacitance of output power pipe MPX and the discharge of output capacitance, thereby improved the transient response of LDO greatly, and circuit scale and chip area all there is not too many variation.
Description of drawings
Fig. 1 is the electrical block diagram of existing LDO output voltage;
Fig. 2 is the transient response simulation waveform figure of a kind of LDO in typical case;
Fig. 3 is the electrical block diagram of LDO output voltage of the present invention;
Fig. 4 LDO of the present invention adds the resultant transient response simulation waveform of same simulated conditions figure;
Fig. 5 is the enlarged diagram of first three waveform among Fig. 4.
Embodiment
As shown in Figure 3, the circuit of LDO output voltage of the present invention, based on the existing circuit of being formed by efferent duct 103, error amplifier 102, reference voltage source 101, resistance pressure-dividing network and load 105, its difference is: resistance pressure-dividing network 204 provides three feedback voltages, be respectively Vfb, than slightly high voltage Vfb+ Δ V of Vfb and the voltage Vfb-Δ V more lower slightly than Vfb.
The first charge discharging resisting control circuit 206 is for the gate capacitance rapid discharge to efferent duct 203, and by one first comparator device comp1, one the one MOS switch MN1 and a current source constitute.The input end of the first comparer comp1 meets reference voltage Vref and voltage Vfb+ Δ V slightly higher than feedback voltage that benchmark produces respectively.
The second charge discharging resisting control circuit 207 is for to load 205 electric capacity rapid discharges.By one second comparator device, one the 2nd MOS switch and a resistance constitute.The input of the second comparer comp2 meets reference voltage Vref and voltage Vfb-Δ V more lower slightly than feedback voltage that benchmark produces respectively.
Two switching tubes of two comparer control are given the discharge of MPX gate capacitance and output load capacitance under specific circumstances, accelerate stable.Δ V chooses according to actual conditions, recommends about 30mV, and resistance R d, the value of Re (this road electric current is approximately 5uA) in the application of typical LDO can be taken at 5k-7kohm.
Add same condition emulation for LDO of the present invention and obtain Fig. 4, first waveform is a load current among Fig. 4, and second waveform is output voltage, and the 3rd waveform is the grid voltage VG of MPX, and the 4th waveform is the grid voltage SW1 of MN1, and the 5th waveform is the grid voltage SW2 of MN2.
Vref=Vfb when load is stablized (very approaching in other words), comparer comp1 and comparer comp2 export low, and MN1 and MN2 end, system stability work.
When load was changed from small to big, output voltage VO UT descended, and when Vfb+ Δ V was lower than Vref, efferent duct, the first charge discharging resisting control circuit 206 worked.First comparer comp1 upset, SW1 uprises, a MN1 conducting, the gate capacitance of MPX is discharged rapidly, and VG is step-down faster, makes MPX conducting electric current become big fast, and output current increases fast, burning voltage.VOUT replys, and Vfb replys, and steady state (SS) is got back in the comp1 upset.Second this process of comparer comp2 is constant.
Load is from large to small the time, and output voltage VO UT rises, and when Vfb-Δ V was higher than Vref, load, second capacitance charge control circuit 207 of releasing worked.Comparer comp2 upset, SW2 uprises, the MN2 conducting, making CL go up too high voltage can release fast via Rb, and the resistance of Rb has determined the size of leakage current, and output voltage is reduced fast, reaches stable.VOUT replys, and Vfb replys, and steady state (SS) is got back in the comp2 upset.First this process of comparer comp1 is constant.
In order better to compare with original LDO, first three waveform in the enlarged drawing 4 obtains Fig. 5.
With existing LDO relatively, by the 1mA transition during to 150mA, the grid voltage VG of MPX descends rapider LDO of the present invention in load, output is promptly replied when dropping to 1.63V, and original LDO drops to 1.53V and just begins answer.The leakage current of VG is a transient current, can not influence the quiescent dissipation of LDO.
When load by the 150mA transition during to 1mA, existing LDO needs about 37us just to tend towards stability (is standard with output ± 5mV), 85us is complete stability (stablize do not become standard with VOUT and VG).LDO of the present invention only needs just to tend towards stability the 40us complete stability about 5us.
Above embodiment is only for the usefulness that the present invention is described, but not limitation of the present invention, person skilled in the relevant technique, under the situation that does not break away from the spirit and scope of the present invention, can also make various conversion or modification, therefore all technical schemes that are equal to also should belong within the category of the present invention, should be limited by each claim.And include within the scope of claim.
Claims (5)
1. circuit of accelerating stabilizing low voltage difference linear stabilizer output voltage, based on by efferent duct (103), error amplifier (102), reference voltage source (101), the circuit that resistance pressure-dividing network and load (105) are formed, comprise a reference voltage (Vref) and the feedback voltage (Vfb) by described resistance pressure-dividing network output by described reference voltage source (101) output, it is characterized in that: described resistance pressure-dividing network (204) is by four divider resistance (Ra, Rd, Re, Rf) be in series, be used to provide three feedback voltages, i.e. first feedback voltage (Vfb+ Δ V), second feedback voltage (Vfb) and the 3rd feedback voltage (Vfb-Δ V).
2. circuit according to claim 1 is characterized in that: also connect one first charge discharging resisting control circuit (206) on the node between described error amplifier (102) and the efferent duct (103), be used for the gate capacitance rapid discharge to efferent duct (103).
3. circuit according to claim 2, it is characterized in that: the described first charge discharging resisting control circuit (206) is connected and composed successively by one first comparator device (comp1), a MOS switch (MN1) and a current source, and wherein: the input end of this first comparator device (comp1) connects reference voltage (Vref) and first feedback voltage (Vfb+ Δ V) respectively.
4. according to claim 1 or 2 or 3 described circuit, it is characterized in that: it also comprises second a charge discharging resisting control circuit (207) that is connected on the connected node of described load (105) and resistance pressure-dividing network (204), be used for the electric capacity of load (105) is carried out rapid discharge.
5. circuit according to claim 4, it is characterized in that: the described second charge discharging resisting control circuit (207) is by one second comparator device (comp2), one the 2nd MOS switch (MN2) and a resistance (Rb) connect and compose successively, and wherein: the input of this second comparer connects reference voltage (Vref) and the 3rd feedback voltage (Vfb-Δ V) respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100238797A CN100414469C (en) | 2006-02-15 | 2006-02-15 | Circuit for speeding up stabilizing low voltage difference linear stabilizer output voltage |
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| CNB2006100238797A CN100414469C (en) | 2006-02-15 | 2006-02-15 | Circuit for speeding up stabilizing low voltage difference linear stabilizer output voltage |
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| CN101183270B (en) * | 2007-11-21 | 2010-06-02 | 北京中星微电子有限公司 | Low pressure difference voltage stabilizer |
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| CN101957625A (en) * | 2010-11-12 | 2011-01-26 | 复旦大学 | Low dropout linear voltage regulator for driving nF-stage load |
| CN101187818B (en) * | 2006-11-21 | 2012-01-11 | 联发科技股份有限公司 | Integrated circuit and method for providing an output voltage that is substantially a reference voltage |
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| CN102393779A (en) * | 2011-10-18 | 2012-03-28 | 中国科学院微电子研究所 | A kind of LDO circuit with compensation circuit |
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