CN1797756A - Inner connected bonding pads of semiconductor IC - Google Patents
Inner connected bonding pads of semiconductor IC Download PDFInfo
- Publication number
- CN1797756A CN1797756A CNA2004100934667A CN200410093466A CN1797756A CN 1797756 A CN1797756 A CN 1797756A CN A2004100934667 A CNA2004100934667 A CN A2004100934667A CN 200410093466 A CN200410093466 A CN 200410093466A CN 1797756 A CN1797756 A CN 1797756A
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- pad
- layer
- metal level
- metal
- integrated circuit
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 76
- 238000000034 method Methods 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- 238000003466 welding Methods 0.000 claims description 8
- 230000000694 effects Effects 0.000 claims description 5
- 238000005538 encapsulation Methods 0.000 claims description 3
- 230000008859 change Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 4
- 230000006872 improvement Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
半导体集成电路的内连焊盘，焊盘包括：六层金属层M1－M6，分别设置在相邻金属层之间的多层介质层；和设置在发明焊盘的最底层金属层M1和顶层金属层M6之间金属电路2；其特征是，焊盘最底层金属层M1和顶层金属层M6的尺寸与焊盘的整体尺寸相同，最底层金属层M1和顶层金属层M6之间镶嵌类似于金属－介质－金属(MIM)结构的无源装置，无源装置的金属层不连续，无源装置的金属层图形随着电路图形变化而变化。The interconnection pad of a semiconductor integrated circuit, the pad includes: six layers of metal layers M1-M6, multi-layer dielectric layers respectively arranged between adjacent metal layers; and the bottom metal layer M1 and the top layer of the inventive pad The metal circuit 2 between the metal layer M6; it is characterized in that the size of the bottom metal layer M1 and the top metal layer M6 of the pad is the same as the overall size of the pad, and the inlay between the bottom metal layer M1 and the top metal layer M6 is similar to For passive devices with metal-medium-metal (MIM) structure, the metal layer of the passive device is discontinuous, and the pattern of the metal layer of the passive device changes with the change of the circuit pattern.
Description
Technical field
The present invention relates generally to the pad of semiconductor integrated circuit, is specifically related to the inner connected bonding pads of semiconductor integrated circuit.
Background technology
Pad is the important composition part in the semiconductor integrated circuit, have at least three layers the integrated circuit, active circuit is positioned at below the pad, and the metal level of adjacent pads layer plays the cushioning effect of dispersive stress, prevents pad and leakage current occurs between the circuit under it.
Usually semiconductor integrated circuit comprises; Substrate; The a plurality of active devices that form on the substrate surface; Order forms on the part in a plurality of active devices has the pad that layer (footprint) is covered in the bottom; Between pad and substrate, has a metal level of composition that layer (footprint) is covered in the bottom, the metal layer sequence of composition is formed on a plurality of active devices, every layer of metal level and active device separate with the first dielectric substance electricity, and the bottom of pad is covered layer order and overlapped the bottom of the metal level of composition and cover on the layer; Every layer the metal level and the pad of composition separate with second dielectric substance, every layer the metal level of composition between first dielectric substance and active device, form the barrier layer, prevented to produce leakage current between second dielectric substance and the active device; With the electric connection line that pad is connected to active device.
U.S. Pat-No.5751065 that on May 12nd, 1998 announced, denomination of invention is: disclose a kind of integrated circuit structure in " integrated circuit with the active device below the pad ", can be clear that other relations between parts in addition of pad and integrated circuit from this United States Patent (USP).Integrated circuit comprises: integrated circuit (IC) chip 1; The formation subclass becomes a plurality of metal pads 3 on the circuit; Dielectric layer covers on the whole surface of integrated circuit (IC) chip 1, and the dielectric layer composition exposes metal pad 3; Integrated circuit has and is positioned at below the pad 3 for example active device of I/O buffer; At least one deck the metal level of composition cover and to be positioned under the pad and part above the active device region.Play the effect of dispersive stress near the metal level of pad, the globality of dielectric layer is not destroyed in welding process, even in welding process during the media damage between pad and its immediate metal level, leakage current also can stop at metal level.So the zone below the pad can be used for active device.
But pad conventional in the semiconductor integrated circuit comprises the multiple layer metal layer, for example, comprises six layers of metal level.Active circuit is positioned at below the pad.All pad is positioned on the non-active area of semiconductor integrated circuit, and the Butut of the multiple layer metal layer that comprises in the existing pad is in full accord from top to bottom, shows as Fig. 1; Metallic circuit shows as Fig. 2 between pad and substrate.Therefore, cause the overall Butut difficulty of semiconductor integrated circuit by existing pad layout structure, cause the die area of semiconductor integrated circuit big, integrated level is low.
In order to overcome the shortcoming that exists in the prior art, the present invention is proposed.
Summary of the invention
The pad that the purpose of this invention is to provide logotype in a kind of semiconductor integrated circuit.Basically overcome the shortcoming that is limited in the technology.
By pad of the present invention, comprising: the multiple layer metal layer is separately positioned on the multilayer dielectricity layer between the adjacent metal, and is arranged on the metallic circuit between pad bottom metal level and the top layer metallic layer.Pad bottom metal level is identical with the overall dimensions of pad with the top layer metallic layer size, inlays the passive device that is similar to metal-dielectric-metal (MIM) structure between pad bottom metal level and the top layer metallic layer.The metal level of passive device is discontinuous, and the passive device metal layer image changes and changes along with circuitous pattern.Pad bottom metal level plays the effect of dispersive stress; globality at the dielectric layer between the metal level is not destroyed in welding process; even in welding process during the media damage between pad and its immediate metal level; leakage current also can stop at metal level, and the bottom metal level protection device of pad is not damaged in encapsulation process.The pad top layer metallic layer is by the not electrical connection of the link on active device, to prevent to damage device.
Since by the intermediate metal layer Butut of pad of the present invention along with circuit layout design need change, therefore, increased the flexibility of Butut, make layout-design easy.Reduce the area of semiconductor integrated circuit naked core in addition, improved the integrated level of semiconductor integrated circuit, reduced the production cost of semiconductor integrated circuit.
Description of drawings
The following description of carrying out in conjunction with the drawings the present invention may be better understood purpose and advantage of the present invention, accompanying drawing is a part of specification, accompanying drawing illustrates principle of the present invention and feature with the word segment of specification, demonstrates the embodiment that represents the principle of the invention and feature in the accompanying drawing.All identical part is indicated with identical reference number or symbol in the accompanying drawing.In the accompanying drawing:
Fig. 1 is existing pad cutaway view, and all pad is all on non-active area;
Fig. 2 is the cutaway view that shows the metallic circuit layouts between existing pad and the substrate;
Fig. 3 shows below the pad of one embodiment of the invention and the cutaway view of the layouts of active device between the pad and circuit; With
Fig. 4 shows below the pad of another embodiment of the present invention and the cutaway view of the layouts of active device between the pad and circuit.
The part description of the reference number indication in the accompanying drawing:
The 1-pad; The 2-circuit; The 3-solder joint; The 4-contact; P Well-P trap; M1-M6-metal level 1-metal level 6;
Embodiment
[embodiment 1]
Fig. 3 shows below the pad of one embodiment of the invention and the cutaway view of the layouts of active device between the pad and circuit.
Referring to Fig. 3, be positioned on the active device by pad of the present invention, pad of the present invention comprises: six layers of metal level M1-M6 are separately positioned on the multilayer dielectricity layer between the adjacent metal; And be arranged on metallic circuit 2 between the bottom metal level M1 of invention pad and the top layer metallic layer M6.The bottom metal level M1 of pad of the present invention is identical with the overall dimensions of pad with the size of top layer metallic layer M6, inlay the passive device that is similar to metal-dielectric-metal (MIM) structure between pad bottom metal level M1 and the top layer metallic layer M6, the metal level of passive device is discontinuous, and the metal layer image of passive device changes and changes along with circuitous pattern; Pad bottom metal layer M1 plays the effect of dispersive stress, globality at the dielectric layer between the metal level is not destroyed in welding process, even in welding process during the media damage between pad and its immediate metal level, leakage current also can stop at metal level.Pad bottom metal layer M1 protection device is not damaged in encapsulation process.Pad top layer metallic layer M6 is by the not electrical connection of the link on active device, to prevent to damage device.The pad structure of pad bottom metal layer M1 and pad top layer metallic layer M6 depends on the layouts of metallic circuit.
[embodiment 2]
Fig. 4 shows below the pad of another embodiment of the present invention and the cutaway view of the layouts of active device between the pad and circuit.
Press the pad of present embodiment, bottom metal layer M1 is identical with first embodiment with top layer metallic layer M6, just the structure between bottom metal layer M1 and the top layer metallic layer M6 is different with first embodiment, and this difference is to be determined by the circuit structure between bottom metal layer M1 and the top layer metallic layer M6.
Owing to by the bottom metal layer M1 of pad of the present invention and the need variation of the metal level Butut between the top layer metallic layer M6, therefore, increased the flexibility of Butut, made layout-design easy along with circuit layout design.In addition, also reduce the area of semiconductor integrated circuit naked core, improved the integrated level of semiconductor integrated circuit, reduced the production cost of semiconductor integrated circuit.
More than describe inner connected bonding pads in detail by semiconductor integrated circuit of the present invention.But the invention is not restricted to detailed description herein.The technical staff of the industry should be appreciated that under the premise without departing from the spirit and scope of the present invention, the present invention can implement with other form, and the present invention also has various improvement and variation, and these improvement and variation all fall in the scope of protection of present invention.Therefore, by whole technical schemes of the present invention, cited execution mode just is used to illustrate the present invention rather than restriction the present invention, and the present invention is not limited to the details of describing herein.The scope of protection of present invention is defined by appending claims.
Claims (1)
1, the inner connected bonding pads of semiconductor integrated circuit, pad comprises: six layers of metal level M1-M6 are separately positioned on the multilayer dielectricity layer between the adjacent metal; And be arranged on metallic circuit 2 between the bottom metal level M1 of invention pad and the top layer metallic layer M6; It is characterized in that, the size of pad bottom metal level M1 and top layer metallic layer M6 is identical with the overall dimensions of pad, inlay the passive device that is similar to metal-dielectric-metal (MIM) structure between bottom metal level M1 and the top layer metallic layer M6, the metal level of passive device is discontinuous, and the metal layer image of passive device changes and changes along with circuitous pattern; Pad bottom metal level M1 plays the effect of dispersive stress, globality at the dielectric layer between the metal level is not destroyed in welding process, even in welding process during the media damage between pad and its immediate metal level, leakage current also can stop at metal level, and pad bottom metal layer M1 protection device is not damaged in encapsulation process; Pad top layer metallic layer M6 is by the not electrical connection of the link on active device, to prevent to damage device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100934667A CN100362657C (en) | 2004-12-22 | 2004-12-22 | Interconnect pads of semiconductor integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100934667A CN100362657C (en) | 2004-12-22 | 2004-12-22 | Interconnect pads of semiconductor integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1797756A true CN1797756A (en) | 2006-07-05 |
| CN100362657C CN100362657C (en) | 2008-01-16 |
Family
ID=36818668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100934667A Expired - Lifetime CN100362657C (en) | 2004-12-22 | 2004-12-22 | Interconnect pads of semiconductor integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100362657C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540316B (en) * | 2008-03-21 | 2011-04-20 | 联发科技股份有限公司 | Integrated circuit chip |
| CN102034779A (en) * | 2009-10-08 | 2011-04-27 | 台湾积体电路制造股份有限公司 | Chip design with robust corner bumps |
| CN102263089A (en) * | 2010-05-27 | 2011-11-30 | 海力士半导体有限公司 | Semiconductor integrated circuit having a multi-chip structure |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0637840A1 (en) * | 1993-08-05 | 1995-02-08 | AT&T Corp. | Integrated circuit with active devices under bond pads |
| JP3583927B2 (en) * | 1998-07-15 | 2004-11-04 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
| US6362531B1 (en) * | 2000-05-04 | 2002-03-26 | International Business Machines Corporation | Recessed bond pad |
| US6614091B1 (en) * | 2002-03-13 | 2003-09-02 | Motorola, Inc. | Semiconductor device having a wire bond pad and method therefor |
| US6717270B1 (en) * | 2003-04-09 | 2004-04-06 | Motorola, Inc. | Integrated circuit die I/O cells |
-
2004
- 2004-12-22 CN CNB2004100934667A patent/CN100362657C/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540316B (en) * | 2008-03-21 | 2011-04-20 | 联发科技股份有限公司 | Integrated circuit chip |
| CN102034779A (en) * | 2009-10-08 | 2011-04-27 | 台湾积体电路制造股份有限公司 | Chip design with robust corner bumps |
| CN102034779B (en) * | 2009-10-08 | 2012-12-12 | 台湾积体电路制造股份有限公司 | Chip design with robust corner bumps |
| CN102263089A (en) * | 2010-05-27 | 2011-11-30 | 海力士半导体有限公司 | Semiconductor integrated circuit having a multi-chip structure |
| CN102263089B (en) * | 2010-05-27 | 2015-08-05 | 海力士半导体有限公司 | There is the semiconductor integrated circuit of multi-chip structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100362657C (en) | 2008-01-16 |
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| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Semiconductor Manufacturing International (Beijing) Corp. Assignor: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Contract fulfillment period: 2009.4.29 to 2014.4.29 Contract record no.: 2009990000626 Denomination of invention: Inner connected bonding pads of semiconductor IC Granted publication date: 20080116 License type: Exclusive license Record date: 20090605 |
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| LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2009.4.29 TO 2014.4.29; CHANGE OF CONTRACT Name of requester: SEMICONDUCTOR MANUFACTURING INTERNATIONAL ( BEIJIN Effective date: 20090605 |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111130 |
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Effective date of registration: 20111130 Address after: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corp. Patentee after: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Address before: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Patentee before: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. |
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