CN1181541C - Layout structure of multilayer metal power/ground bus - Google Patents

Abstract

The invention discloses a layout structure of a multilayer metal power/ground bus on a microelectronic chip, which places most power/ground lead pads on the chip on the outermost layer of all the lead pads, and electrically connects the power/ground lead pads to the internal circuit of the chip by the multilayer metal power/ground bus, thereby achieving the advantages of reducing the whole chip area and reducing the cost. The invention can make the connecting lines of a plurality of lead pads of the microelectronic chip packaged by N layers (N is more than 1) of lead pads and the corresponding input/output circuits of the internal circuits have larger physical layout width, and reduce the resistance value of the connecting lines.

Description

Layout structure of multilayer metal power/ground bus

technical field

The present invention relates to a layout structure for connecting a plurality of power/ground lead pads and an internal circuit on a microelectronic chip, in particular to a multilayer metal power/ground bus to connect multiple power/ground on the outermost layer Lead pads and a layout structure of an internal circuit.

Background technique

With the popularity of system on a chip (system on a chip) design, there are often hundreds of lead pads on a chip. Since the plurality of lead pads are connected to a lead frame or a substrate by mechanical wire bonding, the area occupied by them is not easy to shrink with the progress of the semiconductor manufacturing process. When the manufacturing process enters the 0.25um, O.18um or more precise stage, the width of the hundreds of lead pads and the wiring width of the multiple input/output circuits connected to the internal circuit in the chip often cause the The bottleneck where the overall chip area cannot be reduced, this phenomenon is generally called pad limit.

FIG. 1 is a layout structure of an existing microelectronic chip connecting the plurality of lead pads and the input/output circuits of the corresponding internal circuits. Generally speaking, a chip 11 includes an internal circuit 13 and a plurality of lead pads 12 , and the internal circuit 13 includes a core circuit (core) and a plurality of input/output circuits corresponding to the plurality of lead pads 12 . The plurality of lead pads can be divided into input/output lead pads (I/O pad) and power/ground lead pads (power/ground pad) according to their functions, wherein the input/output lead pads are used to transmit the chip signal, The power/ground lead pads provide the required power and ground within the internal circuit 13 . One end of the plurality of lead pads 12 is electrically connected to the internal circuit 13 by wires, and the upper end thereof is connected to a lead frame or a substrate (not shown) by mechanical wire bonding. The plurality of lead pads in FIG. 1 take the structure of three-tier bonding pad schematics (3-tier bonding pad schematics) as an example, that is, a unit lead pad 15 includes three lead pads, which are respectively located on the first layer 17, the second layer 18 and the second layer. There are three layers 19 , and any lead pad 12 is connected to an input/output circuit 16 of the internal circuit 13 . The smaller the width 14 occupied by a unit of lead pads, the more lead pads can be accommodated under the same perimeter of the chip, or the area of the chip can be effectively reduced with the same number of lead pads. In other words, how to effectively reduce the width 14 occupied by a unit lead pad or the connection width between the plurality of lead pads and the input/output circuit of the corresponding internal circuit 13 will be limited by the lead pad. Under the circumstances, the area of the whole chip can be effectively reduced and the cost can be reduced.

In addition, if the plurality of lead pads are arranged too closely on the first to third layers 17-19, the width of the connection lines between the plurality of lead pads 12 and the input/output circuit 16 of the internal circuit 13 will inevitably be limited. Shrinkage, causing electron migration (electromigration) effect and affecting the reliability of the chip (reliability). In addition, the width of the input/output circuit 16 of the internal circuit 13 is also limited, thereby increasing the design difficulty of its internal physical layout and electrostatic protection.

Contents of the invention

A first object of the present invention is to eliminate the current disadvantage of a plurality of lead pads in a chip occupying a relatively large perimeter of the chip in the case of lead pad constraints.

The second purpose of the present invention is to eliminate the current shortcoming that the width of a plurality of lead pads in a chip and the wiring lines of the input/output circuits of the corresponding internal circuits is too small under the limitation of the lead pads.

The third object of the present invention is to eliminate the current disadvantage that the width of multiple input/output circuits of the internal circuit of a chip is too small to be easily designed under the condition of lead pad limitation.

In order to achieve the above object, the present invention provides a layout structure of a multi-layer metal power/ground bus for connecting the internal circuit and a plurality of power/ground lead pads on a microelectronic chip. The layout structure places most of the power/ground lead pads on the outermost layer of all lead pads, and uses at least one multi-layer metal power/ground bus to electrically connect the multiple power/ground lead pads, and then electrically connects the plurality of power/ground lead pads to the internal circuitry. The multilayer metal power/ground bus can be segmented into a plurality of power/ground external buses, and at least one power/ground bridge bus is used to electrically connect any power/ground external bus to the internal circuit of the chip. Since the plurality of power/ground lead pads do not need to be individually connected to the internal circuit, but are collectively and electrically connected to the internal circuit with at least one multilayer metal power/ground bus, it is possible to reduce the need for the plurality of input/output circuits. The perimeter of the chip can be reduced, thereby achieving the purpose of reducing the entire chip area and increasing the cost. In terms of high-frequency circuits currently used, often every two input/output lead pads must be equipped with a power/ground lead pad, and even each input/output lead pad must be equipped with a power/ground lead pad. Since the present invention uses at least one multi-layer metal power/ground bus to gather and electrically connect the plurality of power/ground lead pads to the internal circuit, the physical layout width occupied by the input/output circuit on average can be increased, and also That is, the plurality of input/output circuits can ensure greater flexibility in physical layout and electrostatic protection design. In addition, since the wiring widths of the plurality of I/O circuits and the I/O lead pads can be increased, the resistance value of the wiring lines is reduced, thereby improving the reliability of the chip. The present invention is applicable to an N-layer (N>1) lead pad structure.

The layout structure of the multilayer metal power/ground bus of the present invention includes an internal circuit, at least one multilayer metal power/ground bus, a plurality of power/ground lead pads and a plurality of input/output lead pads. The internal circuit includes a core circuit and a plurality of input/output circuits. The core circuit is the core of the entire chip function, including various digital circuits, analog circuits or mixed-mode circuits. The multilayer metal power/ground bus includes at least one power/ground external bus and at least one power/ground bridge bus. The power/ground external bus is used to electrically connect the plurality of power/ground lead pads, and the power/ground bridge bus is used to electrically connect the power/ground external bus to the internal circuit. The power/ground external bus can be connected in series to form a ring structure, segmented linear structure or other structures, which is not limited in the present invention. The plurality of power/ground lead pads are electrically connected to the multilayer metal power/ground bus for providing power and ground required by the internal circuit. The plurality of input/output lead pads are electrically connected to the plurality of input/output circuits of the internal circuit for transmitting operation signals of the chip.

Description of drawings

The invention will be described with reference to the accompanying drawings, in which:

Fig. 1 is the layout structure of a plurality of lead pads of existing microelectronic chip and the input/output circuit of its corresponding internal circuit;

Fig. 2 is the layout structure of the first preferred embodiment of the multilayer metal power/ground bus of the present invention;

Fig. 3 is the layout structure of the third preferred embodiment of the multilayer metal power/ground bus of the present invention;

Fig. 4 is the layout structure of the third preferred embodiment of the multilayer metal power/ground bus of the present invention; and

FIG. 5 is a layout structure of a fourth preferred embodiment of a multilayer metal power/ground bus according to the present invention.

Detailed ways

Fig. 2 is the layout structure of the first preferred embodiment of the multilayer metal power supply/ground bus of the present invention, wherein the structure of three layers of lead pads is taken as an example, that is, all lead pads are respectively located on the first layer 17 and the second layer 18 and in the third layer 19 , and any input/output lead pad 24 is electrically connected to the internal circuit 13 by a connection line. In this layout structure, a plurality of power/ground lead pads 23 are placed on the outermost layer of all lead pads, that is, inside the third layer 19, and the plurality of input/output lead pads 24 are placed on the inner circle of all lead pads, that is, Inside the first layer 17 and the second layer 18 . The plurality of power/ground lead pads 23 are electrically connected to a multilayer metal power/ground bus by a wire. And the multi-layer metal power/ground bus is electrically connected to the internal circuit 13 to provide power and ground for each metal layer. The multilayer metal power/ground bus includes at least one power/ground external bus 22 and at least one power/ground bridge bus 26 . The power/ground external bus 22 is connected to the plurality of power/ground lead pads 23 and is electrically connected to the internal circuit 13 of the chip through at least one power/ground bridge bus 26 . Since the plurality of power/ground lead pads 23 do not need to be individually connected to the internal circuit 13, but are electrically connected to the internal circuit by a multilayer metal power/ground bus, it is possible to reduce the number of input/output circuits. The required perimeter of the chip is reduced, thereby achieving the purpose of reducing the entire chip area and reducing the cost. Only a few connection gaps need to be inserted between the plurality of I/O lead pads 24 to allow the power/ground bridge bus 26 to pass through and be electrically connected to the internal circuit 13 . In practical application of the structure of FIG. 2 , the power/ground external bus 22 can also be electrically connected to the internal circuit 13 through more than two power/ground bridge buses 26 to balance the distribution of current density. A unit lead pad 25 of the present invention only includes two input/output lead pads 24, so the width 21 occupied by this unit lead pad 25 is smaller than the width 14 of a unit lead pad of the prior art, representing the same More lead pads can be accommodated under the perimeter of the chip, or the area of the chip 11 can be reduced under the same number of lead pads.

Fig. 3 is the layout structure of the second preferred embodiment of the multi-layer metal power/ground bus of the present invention, which connects the power/ground external bus 22 in series to form a ring (ring), and then connects it with at least one power/ground bridge The bus 26 is electrically connected to this internal circuit 13 .

Fig. 4 is the layout structure of the third preferred embodiment of the multilayer metal power/ground bus of the present invention, which places the power/ground external bus 22 on the outermost layer of the chip 11, and the multiple input/output The lead pads 24 and the plurality of power/ground lead pads 23 can be concentrated in the same area to facilitate subsequent fabrication.

Fig. 5 is the layout structure of the fourth preferred embodiment of the multilayer metal power supply/ground bus of the present invention, which divides the power supply/ground external bus 22 into many sections (can be referred to as segmented linear structure), and each section passes through At least one power/ground bridge bus 26 is connected to the internal circuit 13 . This layout structure can disperse the current density of each power/ground bridging bus 26, and combine a proper number of power/ground lead pads 23 to dispersely connect to multiple segments of the power/ground external bus 22, which can avoid this problem. It occurs that multiple power/ground lead pads 23 electrically interfere with each other.

For the multiple input/output circuits 16 of the internal circuit 13, the layout structure of the present invention only needs to correspond to the multiple input/output lead pads 24 and a small number of power/ground bridge buses 26, so the chip circumference can be used The length must be longer than that of the prior art. In other words, the wiring lines of the plurality of input/output lead pads 24 and the plurality of input/output circuits 16 of the internal circuit 13 will be able to use wider metal wiring, and reduce The resistance value is reduced and the probability of electromigration effect is reduced, thereby improving the reliability of the chip 11 . In addition, the width 21 occupied by a unit lead pad of the present invention is shorter than that of the prior art, so under the same number of lead pads, the average width occupied by a plurality of input/output circuits 16 of the internal circuit 16 is just can increase. In other words, the plurality of input/output circuits 16 can be guaranteed to have a larger physical layout width, thus reducing the design difficulty of physical layout and electrostatic protection thereof.

The technical content and technical characteristics of the present invention have been described above, but those skilled in the art may still make various replacements and modifications that do not depart from the spirit of the present invention based on the examples and illustrations of the present invention; therefore, the protection scope of the present invention should not be limited to The content described in the embodiments shall include various replacements and modifications that do not depart from the present invention, and shall be covered by the scope of the following claims.

Claims (7)

1. A layout structure of a multilayer metal power/ground bus, comprising: An internal circuit, the outermost layer of which includes a plurality of input/output circuits; at least one multilayer metal power/ground bus electrically connected to the internal circuit; a plurality of power/ground lead pads electrically connected to the multilayer metal power/ground bus; and a plurality of input/output lead pads electrically connected to a plurality of input/output circuits of the internal circuit; Wherein the multilayer metal power/ground bus contains: at least one power/ground external bus for electrically connecting the plurality of power/ground lead pads; and At least one power/ground bridge bus is used to electrically connect the power/ground external bus to the internal circuit. 2. The layout structure as claimed in claim 1, wherein the power/ground external buses are connected in series in a ring structure. 3. The layout structure of claim 1, wherein the power/ground external bus is a segmented linear structure. 4. A multilayer metal power/ground bus comprising at least one power/ground external bus and at least one power/ground bridge bus, the power/ground external bus electrically connected to a plurality of power/ground lead pads, the power/ground bridge The bus electrically connects the power/ground external bus to an internal circuit to provide power and ground, thereby increasing the width of multiple input/output circuits of the internal circuit. 5. The multilayer metal power/ground bus as claimed in claim 4, wherein the plurality of power/ground lead pads are located on the outermost layer of all lead pads. 6. The multilayer metal power/ground bus as claimed in claim 4, wherein the power/ground external bus is connected in series to form a ring structure. 7. The multilayer metal power/ground bus as claimed in claim 4, wherein the power/ground external bus is a segmented linear structure.

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