CN1764062A - DC offset correction device - Google Patents

Abstract

The invention provides a DC offset correction device for correcting the DC offset of the output signal of a gain stage (gain stage), comprising: a digital-to-analog converter (DAC) electrically connected to the gain stage for generating a current signal according to a DC offset condition of an output signal of the gain stage; and a current-to-current converter (current-to-current converter) electrically connected to the DAC and the gain stage for performing a reduction process on the current signal to generate a compensation signal to reduce a DC offset of an output signal of the gain stage.

Description

DC offset correction device

technical field

The invention provides a DC offset correction device, especially a correction device for reducing the DC offset of a circuit.

Background technique

In the past wireless communication applications, most radio frequency transmission receivers (RFtransceiver) adopt the traditional "super-heterodyne" (super-heterodyne) architecture. Although the transmission receiver of the superheterodyne structure has good performance, it must use many components such as the expensive and bulky IF SAW filter (IF SAW Filter), which makes the system complexity and production cost higher.

Recently, many RF transmission receivers have changed to a "direct conversion" (direct conversion) type architecture to improve the above-mentioned problems of the superheterodyne transmission receiver. Direct conversion, also known as zero intermediate frequency (zero IF), is to directly reduce the received RF signal to the base frequency. Compared with the traditional superheterodyne architecture, the direct-conversion transmission receiver can save components such as expensive SAW filter, intermediate frequency to base frequency conversion circuit, and image rejection filter (image reject filter), so it can reduce the cost of the circuit cost and space required.

However, in practical applications, the direct conversion architecture often faces the problem of DC offset, which seriously affects performance. The DC offset will not only distort and alias the signal output by the mixer, but may also cause saturation of subsequent circuits (such as analog-to-digital converters, ADCs), thereby reducing the overall performance of the receiving circuit.

In UP Patent 6225848, "Method and apparatus forsettling and maintaining DC offset" and UP Patent 6356217, "Enhanced DC off set correction through bandwidth and clock speedselection", Tilley et al proposed to set up a DC offset correction loop to correct the circuit DC offset architecture. In the aforementioned DC offset correction circuit, a binary search (binary search) algorithm is used to adjust the output voltage of a voltage-type digital-to-analog converter (DAC) to achieve the purpose of correcting the DC offset of the circuit. . To improve the calibration accuracy, additional voltage-type digital-to-analog converters and operational transconductance amplifiers (OTA) need to be added.

However, the aforementioned method of improving the accuracy of DC offset correction not only increases the circuit cost, but also the accuracy of the correction is still limited by the resolution of the voltage-type digital-to-analog converter itself. In other words, the conventional technology obviously cannot meet the dual requirements of reducing circuit cost and improving calibration accuracy at the same time.

Contents of the invention

The technical problem to be solved by the present invention is to provide a DC offset correction device that can reduce circuit cost and improve correction accuracy at the same time.

A preferred embodiment of the present invention provides a DC offset (DC offset) correction device for correcting the DC offset of a gain stage (gain stage) output signal. The DC offset correction device includes: a A digital-to-analog converter (digital-to-analog converter, DAC) is electrically connected to the gain stage, and is used to generate a current signal according to the DC offset of the output signal of the gain stage; and a current-to-current converter (current- to-current converter), electrically connected to the digital-to-analog converter and the gain stage, and used for reducing the current signal to generate a compensation signal, so as to reduce the DC offset of the output signal of the gain stage.

Another DC offset correction device provided in a preferred embodiment of the present invention includes a digital-to-analog converter (DAC), electrically connected to the gain stage, and used for outputting the signal according to the DC offset of the gain stage generating a current signal; a first current-to-current converter electrically connected to the digital-to-analog converter and the gain stage for reducing the current signal to generate a first compensation signal; and a second current to a current converter, electrically connected to the digital-to-analog converter and the gain stage, and used to generate a second compensation signal according to a reference current; wherein the first and second compensation signals are used to reduce the output signal of the gain stage DC offset situation.

A preferred embodiment of the present invention also provides a DC offset correction device, which includes a first digital-to-analog converter electrically connected to the gain stage for generating a DC offset according to the DC offset of the output signal of the gain stage a first current signal; a first current-to-current converter electrically connected to the first digital-to-analog converter and the gain stage, and used to reduce the first current signal to generate a first compensation signal; a second digital-to-analog converter, electrically connected to the gain stage, for generating a second current signal according to the DC offset of the output signal of the gain stage; and a second current-to-current converter, electrically connected to the gain stage The second digital-to-analog converter and the gain stage are used to reduce the second current signal to generate a second compensation signal; wherein the first and second compensation signals are used to reduce the output signal of the gain stage DC offset situation.

The advantage of the present invention is that the current-mode digital-to-analog converter is used to replace the voltage-mode digital-to-analog converter in the known technology, which can reduce the circuit cost, and through the operation of the current-to-current converter, the current-mode digital-to-analog converter can be reduced. The scale of the current signal output by the converter can achieve the purpose of improving the calibration accuracy.

Description of drawings

FIG. 1 is a simplified partial block diagram of a first embodiment of a signal receiver applying the DC correction device of the present invention.

FIG. 2 is a schematic diagram of a first embodiment of the current-mode digital-position-analog converter in FIG. 1 .

FIG. 3 is a schematic diagram of a second embodiment of the current-mode digital-position-analog converter in FIG. 1 .

FIG. 4 is a schematic diagram of a third embodiment of the current-mode digital-position-analog converter in FIG. 1 .

FIG. 5 is a simplified partial block diagram of a second embodiment of a signal receiver applying the DC correction device of the present invention.

FIG. 6 is a simplified partial block diagram of a third embodiment of a signal receiver applying the DC correction device of the present invention.

FIG. 7 is a simplified partial block diagram of a fourth embodiment of a signal receiver applying the DC correction device of the present invention.

FIG. 8 is a simplified partial block diagram of a fifth embodiment of a signal receiver applying the DC correction device of the present invention.

FIG. 9 is a simplified partial block diagram of a sixth embodiment of a signal receiver applying the DC correction device of the present invention.

FIG. 10 is a schematic diagram of an embodiment of a differential gain stage.

100, 500, 600, 700, 800, 900 signal receiver

110, 610, 810, 910 pre-stage circuit

120, 520, 620, 720, 820, 920, 1000 gain stages

122, 124 resistors

126 capacitance

130, 630, 830, 930 control circuit

132, 632, 832, 932 comparison circuits

134, 634, 834, 934 processing units

140, 640, 840, 942, 944 Current Mode Digital to Analog Converters

150, 650, 850, 860, 950, 960 Current-to-Current Converters

152, 652, 852, 862, 952, 962 Current to Voltage Converters

154, 654, 854, 864, 954, 964 compensation signal generator

Detailed ways

The DC offset correction device proposed by the present invention, in addition to being applicable to signal receivers (receivers) or transmission receivers (transceivers) of direct conversion architecture or superheterodyne architecture, can also be applied to other Electronic circuit for DC offset. For the convenience of description, the structure and operation of the DC offset correction device of the present invention will be described below by taking a radio frequency signal receiver using the DC offset correction device of the present invention as an example. It should be noted that the embodiments disclosed below are intended to illustrate rather than limit the scope of application of the present invention.

Please refer to FIG. 1 , which is a simplified partial block diagram of a signal receiver (receiver) 100 applying the DC offset correction device of the present invention. The signal receiver 100 includes a pre-stage circuit 110 and a gain stage 120 . In a receiver using a direct conversion architecture, the pre-stage circuit 110 usually includes a mixer for reducing the frequency of the received signal to the baseband, but in the present invention , the pre-stage circuit 110 may also be another gain stage circuit. As shown in FIG. 1, the gain stage 120 is a single-end gain circuit, and its gain is determined by the resistance values _R2 and _R1 of the resistors 124 and 122, and the bandwidth of the gain stage 120 is ) is determined by the resistance value R ₂ of the resistor 124 and the capacitance value C ₂ of the capacitor 126 .

In this embodiment, the DC offset correction device of the present invention includes a control circuit 130, a current-type digital-to-analog converter (current DAC) 140, and a current-to-current (current-to-current, I-to- 1) Converter 150. As is well known in the industry, even if there is no input signal at the input end of the pre-stage circuit 110, some DC bias voltage (DC bias) may be induced at the output end, which is the so-called DC offset (DC offset) phenomenon. Since the subsequent gain stage 120 will further amplify the DC offset of the front-stage circuit 110 , it may cause saturation of the latter-stage circuit and affect the performance of the circuit. In the DC offset correction device of the present invention, the control circuit 130 generates an n-bit digital control signal according to the DC offset of the output signal of the gain stage 120 . The current-mode digital-to-analog converter 140 generates a current signal according to the digital control signal. The current-to-current converter 150 scales down the current signal to generate a compensation signal to reduce the DC offset of the output signal of the gain stage 120 .

The DC offset correction device of the present invention uses the current-to-current converter 150 to reduce the scale of the current signal. In addition to improving the accuracy of the correction, it can also reduce the requirement for the output signal resolution of the current-type digital-to-analog converter 140. , thereby reducing the circuit cost of the current-mode digital-to-analog converter 140 . The operation of the DC offset correction device of the present invention will be further described below.

As mentioned above, the control circuit 130 generates an n-bit digital control signal according to the DC offset of the output signal of the gain stage 120 . In a preferred embodiment, the control circuit 130 further includes a comparing circuit 132 and a processor 134 for generating the n-bit digital control signal. The comparison circuit 132 is used to compare the output signal of the gain stage 120 with a reference level, which can be achieved by a comparator, a limiter, or an analog-to-digital converter (ADC). accomplish. In a preferred embodiment, the comparison circuit 132 compares the output signal of the gain stage 120 with the reference level when there is no input signal from the previous stage circuit 110 . Generally speaking, at this time, the expected value of the output signal level of the gain stage 120 is zero (that is, the DC offset value is zero), so the reference level can be set to zero.

The processing unit 134 will perform a binary search operation (binary search) according to the comparison result of the comparison circuit 132, and set the bit-by-bit gradually from the highest bit (MSB) to the lowest bit (LSB). Bit value of the digital control signal. Whenever the processing unit 134 finishes setting a bit value of the digital control signal, the current-mode digital-to-analog converter 140 correspondingly adjusts the magnitude of the output current signal. Before the processing unit 134 sets the next bit value of the digital control signal, the output current of the current-mode digital-to-analog converter 140 will remain constant. After the processing unit 134 of the control circuit 130 finishes setting all the bit values of the digital control signal, the current signal output by the current-mode digital-to-analog converter 140 will maintain the final value.

In the framework of the DC offset correction device of the present invention, the processing unit 134 can adjust the way of setting the digital control signal according to the different types of the current-mode digital-to-analog converter 140 .

其中I₀为一常数。实际操作上，亦可将电流型数字至模拟转换器140当中的各电流源皆设计成提供负向电流。在此情况下，当{a_n-1，...，a₁，a₀}均设定为1时，电流型数字至模拟转换器140所输出的总电流大小将会是

由上述可知，在图2的实施例中，电流型数字至模拟转换器140只会输出正向电流或负向电流的其中之一。For example, FIG. 2 shows a schematic diagram of a first embodiment of the current-mode digital-to-analog converter 140 in FIG. 1 . In FIG. 2, the digital control signal output by the processing unit 134 can be represented as a control byte {a _n-1 ,..., a ₁ , a ₀ }, where a _n-1 corresponds to the digital The most significant bit (MSB) of the control signal, while a ₀ corresponds to the least significant bit (LSB). In one embodiment, the processing unit 134 can gradually set the values a _m of each bit of the digital control signal to 0 or 1, so that the current source digital-to-analog converter 140 can control the corresponding current sources CS _m accordingly. Switch SW _m to adjust the magnitude of the total output current, where m=0, 1, . . . , n-1. In this embodiment, when a control bit value _am is 1, the current-mode digital-to-analog converter 140 will control a corresponding switch SW _m to form a path (close); when the control bit value _am is 0, The current-mode digital-to-analog converter 140 controls the switch SW _m to form an open circuit (open). In this way, when _{ a _{n- 1 ,} . When _-1 , ..., a ₁ , a ₀ } are all set to 1, the total current output by the current-mode digital-to-analog converter 140 is

Where I ₀ is a constant. In practice, each current source in the current-mode digital-to-analog converter 140 can also be designed to provide negative current. In this case, when {a _{n− 1 ,} .

It can be seen from the above that, in the embodiment of FIG. 2 , the current-mode digital-to-analog converter 140 can only output one of the positive current and the negative current.

In addition, the architecture of the current-mode digital-to-analog converter 140 can also be designed to provide positive or negative output current, so as to expand the range of applications. For example, FIG. 3 shows a schematic diagram of a second embodiment of the current-mode digital-to-analog converter 140 in FIG. 1 . As shown in FIG. 3 , the current-mode digital-to-analog converter 140 includes a current source CS' providing negative current, and multiple current sources CS ₀ -CS _n-1 providing positive current. In one embodiment, the initial values of the control bytes {a _n-1 , ..., a ₁ , a ₀ } are all set to 0, and the processing unit 134 will sequentially set and adjust each bit of the digital control signal . When processing a certain bit a _m , the value of the bit a _m will be set to 1 first, and then the bit a _m will be set to 0 or 1 according to the comparison result of the comparison circuit 132, so that the current type digital to Accordingly, the analog converter 140 controls the switch SW _m corresponding to the current source CS _m to adjust the magnitude of the total output current. In this embodiment, it is also assumed that when a control bit value _am is 1, the current-mode digital-to-analog converter 140 will control a corresponding switch SW _m to form a path; when the control bit value _am is 0, the current The digital-to-analog converter 140 controls the switch SW _m to form an open circuit. In this way, the total current output by the current-mode digital-to-analog converter 140 can be expressed as $-2^{\mathrm{no}-1}\&Center\; Dot;I_0+\underset{m=0}{\overset{\mathrm{no}-1}{\mathrm{\Σ}}}{a}_m\·2^m\&Center\; Dot;I_0,$ Where I ₀ is a constant. In practical applications, the architecture of the embodiment shown in FIG. 3 can also be changed to a combination of a current source providing forward current and a plurality of current sources providing negative current. In this case, the total current output by the current-mode digital-to-analog converter 140 will be changed to $2^{\mathrm{no}-1}\·I_0-\underset{m=0}{\overset{\mathrm{no}-1}{\mathrm{\Σ}}}{a}_m\·2^m\·I_0.$

而当{a_n-1，...，a₁，a₀}均设定为-1时，电流型数字至模拟转换器140所输出的总电流大小则为

FIG. 4 is a schematic diagram of a third embodiment of the current mode digital-to-analog converter 140 of the present invention. As shown in FIG. 4 , the current-mode digital-to-analog converter 140 includes a plurality of current sources CS' ₀ -CS' _n-1 providing negative currents, and a plurality of current sources CS ₀ -CS _n providing positive currents. _-1 . In a preferred embodiment, the processing unit 134 can set each bit value of the digital control signal {a _n-1 , ..., a ₁ , a ₀ } to 1 or -1 step by step, so as to control the switches respectively The switching states of SW ₀ -SW _n-1 and SW' ₀ -SW' _n-1 , and then respectively control multiple current sources CS ₀ -CS _n-1 providing positive current and multiple current sources providing negative current Whether CS' ₀ -CS' _n-1 contribute to the final total current value. In actual operation, the initial values of each bit can be set to 0, so that all the switches SW ₀ -SW _n-1 , SW' ₀ -SW' _n-1 of the current-mode digital-to-analog converter 140 are kept in the disconnected state, Therefore, the initial total current value output by the current-mode digital-to-analog converter 140 is zero. For example, when the value a _n-1 of the most significant bit (MSB) is set to 1, the current-mode digital-to-analog converter 140 will control the switch SW _n-1 to form a path (close), and control the switch SW' _{n -1} forms an open circuit (open) to provide a forward current 2 ^n-1 *I ₀ . When the bit value a ₁ is set to -1, the current-mode digital-to-analog converter 140 controls the switch SW ₁ to form an open circuit, and controls the switch SW' ₁ to form a path to provide a negative current 2 ¹ *I ₀ , and so on for the rest. In other words, in this embodiment, when the _processing unit 134 sets {a _{n-1 ,} . for

And when {a _n-1 , . . . , a ₁ , a ₀ } are all set to -1, the total current output by the current-mode digital-to-analog converter 140 is

In practice, in addition to the aforementioned embodiments, the processing unit 134 can also be implemented by using various known successive approximation registers (Successive Approximation Register, SAR), or software that can perform a binary search algorithm. It is well known, so it will not be repeated here.

Please refer to FIG. 1 again. In a preferred embodiment of the present invention, the current-to-current converter 150 further includes a current-to-voltage (current-to-voltage, I-to-V) converter 152, which is electrically connected to the digital to the analog converter 140 ; and a compensation signal generator 154 electrically connected to the current-to-voltage converter 152 and the gain stage 120 . The current-to-voltage converter 152 is used to convert the current signal output by the current-mode digital-to-analog converter 140 from a current domain to a voltage domain and amplify it. The compensation signal generator 154 is used to convert the voltage signal back to the current domain and at the same time reduce the signal to generate a compensation signal to reduce the DC offset of the output signal of the gain stage 120 . In practice, the compensation signal generator 154 can be realized by a voltage-to-current (V-to-I) converter, for example, the compensation signal generator 154 can be a resistor.

It should be noted here that the function of the current-to-current converter 150 of the present invention is not simply to convert the current signal output by the current-mode digital-to-analog converter 140 from the current domain to the voltage domain, and then convert back to the current domain. In detail, the current-to-current converter 150 of the present invention first uses the current-to-voltage converter 152 to convert the signal type to the voltage domain while amplifying the scale of the signal, and then uses the compensation signal generator 154 While converting the signal type back to the current domain, the scale of the signal is reduced, so that the present invention has the ability to finely adjust the magnitude of the compensation signal. For example, in a preferred embodiment, the compensation signal generator 154 can be realized by a resistor unit. Changing the resistance value of the compensation signal generator 154 can adjust the scale of the compensation signal. Generally speaking, the higher the resistance value of the compensation signal generator 154 is, the smaller the scale of the compensation signal is, and the higher the resolution of the fine-tuning compensation signal is in the present invention.

The purpose of the current-to-current converter 150 of the present invention is to make the scale of the compensation signal output by the compensation signal generator 154 smaller than the scale of the current signal originally output by the current-mode digital-to-analog converter 140 . In other words, through the aforementioned conversion process, the resolution of the compensation signal is higher than the current signal originally output by the current-mode digital-to-analog converter 140 . The resolution of the compensation signal can be adjusted by changing the extent to which the current-to-voltage converter 152 amplifies the signal, or the voltage-to-current conversion characteristic of the compensation signal generator 154 . In addition, increasing the current to the extent that the voltage converter 152 amplifies the signal, and cooperating with the compensation signal generator 154 with an appropriate equivalent resistance value, can control the resolution of the compensation signal more precisely.

On the other hand, since the current-to-current converter 150 of the present invention can increase the resolution of the compensation signal, the requirement on the resolution of the current-mode digital-to-analog converter 140 can be reduced. In this way, the circuit cost or circuit area required by the current-mode digital-to-analog converter 140 can be effectively reduced.

In practice, a switch (not shown) can also be provided on the signal path from the gain stage 120 to the control circuit 130, so that the processing unit 134 can control the switch to set all the bit values of the digital control signal. The signal feedback path is set to an open state. This architecture is applicable to all the following embodiments, and for the sake of brevity, the description will not be repeated below.

Please note that the gain stage 120 shown in FIG. 1 is only a schematic circuit. In application, the gain stage 120 can be a filter, a programmable gain amplifier (PGA) and other different gain circuits. Even, the structure of the DC offset correction device of the present invention can also be used to simultaneously correct the DC offsets of multiple gain circuits. For example, FIG. 5 is a simplified partial block diagram of a second embodiment of a signal receiver applying the DC correction device of the present invention. A signal receiver 500 in FIG. 5 is very similar to the aforementioned signal receiver 100 , the only difference is that the gain stage 520 of the signal receiver 500 includes multiple gain circuits. In practical applications, the multiple gain circuits in the gain stage 520 may be gain circuits with different functions. Components with the same numbers in FIG. 5 and FIG. 1 have substantially the same implementation and operation methods, so details will not be repeated.

Please refer to FIG. 6 , which is a simplified partial block diagram of a third embodiment of a signal receiver applying the DC correction device of the present invention. As shown in FIG. 6 , a signal receiver 600 includes a pre-stage circuit 610 and a differential gain stage 620 . The DC offset correction device of the present invention includes a control circuit 630 , a current-mode digital-to-analog converter 640 , and a current-to-current converter 650 . Wherein, the control circuit 630 further includes a comparison circuit 632 and a processing unit 634 , and the current-to-current converter 650 further includes a current-to-voltage converter 652 and a compensation signal generator 654 . Generally speaking, the resistance value of _the resistor _R1A in the differential gain stage 620 will be the same as that of the resistor R1B, the resistance value of the resistor _R2A will be the same as that of the resistor _R2B , and the capacitance of the capacitor _C2A will be the same as that of the capacitor C _2B is the same.

Since the gain stage 620 in this embodiment is a differential gain circuit, the comparator circuit 632 of the control circuit 630 compares the two differential output signals of the gain stage 620 to detect the DC voltage of the gain stage 620 during operation. Offset situation. The operation modes of the processing unit 634 and the current-mode digital-to-analog converter 640 are substantially the same as those of the processing unit 134 and the current-mode digital-to-analog converter 140 in FIG.

Similarly, the current-to-current converter 650 first uses the current-to-voltage converter 652 to convert the output signal of the current-mode digital-to-analog converter 640 from the current domain to the voltage domain and simultaneously amplifies its scale, and then uses the compensation signal to generate Converter 654 converts the signal type back to the current domain and downscales the signal. As mentioned above, such a conversion method can make the resolution of a compensation signal output by the compensation signal generator 654 higher than that of the current signal originally output by the current-mode digital-to-analog converter 640 . Similarly, in practice, the compensation signal generator 654 can be realized by a voltage-to-current (V-to-I) converter. For example, the compensation signal generator 654 can be realized by a resistor unit, and the resolution of the compensation signal can be adjusted by changing the degree of amplification of the signal by the current-to-voltage converter 652 or the resistance value of the compensation signal generator 654 . The compensation signal output by the compensation signal generator 654 is used to compensate the signal of one of the two differential input paths of the gain stage 620 to correct the DC offset of the gain stage 620 .

Please note that the gain stage 620 shown in FIG. 6 is only a schematic circuit. In practice, the gain stage 620 can be various types of differential gain circuits. Even, the structure of the DC offset correction device of the present invention can also be used to simultaneously correct the DC offsets of multiple differential gain circuits. For example, FIG. 7 is a simplified partial block diagram of a fourth embodiment of a signal receiver applying the DC correction device of the present invention. In a signal receiver 700 shown in FIG. 7 , its gain stage 720 includes a plurality of differential gain circuits. In practical applications, the multiple gain circuits in the gain stage 720 can be differential gain circuits with different functions. Components with the same numbers in FIG. 7 and FIG. 6 have substantially the same implementation and operation methods, and will not be repeated here.

FIG. 8 is a simplified partial block diagram of a fifth embodiment of a signal receiver applying the DC correction device of the present invention. As shown in FIG. 8 , a signal receiver 800 includes a pre-stage circuit 810 and a differential gain stage 820 . The DC offset correction device of the present invention includes a control circuit 830 , a current-mode digital-to-analog converter 840 , a first current-to-current converter 850 , and a second current-to-current converter 860 . Likewise, the gain stage 820 can be various types of differential gain circuits or include multiple differential gain circuits. The control circuit 830 includes a comparison circuit 832 and a processing unit 834 . The first current-to-current converter 850 includes a current-to-voltage converter 852 and a compensation signal generator 854 , and the second current-to-current converter 860 includes a current-to-voltage converter 862 and a compensation signal generator 864 . The comparison circuit 832 of the control circuit 830 is used to compare the two differential output signals of the gain stage 820 to detect the DC offset of the gain stage 820, and the processing unit 834 will generate a digital control signal according to the comparison result of the comparison circuit 832 . As mentioned above, the digital control signal is used to control the current-mode digital-to-analog converter 840 to generate a current signal. Likewise, the first current-to-current converter 850 utilizes the current-to-voltage converter 852 and the compensation signal generator 854 to convert the current signal into a first compensation signal with higher resolution to compensate the gain stage 820 Signal from one of the two differential input paths.

In an actual circuit, the first current-to-current converter 850 itself may also cause a slight DC offset. The DC offset caused by the first current-to-current converter 850 is usually very small, but may still cause an offset in the effective operating range of the subsequent circuits of the gain stage 820 (eg, analog-to-digital converter, ADC). Therefore, in this embodiment, the second current-to-current converter 860 is used to output a second compensation signal to the other path of the two differential input paths of the gain stage 820 according to a reference current, so as to offset the first current-to-current The DC offset induced by the current converter 850 . In practice, the value of the reference current can be zero. In order to minimize the DC offset caused by the first current-to-current converter 850, in a preferred embodiment, the current-to-voltage converter 862 in the second current-to-current converter 860 is connected with the first current-to-current converter 862 The current-to-voltage converter 852 in the current converter 850 has the same current-to-voltage conversion characteristic. In addition, the compensation signal generator 864 also has the same voltage-to-current conversion characteristics as the compensation signal generator 854 . For example, the compensation signal generator 864 and the compensation signal generator 854 can be respectively realized by using two resistance units with the same resistance value.

Please refer to FIG. 9 , which is a simplified partial block diagram of a sixth embodiment of a signal receiver applying the DC correction device of the present invention. In this embodiment, a signal receiver 900 includes a pre-stage circuit 910 and a differential gain stage 920 . The DC offset correction device of the present invention includes a control circuit 930, a first current-mode digital-to-analog converter 942, a second current-mode digital-to-analog converter 944, a first current-to-current converter 950, and a Second current-to-current converter 960 . Similar to the aforementioned fifth embodiment, the control circuit 930 includes a comparison circuit 932 and a processing unit 934; the first current-to-current converter 950 includes a current-to-voltage converter 952 and a compensation signal generator 954; and the second The current-to-current converter 960 includes a current-to-voltage converter 962 and a compensation signal generator 964 .

From the description of the foregoing embodiments, it can be seen that if the current-to-voltage conversion characteristic of the current-to-voltage converter 952 is the same as that of the current-to-voltage converter 962, and the voltage-to-current conversion characteristic of the compensation signal generator 954 is also the same as that of the compensation signal generator 964 , the DC offsets caused by the first current-to-current converter 950 and the second current-to-current converter 960 can be canceled to a minimum. Likewise, the compensation signal generators 954 and 964 can be implemented by two voltage-to-current converters with the same voltage-to-current conversion characteristics, for example, by two resistor units with the same resistance value.

The difference from the aforementioned embodiment of FIG. 8 is that two current-mode digital-to-analog converters (942 and 944) are provided in this embodiment, and the processing unit 934 of the control circuit 930 will, according to the comparison result of the comparison circuit 932, A first control signal and a second control signal are generated to control the magnitudes of currents output by the current-mode digital-to-analog converters 942 and 944 respectively. The current-mode digital-to-analog converter 942 outputs a first current signal to the first current-to-current converter 950 according to the first control signal; and the current-mode digital-to-analog converter 944 outputs a first current signal according to the second control signal. The second current signal is sent to the second current-to-current converter 960 . Since gain stage 920 is a differential gain stage, adding a specific amount of current to one of the two differential input paths of gain stage 920 has the same effect as from the other input path of gain stage 920 reduce that particular amount of current. Based on this feature, when the processing unit 934 sets the first and second control signals, it can simply set the corresponding bit values in the two control signals to be opposite.

For example, assuming that the current-mode digital-to-analog converters 942 and 944 are both implemented in the embodiment shown in FIG. 2, when the processing unit 934 sets the MSB of the first control signal to 1, then Simply set the highest bit value of the second control signal to 0; on the contrary, when the processing unit 934 sets the highest bit value of the first control signal to 0, the highest bit value of the second control signal can simply be The value is set to 1. In addition, the actual operation of the DC offset correction device of the present invention does not limit the implementation of the current-mode digital-to-analog converter 942 to be the same as that of the current-mode digital-to-analog converter 944 . Any architecture that uses two current-mode digital-to-analog converters in conjunction with two current-to-current converters to correct the DC offset of the output signal of the gain stage falls within the scope of the embodiments of the present invention.

Please note that the differential gain stage in the foregoing embodiments is not limited to the differential gain circuit of the OP-amplifier architecture. For example, FIG. 10 is a schematic diagram of another type of differential gain stage 1000 . The aforementioned DC offset correction device of the present invention can also electrically connect the compensation signal output by the current-to-current converter to the differential input terminals A, A' or load terminals B, B' of the differential gain stage 1000 to The DC offset of the output signal of the differential gain stage 1000 is corrected.

From the descriptions of the above-mentioned embodiments, it can be seen that the structure of the DC offset correction device of the present invention is to convert the current signal with a lower resolution output by the original current-type digital-to-analog converter through the operation of the current-to-current converter, Convert to the voltage domain, amplify, and convert back to the current domain to obtain a higher resolution, steady-state compensation current. In this way, the requirement on the resolution of the output signal of the current-mode digital-to-analog converter can be reduced, thereby saving its circuit cost and circuit area.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (23)

1. DC drift correction apparatus is used for proofreading and correct the direct current offset situation of a gain stage output signal, it is characterized in that this DC drift correction apparatus includes:

One digital to analog converter is electrically connected on this gain stage, is used for producing a current signal according to the direct current offset situation of this gain stage output signal; And

One electric current is electrically connected on this digital to analog converter and this gain stage to current converter, is used for this current signal is dwindled processing to produce a compensating signal, to reduce the direct current offset situation of this gain stage output signal.

2. according to the described DC drift correction apparatus of claim 1, it is characterized in that this electric current to current converter includes in addition:

One electric current is electrically connected on this digital to analog converter to electric pressure converter, is used for this current signal is converted to a voltage signal; And

One compensation signal generator is electrically connected on this electric current to electric pressure converter and this gain stage, is used for producing this compensating signal according to this voltage signal.

3. according to the described DC drift correction apparatus of claim 2, it is characterized in that this compensation signal generator is a voltage-to-current converter.

4. according to the described DC drift correction apparatus of claim 3, it is characterized in that this voltage-to-current converter is a resistance unit.

5. according to the described DC drift correction apparatus of claim 1, it is characterized in that, this device includes a control circuit in addition, be electrically connected between this gain stage and this digital to analog converter, be used for relatively an output signal and a reference level of this gain stage, and produce a control signal according to result relatively;

Wherein this gain stage is a monofocal gain stage, and this digital to analog converter produces this current signal according to this control signal.

6. according to the described DC drift correction apparatus of claim 1, it is characterized in that, this device includes a control circuit in addition, be electrically connected between this gain stage and this digital to analog converter, be used for two signals of differential type output of this gain stage relatively, and produce a control signal according to result relatively;

Wherein this gain stage is a differential type gain stage, and this digital to analog converter produces this current signal according to this control signal.

7. DC drift correction apparatus is used for proofreading and correct the direct current offset situation of a gain stage output signal, it is characterized in that this DC drift correction apparatus includes:

One digital to analog converter is electrically connected on this gain stage, is used for producing a current signal according to the direct current offset situation of this gain stage output signal;

One first electric current is electrically connected on this digital to analog converter and this gain stage to current converter, is used for this current signal is dwindled processing to produce one first compensating signal; And

One second electric current is electrically connected on this digital to analog converter and this gain stage to current converter, is used for producing one second compensating signal according to a reference current;

Wherein this first, second compensating signal is the direct current offset situation that is used for reducing this gain stage output signal.

8. according to the described DC drift correction apparatus of claim 7, it is characterized in that this first electric current to current converter includes in addition:

One first electric current is electrically connected on this digital to analog converter to electric pressure converter, is used for this current signal is converted to one first voltage signal; And

One first compensation signal generator is electrically connected on this first electric current to electric pressure converter and this gain stage, is used for producing this first compensating signal according to this first voltage signal.

9. according to the described DC drift correction apparatus of claim 8, it is characterized in that this second electric current to current converter includes in addition:

One second electric current is used for producing one second voltage signal according to this reference current to electric pressure converter; And

One second compensation signal generator is electrically connected on this second electric current to electric pressure converter and this gain stage, is used for producing this second compensating signal according to this second voltage signal.

10. according to the described DC drift correction apparatus of claim 9, it is characterized in that this first or second compensation signal generator is a voltage-to-current converter.

11., it is characterized in that this voltage-to-current converter is a resistance unit according to the described DC drift correction apparatus of claim 10.

12., it is characterized in that this first and second compensation signal generator is all a resistance unit according to the described DC drift correction apparatus of claim 11.

13., it is characterized in that this first and second compensation signal generator has identical resistance value according to the described DC drift correction apparatus of claim 12, and this first and second electric current to electric pressure converter has identical electric current to the voltage transitions characteristic.

14., it is characterized in that the current value of this reference current is zero according to the described DC drift correction apparatus of claim 7.

15. according to the described DC drift correction apparatus of claim 7, it is characterized in that, this device includes a control circuit in addition, be electrically connected between this gain stage and this digital to analog converter, be used for two signals of differential type output of this gain stage relatively, and produce a control signal according to result relatively;

Wherein this digital to analog converter produces this current signal according to this control signal.

16. a DC drift correction apparatus is used for proofreading and correct the direct current offset of a gain stage, it is characterized in that, this DC drift correction apparatus includes:

One first digital to analog converter is electrically connected on this gain stage, is used for producing one first current signal according to the direct current offset situation of this gain stage output signal;

One first electric current is electrically connected on this first digital to analog converter and this gain stage to current converter, is used for this first current signal is dwindled processing to produce one first compensating signal;

One second digital to analog converter is electrically connected on this gain stage, is used for producing one second current signal according to the direct current offset situation of this gain stage output signal; And

One second electric current is electrically connected on this second digital to analog converter and this gain stage to current converter, is used for this second current signal is dwindled processing to produce one second compensating signal;

Wherein this first, second compensating signal is the direct current offset situation that is used for reducing this gain stage output signal.

17., it is characterized in that this first electric current to current converter includes in addition according to the described DC drift correction apparatus of claim 16:

One first electric current is electrically connected on this first digital to analog converter to electric pressure converter, is used for this first current signal is converted to one first voltage signal; And

One first compensation signal generator is electrically connected on this first electric current to electric pressure converter and this gain stage, is used for producing this first compensating signal according to this first voltage signal.

18., it is characterized in that this second electric current to current converter includes in addition according to the described DC drift correction apparatus of claim 17:

One second electric current is electrically connected on this second digital to analog converter to electric pressure converter, is used for producing one second voltage signal according to this second current signal; And

One second compensation signal generator is electrically connected on this second electric current to electric pressure converter and this gain stage, is used for producing this second compensating signal according to this second voltage signal.

19., it is characterized in that this first or second compensation signal generator is a voltage-to-current converter according to the described DC drift correction apparatus of claim 18.

20., it is characterized in that this voltage-to-current converter is a resistance unit according to the described DC drift correction apparatus of claim 19.

21., it is characterized in that this first and second compensation signal generator is all a resistance unit according to the described DC drift correction apparatus of claim 20.

22., it is characterized in that this first and second compensation signal generator has identical resistance value according to the described DC drift correction apparatus of claim 21, and this first and second electric current to electric pressure converter has identical electric current to the voltage transitions characteristic.

23. according to the described DC drift correction apparatus of claim 16, it is characterized in that, this device includes a control circuit in addition, be electrically connected between this gain stage and this first and second digital to analog converter, be used for two signals of differential type output of this gain stage relatively, and produce one first control signal and one second control signal that should direct current offset according to result relatively;

Wherein this first digital to analog converter produces this first current signal according to this first control signal, and this second digital to analog converter produces this second current signal according to this second control signal.

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