CN104734645A - Method for eliminating variable gain amplifier circuit DC offset by adopting current DAC - Google Patents

Abstract

The invention discloses a method for eliminating the DC offset of a variable gain amplifier circuit by using a current DAC. The differential input terminals of the variable gain amplifier are short-circuited, and the output signal of the variable gain amplifier circuit is the DC offset voltage. The device performs sampling detection and analog-to-digital conversion on the DC offset voltage to obtain the digital value of the DC offset voltage. The improved bit-by-bit comparison algorithm is used to process the digital value of the DC offset voltage to obtain the control word for controlling the current DAC, and finally through the current DAC. Feedback calibration is performed on the input of the corresponding variable gain amplifier to cancel the dc offset voltage. The invention improves the bit-by-bit calibration method in the traditional digital-assisted DC offset elimination technology, and uses an analog-to-digital converter to directly detect the DC offset voltage, thereby increasing the calibration speed.

Description

A Method of Using Current DAC to Eliminate DC Offset of Variable Gain Amplifier Circuit

technical field

The invention relates to a method for eliminating DC offset of a variable gain amplifier circuit by using a current DAC, which is an important technology applied in an intermediate frequency amplifier of a wireless transceiver, and relates to an intermediate frequency amplification technology and a digital baseband technology in the field of wireless communication.

Background technique

In CMOS processes, noise and offset are the main factors that limit the accuracy of analog integrated circuits. In fact, as the channel length becomes smaller, the offset will become more serious, so the offset is the dominant factor that limits the accuracy. Offset is caused by mismatches between identically placed transistors. Especially in the design process of the differential variable gain amplifier, due to the offset voltage caused by the mismatch of the transistor, when the gain of the amplifier is large, the DC offset voltage equivalent to the input of the amplifier will be amplified, thus making the high-gain op amp produce a comparative A large error, even when the offset is large, will annihilate the effective signal, resulting in the blockage of the signal path. The offset of a general circuit is defined by the input offset voltage: the difference between the input voltage at both ends when the output voltage is zero. In a two-terminal amplifier, the offset voltage is usually on the millivolt level, and in a CMOS process, the offset voltage may increase by at least a factor of 10. The variable gain amplifier usually has a higher gain, so how to effectively eliminate the offset voltage of the variable gain amplifier is an important issue that must be considered in circuit design.

There are many ways to eliminate DC offset, such as feedback and feedforward, switched capacitors, and digital correction. The performance of the DC offset cancellation technology can be evaluated from the following indicators: the establishment time of the DC offset, that is, the time required for the DC component of the output signal to stabilize to a certain accuracy; the attenuation degree of the DC offset, that is, the DC component of the output signal and the input signal The ratio of the DC component; circuit power consumption, area, stability, etc. The simplest way to eliminate DC offset is AC coupling: place a large capacitor between two circuits to achieve the purpose of blocking DC and AC. This method is relatively simple to implement, but when the circuit works at low frequencies, a large capacitor is required to attenuate low AC signals. If a large DC blocking capacitor is implemented on-chip, it will occupy a large area. In some circuits, circuits with high-pass characteristics are used to replace direct AC coupling. In addition, considering the large area occupied by large resistors and capacitors, MOS transistors are used to realize capacitors and resistors in some circuits. Another method is to use feedback vanishing tone. The basic principle is to connect a low-pass negative feedback loop in parallel on the forward amplification path, so as to realize the high-pass characteristic of the closed-loop transfer function. The traditional analog DC offset cancellation technology needs to use a large capacitor and has a very slow settling time. In addition, the feedback method is easy to cause stability problems of the circuit.

Therefore, in some current circuit designs, the technology of digitally assisted DC offset elimination is mainly used. The basic process of the digital-assisted calibration method is: first, short the differential input of the amplifier, detect the output offset voltage of the variable gain amplifier, then calculate the offset calibration value through a successive comparison algorithm, and finally eliminate the offset through a calibration DAC . The DC offset cancellation circuit of this method occupies a small chip area and the offset of each gain stage can be calibrated. Among them, comparing the output offset voltage is usually achieved by using a comparator, which has relatively high requirements on the comparator, and requires a comparator with a small offset to obtain accurate calibration. In the traditional digital-assisted DC offset calibration algorithm, since the calibration DAC used is a binary DAC, if an error occurs in the calibration of a DAC, it will be difficult to recalibrate the offset in subsequent calibrations. In some literatures, a sub-binary DAC is used, that is, the weight of each bit of the DAC is less than two. This can effectively prevent calibration errors, but the offset voltage of DAC calibration with the same number of bits is small.

Contents of the invention

Purpose of the invention: In order to eliminate the influence of the DC offset voltage on the performance of the variable gain amplifier, the present invention provides a method for eliminating the DC offset of the variable gain amplifier circuit by using a current DAC, which can realize digital automatic DC offset calibration in a relatively short period of time; The invention adopts an improved step-by-step calibration algorithm to control and calibrate the DAC to eliminate the equivalent input offset voltage of the variable gain amplifier; high speed.

Technical scheme: in order to achieve the above object, the technical scheme adopted in the present invention is:

A method for eliminating the DC offset of a variable gain amplifier circuit by using a current DAC. The variable gain amplifier circuit has three amplification stages, that is, three variable gain amplifiers are connected in series to form a variable gain amplifier circuit. Each variable gain amplifier Both are connected to a current DAC for DC offset adjustment (ie calibration DAC), the output end of the variable gain amplifier circuit is connected to the input end of the analog-to-digital converter, and the output end of the analog-to-digital converter is connected to the DC offset elimination module for digital processing , the obtained digital control words are respectively connected to control each current DAC; the working process is: the differential input terminals of the variable gain amplifier circuit are short-circuited, the output signal of the variable gain amplifier circuit is the DC offset voltage, and the analog-to-digital converter is used to Sampling detection and analog-to-digital conversion of the DC offset voltage are performed to obtain the digital value of the DC offset voltage, and the improved bit-by-bit comparison algorithm is used to process the digital value of the DC offset voltage to obtain the control word of the control current DAC, and finally the corresponding The input terminal of the variable gain amplifier performs feedback calibration to eliminate the DC offset voltage; after the DC offset voltage is eliminated, the differential input terminal of the variable gain amplifier circuit is disconnected to amplify the AC signal, that is, the variable gain The amplifier circuit enters the normal amplification mode.

The current DAC has (N+1) current branches in total, wherein the currents from the second current branch to the (N+1)th current branch are increased by binary weighting, which are respectively I ₀ , 2×I ₀ , ..., 2 ⁿ ×I ₀ , ..., 2 ^(N-1) ×I ₀ , the current of the first current branch is I ₀ ; there are two current output ports of the current DAC, which are respectively connected to the corresponding variable gain amplifier The two ports of the differential input end of the current DAC, the current signals output by the two current output ports of the current DAC are respectively I _outn and I _outp ; the second current branch to the (N+1)th current branch are provided with a Each switch is composed of two NMOS transistors connected in parallel. For the (n+1)th current branch, the control signal of the two NMOS transistors is B[n] and the All the current branches using the control signal B[n] are directly connected to the first current and then output I _outn , using the All current branches of are connected to output I _outp , namely:

I _outn ＝2 ^N I ₀ -(B[0]I ₀ +2B[1]I ₀ +…+2 ^(N-1) B[N-1]I ₀ )

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; outp</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; ]</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ]</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ]</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span>$

Among them, B[0:N-1] is recorded as the control word of the current DAC; the calibration current that the current DAC flows into the variable gain amplifier is I _outn -I _outp , and the variation range of the calibration current is (-2 ^N I ₀ ,2 ^N I ₀ ), the precision of the change is I ₀ .

The improved bit-by-bit comparison algorithm is: adjust the control word of the current DAC bit by bit according to the currently detected DC offset voltage value of the analog-to-digital converter and the DC offset voltage value of the previous state: when the currently detected DC offset voltage is not in the When the analog-to-digital converter is within the detection range, compare and adjust bit by bit from the high bit to the low bit of the current DAC. First, adjust the variable gain amplifier of the first stage. After the adjustment is completed, adjust the variable gain amplifier of the second stage. After the adjustment is completed, adjust The third-stage variable gain amplifier; when the currently detected DC offset voltage is within the detection range of the analog-to-digital converter, it is directly adjusted by converting the currently detected DC offset voltage value and the gain value of the current variable gain amplifier circuit The control word of the current DAC realizes the rapid adjustment of the DC offset voltage;

Among them, the DC offset voltage value of the previous state is the DC offset voltage value of the previous state after the current DAC control word is changed; the basic process of comparing and adjusting bit by bit from the high bit to the low bit of the current DAC is: the initial control word of the current DAC is B [N-1:0]=<100...0>, that is, the highest bit is 1, and the remaining (N-1) bits are all low bits. At this time, the calibration current of variable gain amplifiers at all levels is 0; according to the currently detected DC offset voltage value and the DC offset voltage value of the previous state: If the current DC offset voltage value and the DC offset voltage value of the previous state are both within the detection range of the analog-to-digital converter, the DC offset voltage elimination calibration stops, and the current DAC At this time, the variable gain amplifier circuit can enter the normal amplification mode; if the current DC offset voltage value is lower than the detection range of the analog-to-digital converter, the DC offset voltage value of the previous state is higher than the modulus The detection range of the converter, the current control bit of the current DAC becomes high; if the current DC offset voltage value is higher than the detection range of the analog-to-digital converter, the DC offset voltage value of the previous state is lower than the detection range of the analog-to-digital converter , the current control bit of the current DAC becomes low; if the current DC offset voltage value is lower than the detection range of the analog-to-digital converter, the DC offset voltage value of the previous state is lower than the detection range of the analog-to-digital converter, and the current DAC’s The current control bit becomes high, and the previous control bit becomes high; if the current DC offset voltage value is higher than the detection range of the analog-to-digital converter, the DC offset voltage value of the previous state is higher than the detection range of the analog-to-digital converter, The current control bit of the current DAC becomes low, and the previous control bit becomes low; by comparing the current state with the previous state in the above way, the method of gradually changing one or two control bits can effectively solve the problem of DC offset voltage calibration. The misalignment and redundancy problems that occur during the process allow the DC offset voltage to be accurately calibrated.

Beneficial effects: The method for eliminating the DC offset of a variable gain amplifier circuit provided by the present invention improves the bit-by-bit calibration method in the traditional digital-assisted DC offset elimination technology, and uses an analog-to-digital converter to directly detect the DC offset voltage , improving the calibration speed; and the present invention adopts the digital-assisted DC offset elimination method, which can effectively reduce the layout area occupied by the chip; the DC offset elimination method of the present invention has accuracy and rapidity.

Description of drawings

Fig. 1 is the structural block diagram and the circuit DAC circuit diagram of the variable gain amplifier circuit that adopts the inventive method;

Figure 2 is a flow chart of comparing and adjusting bit by bit from the high bit to the low bit of the current DAC;

FIG. 3 is a process waveform of DC offset voltage elimination in different gain modes of the variable gain amplifier circuit adopting the method of the present invention.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings.

The method for eliminating the direct current offset of the variable gain amplifier circuit provided by the present invention adopts the digital auxiliary direct current offset voltage elimination technology. The digital-assisted DC offset voltage elimination technology uses the DC offset voltage output by the variable gain amplifier circuit to calibrate and eliminate the input terminal of the variable gain amplifier through the current DAC, and finally makes the DC offset voltage of the output signal of the variable gain amplifier circuit It can even reach zero in the acceptable range. During the calibration process, if the DC offset after the amplifier is too large, it will exceed the detection range of the analog-to-digital converter. Therefore, it is necessary to use a bit-by-bit comparison method in the process of eliminating the DC offset. The invention improves the bit-by-bit approximation algorithm of the traditional digital DC offset elimination technology, can effectively prevent the loss and redundancy of bits in the process of eliminating the DC offset, and enables the DC offset voltage to be effectively eliminated.

A method of eliminating the DC offset of a variable gain amplifier circuit by using a current DAC. As shown in Figure 1 and Figure 2, the variable gain amplifier circuit has three amplification stages, that is, three variable gain amplifiers are connected in series to form a variable gain amplifier circuit, each variable gain amplifier is connected to a current DAC for DC offset adjustment (ie calibration DAC), the output terminal of the variable gain amplifier circuit is connected to the input terminal of the analog-to-digital converter, and the output terminal of the analog-to-digital converter is connected to Input the DC offset elimination module for digital processing, and the obtained digital control words are respectively connected to each current DAC; the working process is: short the differential input terminals of the variable gain amplifier, and the output signal of the variable gain amplifier circuit is the DC offset voltage Voltage, use analog-to-digital converter to sample detection and analog-to-digital conversion of DC offset voltage, get the digital value of DC offset voltage, use the improved bit-by-bit comparison algorithm to process the digital value of DC offset voltage, and obtain the control current DAC Finally, the current DAC is used to perform feedback calibration on the input terminal of the corresponding variable gain amplifier to eliminate the DC offset voltage; after the DC offset voltage is eliminated, the differential input terminal of the variable gain amplifier circuit is disconnected to perform AC signal The amplification, that is, the variable gain amplifier circuit enters the normal amplification mode.

The current DAC has (N+1) current branches in total, wherein the currents from the second current branch to the (N+1)th current branch are increased by binary weighting, which are respectively I ₀ , 2×I ₀ , ..., 2 ⁿ ×I ₀ , ..., 2 ^(N-1) ×I ₀ , the current of the first current branch is I ₀ ; there are two current output ports of the current DAC, which are respectively connected to the corresponding variable gain amplifier The two ports of the differential input end of the current DAC, the current signals output by the two current output ports of the current DAC are respectively I _outn and I _outp ; the second current branch to the (N+1)th current branch are provided with a Each switch is composed of two NMOS transistors connected in parallel. For the (n+1)th current branch, the control signal of the two NMOS transistors is B[n] and the All the current branches using the control signal B[n] are directly connected to the first current and then output I _outn , using the All current branches of are connected to output I _outp , namely:

I _outn ＝2 ^N I ₀ -(B[0]I ₀ +2B[1]I ₀ +…+2 ^(N-1) B[N-1]I ₀ )

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; outp</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; ]</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ]</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ]</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span>$

Among them, B[0:N-1] is recorded as the control word of the current DAC; the calibration current that the current DAC flows into the variable gain amplifier is I _outn -I _outp , and the variation range of the calibration current is (-2 ^N I ₀ ,2 ^N I ₀ ), the precision of the change is I ₀ .

The improved bit-by-bit comparison algorithm is: adjust the control word of the current DAC bit by bit according to the currently detected DC offset voltage value of the analog-to-digital converter and the DC offset voltage value of the previous state: when the currently detected DC offset voltage is not in the When the analog-to-digital converter is within the detection range, compare and adjust bit by bit from the high bit to the low bit of the current DAC. First, adjust the variable gain amplifier of the first stage. After the adjustment is completed, adjust the variable gain amplifier of the second stage. After the adjustment is completed, adjust The third-stage variable gain amplifier; when the currently detected DC offset voltage is within the detection range of the analog-to-digital converter, it is directly adjusted by converting the currently detected DC offset voltage value and the gain value of the current variable gain amplifier circuit The control word of the current DAC realizes the fast adjustment of the DC offset voltage.

Among them, the DC offset voltage value of the previous state is the DC offset voltage value of the previous state after the current DAC control word is changed; the basic process of comparing and adjusting bit by bit from the high bit to the low bit of the current DAC is: the initial control word of the current DAC is B [N-1:0]=<100...0>, that is, the highest bit is 1, and the remaining (N-1) bits are all low bits. At this time, the calibration current of variable gain amplifiers at all levels is 0; according to the currently detected DC offset voltage value and the DC offset voltage value of the previous state: If the current DC offset voltage value and the DC offset voltage value of the previous state are both within the detection range of the analog-to-digital converter, the DC offset voltage elimination calibration stops, and the current DAC At this time, the variable gain amplifier circuit can enter the normal amplification mode; if the current DC offset voltage value is lower than the detection range of the analog-to-digital converter, the DC offset voltage value of the previous state is higher than the modulus The detection range of the converter, the current control bit of the current DAC becomes high; if the current DC offset voltage value is higher than the detection range of the analog-to-digital converter, the DC offset voltage value of the previous state is lower than the detection range of the analog-to-digital converter , the current control bit of the current DAC becomes low; if the current DC offset voltage value is lower than the detection range of the analog-to-digital converter, the DC offset voltage value of the previous state is lower than the detection range of the analog-to-digital converter, and the current value of the current DAC The control bit becomes high, and the last control bit becomes high; if the current DC offset voltage value is higher than the detection range of the analog-to-digital converter, the DC offset voltage value of the previous state is higher than the detection range of the analog-to-digital converter, and the current The current control bit of the DAC becomes low, and the previous control bit becomes low; by comparing the current state with the previous state in the above way, the method of gradually changing one or two control bits can effectively solve the DC offset voltage calibration process. The misalignment and redundancy problems that occur in the circuit allow the DC offset voltage to be accurately calibrated.

Figure 3 is the process waveform of the DC offset voltage elimination of the variable gain amplifier circuit using the method of the present invention in different gain modes, the circuit is gradually calibrated according to the value of the DC offset voltage, and the variable gain can be finally made by gradually calibrating from the figure The DC offset of the amplifying circuit is within an acceptable range, and the simulation results show that the DC offset signal at both ends of the differential can be calibrated to be less than 15mV in the end. When the gain mode is switched, the DC offset is readjusted. Since the DC offset is adjusted according to the sampling value of the analog-to-digital converter, the calibration speed of the DC offset is related to the sampling rate of the analog-to-digital converter, where the sampling rate is 16MHz. It can be seen from the simulation results that the calibration time of the DC offset can be controlled within 10us.

The technology of the present invention adopting the current DAC to eliminate the direct current offset of the variable gain amplifier improves the disadvantages of the traditional digital auxiliary direct current offset elimination technology, which is prone to errors and is inaccurate, and has the characteristics of fast and accurate response. Using binary weighted current DAC, it has the characteristics of large calibration range and high precision.

The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications are also possible. It should be regarded as the protection scope of the present invention.

Claims (3)

1. the method adopting current DAC to eliminate variable-gain amplification circuit DC maladjustment, it is characterized in that: this variable-gain amplification circuit has three amplifying stages, namely by three variable gain amplifier variable-gain amplification circuits in series, each variable gain amplifier all connects the current DAC that a DC maladjustment regulates, the input of the output access analog to digital converter of variable-gain amplification circuit, the output access DC maladjustment cancellation module of analog to digital converter carries out digital processing, and the digital control word obtained is each current DAC of connection control respectively; The course of work is: by the differential input end short circuit of variable-gain amplification circuit, the output signal of variable-gain amplification circuit is DC offset voltage, analog to digital converter is used to carry out sample detecting and analog-to-digital conversion to DC offset voltage, obtain the digital value of DC offset voltage, the digital value of successive appraximation algorithm to DC offset voltage improved is adopted to process, obtain the control word controlling current DAC, finally by current DAC, feedback calibration is carried out to the input of corresponding variable gain amplifier, to eliminate DC offset voltage; After DC offset voltage is eliminated, disconnected by the differential input end of variable-gain amplification circuit, can carry out the amplification of AC signal, also namely variable-gain amplification circuit enters normal amplification mode.

2. employing current DAC according to claim 1 eliminates the method for variable-gain amplification circuit DC maladjustment, it is characterized in that: described current DAC has (N+1) individual current branch, wherein second current branch presses binary weighting increase to the electric current of (N+1) individual current branch, is respectively I ₀, 2 × I ₀..., 2 ⁿ× I ₀..., 2 ^(N-1)× I ₀, the electric current of first current branch is I ₀; The current output terminal mouth of current DAC has two, is connected respectively to two ports of the differential input end of corresponding variable gain amplifier, and the current signal that two current output terminal mouths of note current DAC export is respectively I _outnand I _outp; Second current branch to (N+1) individual current branch is provided with a switch, each switch is formed by two NMOS tube in parallel, for (n+1) individual current branch, the control signal of two NMOS tube is B [n] and through inverter i is exported after adopting all current branch of control signal B [n] to be connected with first current DC _outn, adopt through inverter all current branch be connected after export I _outp, that is:

I _outn＝2 ^NI ₀-(B[0]I ₀+2B[1]I ₀+…+2 ^(N-1)B[N-1]I ₀)

$I_{\mathrm{outp}}=2^N{I}_0-(\stackrel{\&OverBar;}{B\left[0\right]}{I}_0+2\stackrel{\&OverBar;}{B\left[1\right]}{I}_0+...+2^{(N-1)}\stackrel{\&OverBar;}{B[N-1}{I}_0)$

Wherein, B [0:N-1] is designated as the control word of current DAC; The calibration current that current DAC flows into variable gain amplifier is I _outn-I _outp, the excursion of calibration current is (-2 ⁿi ₀, 2 ⁿi ₀), the precision of change is I ₀.

3. employing current DAC according to claim 2 eliminates the method for variable-gain amplification circuit DC maladjustment, it is characterized in that: the successive appraximation algorithm of described improvement is: the control word adjusting current DAC according to the DC offset voltage value of the current detection of analog to digital converter and the DC offset voltage value of laststate by turn: when the DC offset voltage of current detection is not in the detection range of analog to digital converter, adjust from a high position for current DAC to low level successive appraximation, first the variable gain amplifier of the first order is adjusted, adjust the variable gain amplifier of the rear adjustment second level, adjust the variable gain amplifier of the rear adjustment third level, when the DC offset voltage of current detection is in the detection range of analog to digital converter, converted by the DC offset voltage value of current detection and the yield value of current variable-gain amplification circuit, the control word of direct adjustment current DAC, realizes the rapid adjustment of DC offset voltage,

Wherein, the DC offset voltage value of the DC offset voltage value of laststate and the previous state of current DAC control word change; The basic process adjusted from a high position for current DAC to low level successive appraximation is: the initial control word of current DAC is B [N-1:0]=<100 ... 0>, namely highest order is 1, remaining (N-1) position is low level, and now the calibration current of variable gain amplifier at different levels is 0; According to the DC offset voltage value of current detection and the DC offset voltage value of laststate: if the DC offset voltage value of current DC offset voltage value and laststate is all in the detection range of analog to digital converter, DC offset voltage is eliminated calibration and is stopped, the control word of current DAC remains unchanged, and now variable-gain amplification circuit can enter normal amplification mode; If current DC offset voltage value is lower than the detection range of analog to digital converter, the DC offset voltage value of laststate is higher than the detection range of analog to digital converter, and the current control bit of current DAC becomes height; If current DC offset voltage value is higher than the detection range of analog to digital converter, the DC offset voltage value of laststate is lower than the detection range of analog to digital converter, and the current control bit of current DAC becomes low; If current DC offset voltage value is lower than the detection range of analog to digital converter, the DC offset voltage value of laststate is lower than the detection range of analog to digital converter, and the current control bit of current DAC becomes height, and a upper control bit becomes height; If current DC offset voltage value is higher than the detection range of analog to digital converter, the DC offset voltage value of laststate is higher than the detection range of analog to digital converter, and the current control bit of current DAC becomes low, and a upper control bit becomes low; Compare current state and laststate by the way, adopt the mode progressively changing or change two control bits, effectively can solve the dislocation and redundancy issue that occur in DC offset voltage calibration process, DC offset voltage is calibrated accurately.