CN1719611B

CN1719611B - Charge trapping non-volatile memory and method of operating the same

Info

Publication number: CN1719611B
Application number: CN200510075154.8A
Authority: CN
Inventors: 叶致锴
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2004-07-06
Filing date: 2005-06-08
Publication date: 2012-07-11
Anticipated expiration: 2025-06-08
Also published as: CN1719612A; CN1722445A; CN1722444B; CN1719611A; CN100573878C; CN1722444A; CN1719598A

Abstract

The invention relates to a multi-grid memory cell, which comprises a semiconductor body and a plurality of grids which are arranged on the semiconductor body in series. A charge storage structure on the semiconductor body includes a charge trapping region under a gate of the plurality of gates. First circuitry for conducting source and drain bias voltages to the semiconductor body in the memory cell row adjacent the first gate and adjacent the last gate. Second circuitry to conduct a gate bias voltage to the plurality of gates. Includes a continuous multiple gate channel region located below the plurality of gates in the memory cell row. The multiple-gate memory cell has a charge storage region between some or all of the gates.

Description

Charge trapping non-volatile memory and method of operation thereof

Technical field

The invention relates to a kind of integrated circuit non-volatility memory element, and particularly relevant for a kind of new memory cell and method of operation thereof.

Background technology

Electrically programmed and erasable non-volatility memory are technological; As have electrically can erasing and programmed ROM (electrically erasable and programmable read only memory of Charge Storage function; EEPROM) with fast flash memory bank (flash memory), used in various modern application.Some memory cell structures are used for as electrically erasing and programmed ROM and fast flash memory bank.Along with dwindling of integrated circuit size, for the expandability and the simplification of processing procedure, the memory cell structure with charge-trapping dielectric layers receives bigger concern gradually.Memory cell structure with charge-trapping dielectric layers for example comprises only reading memory (nitride read only memory of industrial called after silicon nitride; NROM), silicon-oxide-nitride--oxide-silicon (silicon-oxide-nitride-oxide-silicon; SONOS), metal-oxide-nitride-oxide-silicon (metal-oxide-nitride-oxide-silicon; MONOS) inject nitrogenize electron storage device with (programming by hot hole injection nitride electron storage, structure PHINES) of stylizing with the mat hot electron.It for example is to catch electric charge in the charge-trapping dielectric layers of silicon nitride to store data that these memory cell structures are utilized in.When trap negative charge, the critical voltage voltage of memory cell then can increase.Self charge is caught layer and is removed the critical voltage voltage that negative electrical charge then reduces memory cell.

Fig. 1 is the section of structure of the charge-trapping memory cell of a kind of SONOS type of convention.Substrate comprises the n as the

electrode

15,16 of source/drain ⁺Doped region, and at electrode 15, p doping channel region 17 between 16.The remainder of memory cell comprises the charge-trapping structure, and the charge-trapping structure comprises and is positioned at dielectric layer of the suprabasil end 14, is positioned at charge-trapping material 13 on the end dielectric layer 14, is positioned at the top dielectric layer 12 on the charge-trapping material 13 and is positioned at the grid 11 on the top dielectric layer 12.Typical top dielectric layer comprises that thickness is the silicon dioxide and the silicon oxynitride of 5～10 nanometers, or other similar high dielectric constant materials, for example comprises aluminium oxide (Al ₂O ₃).Dielectric layer of the typical end comprises that thickness is the silicon dioxide and the silicon oxynitride of 3～10 nanometers, or other similar high dielectric constant materials.For this kind of charge-trapping structure, typical charge-trapping material comprises that thickness is the silicon nitride of 3～9 nanometers, or other similar high dielectric constant materials, comprises silicon oxynitride, metal oxide such as aluminium oxide, hafnium oxide (HfO ₂) or other materials.The charge-trapping material can be charge-trapping material area or the particle that is interrupted, or continuous rete as shown in the figure.

For memory cell,

electrode

15,16 comes memory cell is read, stylizes and erases in bias arrangement as source/drain.The doped region that forms

electrode

15,16 generally comprises the impurity of implanted semiconductor substrate, with the conducting electrode of foundation with channel region 17 opposite conductive form.At at the diffusion of impurities that the step of implant impurity make to be implanted to the semiconductor-based end, and can limitation capability dwindling electrode 15, the length of passage between 16, or even use little shadow to shrink the minimum dimension that can reach.

Fig. 2 A and Fig. 2 B cause Fu Lenuohai to wear when to be convention with memory cell stylize paramount critical voltage state satisfying (Fowler-Nordheim tunneling) getting into a kind of bias arrangement in the charge-trapping structure from substrate.According to the configuration of known techniques, Fig. 2 A shows grid, source electrode, drain and suprabasil bias voltage Vg, Vs, Vd, Vb, and it has caused the electronics shown in Fig. 2 B to be worn then.

Fig. 3 is that (not-and, NAND) the SONOS type memory cell of type array structure institute arranged in series utilizes the memory cell that it is fixed that a kind of bias arrangement stylizes instead to reach grid in convention.In Fig. 3, memory cell array comprises n ⁺Doped region 20～26, selection grid SLG1 and SLG2 and character line WL ₁～WL ₄Charge storing structure 27～30 is positioned at character line WL ₁～WL ₄Under, and respectively on the channel region 31～34 between doped region 21 and 22, doped region 22 and 23, doped region 23 and 24, the doped region 24 and 25.Doped region 20,26 is as the bit line or respectively as bit line BL ₁With BL ₂Connection.Select grid SLG1 and SLG2 to form and select transistor, doped region 21 with 22 and doped region 25 and 26 be used for being connected or isolating memory cell array and and BL respectively ₂For the selected memory cell in the memory cell array that stylizes, like character line WL ₁On memory cell, use one bias arrangement as shown in the figure, wherein bit line BL ₁Be not that idol is received ground (injecting the selected memory cell that stylizes with FN), idol connects to apply current potential Vcc (with stylizing of the memory cell forbidding selecting) exactly.In order to couple bit line BL ₁To doped region 21, select grid SLG1 to receive and apply current potential Vcc.Select voltage or the ground connection of grid SLG2 reception 0V, to isolate bit line BL ₂With doped region 25.When substrate ground connection, the character line of selected memory cell is character line WL in this example ₁, receive the high voltage that is about 18V.The character line of selected memory cell receives the voltage that is about 10V, and enough feasible other channel region produces counter-rotating, but not enough so that important electric charge ejaculation.As shown in Figure 3, doped region is formed between each channel region.

Therefore, for source/drain, the use of diffusing lines from the semiconductor-based end (diffusion line) has produced a restriction on the size of traditional memory cell.Be used for forming the diffusion of the impurity of diffusing lines, scattering surpasses the zone of being implanted, and has increased the size of doped region, and other restrictions that cause the memory cell size, comprises the smallest passage length of avoiding puncturing (pounch-through).

The method of using diffusing lines to overcome problem is developed; The method is based on and produces conduction counter-rotating zone in the substrate; The control electrode of use adjacent charge memory structure in memory cell, the foundation that therefore constantly changes counter-rotating zone is then as the source/drain electrode.Because do not carry out implantation process, the size in counter-rotating zone can be controlled according to the minimum feature size of processing procedure more accurately." 90-nm*node multi-level AG-AND type flash memory with cell size of true 2F ²/ bit and programming throughput of 10MB/s, " IEDM, 2003, page823-826 and by U.S. Patent Publication No.US2004/0084714 that the people proposed such as Ishii.The technology of the improvement grid that the people proposed such as Sasago can be regarded as being applied in the extension of so-called separated grid (split gate) technology of various forms of floating grid memory cells.Please refer to by the Chang proposition about the separated grid element No. the 5th, 408,115, United States Patent (USP).

Therefore, develop that making simple and the technology of the non-volatility memory of high-density applications is provided is gratifying.

Summary of the invention

The present invention proposes a kind of ic memory element with multiple grid (multiple-gate) memory cell.In one embodiment, said elements comprises the semiconductor main body and the grid of most arranged in series on semiconductor body.A charge storing structure on semiconductor body is included in the charge-trapping zone that surpasses in most the grids under the grid.Also be included in the semiconductor body, near the first grid and final grid of memory cell array, conduct the Circuits System that source/drain is biased into the first region territory and the second electrode region respectively, and conduct the grid bias Circuits System of several grids at the most.The multiple grid memory cell comprises one continuously and be positioned at the multiple grid passage area under most the grids of memory cell array, and it is between the first region territory and the second electrode region.In certain embodiments, the charge-trapping zone comprises the specific multiple grid memory cell under all grids that are positioned at memory cell array, and all grids are as controlling grid to store data.In other embodiments, all grids in the memory cell array are not all as controlling grid to store data.In an example, storing data, and other grids in the memory cell array are used for promoting the isolation between the storage area in the memory cell to part of grid pole as the control grid.

In certain embodiments, on the multiple grid memory cell, two zones whole or that surpass under one the grid in most the grids in memory cell array store data, and use and use two storage areas of each control grid to store data.

In certain embodiments, the Circuits System of conduction source/drain bias voltage comprises the conductive material of arrangement as the bit line, and the Circuits System of conduction grid bias comprises the conductive material of arrangement as the character line.For instance, first doped region and second doped region are included in the semiconductor body, with final grid electrode zone are provided with the first grid in abutting connection with memory cell array.Doped region has the conduction type opposite with semiconductor body, and as the source/drain electrode.In other embodiments, be utilized in the counter-rotating zone of being caused when access stored is regional in the multiple grid memory cell the first region territory and the second electrode region are provided.In certain embodiments, for example for selecting transistorized element optionally to connect as at least one doped region or reversal zone to bit line in first area and the second electrode region.

Carry out the operation of memory cell in order to set up bias arrangement, utilize the controller of Circuits System with the Circuits System of conduction grid bias of control conduction source/drain bias voltage, the integrated circuit component with multiple grid memory cell is operated.In an example; In order to set up a high critical voltage state; Utilize controller that bias arrangement is provided; It comprises the bias arrangement that stylizes, and injects the charge-trapping zone wear then to the memory cell to cause electronics, and this charge-trapping zone is arranged under the selected grid of memory cell array.In the process that stylizes, apply another control grid in selected grid bias to the memory cell array, or other whole control grids causing in channel region that fully counter-rotating supports electronics and wear and satisfy.Comprise the example that utilizes electronics to inject to stylize at some; With controller bias arrangement is provided; It comprises the bias arrangement of erasing, and erases to cause that electronics ejaculation or electric hole are injected in the charge storage region, to set up a low critical voltage state.

In the embodiment of integrated circuit with multiple grid memory cell; The embodiment that comprises two storage areas that utilize each control grid; The Circuits System of controller control conduction source/drain bias voltage is set up a bias arrangement with the Circuits System of conduction grid bias, stores data with the charge-trapping zone under each grid of the grid above that is arranged in memory cell array.In an example; In order to set up a low critical voltage state; Utilize controller that bias arrangement is provided, it comprises the bias arrangement that stylizes, and injects the charge-trapping zone wear then to the memory cell to cause hot hole; This charge-trapping zone is in two selected charge storage region in one of them, and charge storage region is arranged under the selected grid of memory cell array.The process that stylizes being arranged in the selected charge storage region under the selected control grid applies another grid that is biased in the memory cell array, or other whole grids, causing in channel region that fully counter-rotating supports electricity and pierce and satisfy.Comprise at some and to utilize electric hole to inject the example that stylizes that with controller bias arrangement is provided, it comprises the bias arrangement of erasing, and erases to cause that electronics is injected in the charge storage region, to set up a high critical voltage state.In the embodiment of integrated circuit with multiple grid memory cell; The embodiment that comprises two storage areas that utilize each control grid; Comprise that in certain embodiments hot hole erases, according to an erase step, the controller control applies bias arrangement and erases; This erase step comprises the storage area under the selected grid of the memory cell array that is arranged in the multiple grid memory cell of erasing, and the storage area under another grid that is arranged in memory cell array of not erasing.

In some instances; The controller control applies bias arrangement; It comprises that is read a bias arrangement, reads under the bias arrangement at this, and selected control grid receives and reads voltage; And the control grid on other storage areas receives voltage and in the multiple grid passage area, causes counter-rotating, to support reading of memory zone.

The present invention proposes a kind of method of operation of ic memory element in addition, and wherein ic memory element comprises that aforesaid multiple grid memory cell and the method generally are to control with wafer built-in (on-chip) controller.Method of the present invention is included in the element and applies bias arrangement to read data in the zone that is positioned under the selected grid; Apply bias arrangement with the data that stylizes in the zone that is positioned under the selected grid; Apply bias arrangement with erase data in the zone that is positioned under the selected grid.In the embodiment of this method, the bias arrangement that stylizes comprises:

In the multiple grid channel region, apply substrate bias condition (bias condition) to semiconductor body;

First grid in memory cell array and final grid one of them near apply the source electrode bias condition to semiconductor body;

Apply the drain bias condition to semiconductor body near in first grid in memory cell array and the final grid another; And

In memory cell array, apply most grid bias conditions several grids at the most; Wherein these grid bias conditions comprise stylize a voltage and a reversal voltage; Wherein the voltage that stylizes on the selected grid in memory cell array is with respect to the substrate bias condition; Enough reduce electron injection current to the charge-trapping zone that is positioned at selected grid below, setting up high critical voltage state, and the reversal voltage on other grids in memory cell array enough reduces the counter-rotating in the multiple grid channel region; Wherein the multiple grid channel region is positioned at above-mentioned other grids below, and does not have effective electronics to be injected into to be positioned at most charge storaging areas of above-mentioned other grids belows.

In the embodiment of this method, the bias arrangement of erasing comprises:

In the multiple grid channel region, apply the substrate bias condition to semiconductor body;

First grid and final grid apply the source electrode bias condition to semiconductor body near one of them in memory cell array;

First grid and final grid wherein apply the drain bias condition to semiconductor body near another in memory cell array; And

In memory cell array, apply most grid bias conditions several grids at the most; Wherein these above-mentioned these grid bias conditions comprise most voltages; These voltages cause that enough electronics penetrates or electric hole iunjected charge capture region from the charge-trapping zone; To set up low critical voltage state, wherein the charge-trapping zone is arranged on the memory cell array and states under the grid.

In another example, the bias arrangement of erasing comprises:

In memory cell array, apply most grid bias conditions with to being positioned at one or more selected zones, most grids belows; Wherein above-mentioned these grid bias conditions comprise most voltages; It is regional that these voltages cause that enough the charge-trapping that is arranged in the selected grid below of memory cell array is injected in electric hole; And above-mentioned grid bias condition is included in the counter-rotating bias voltage on other grids in the memory cell array; This reversal voltage enough reduces the counter-rotating in the multiple grid channel region, and in selected grid, to set up low critical voltage state, wherein the multiple grid channel region is positioned at above-mentioned other grid belows.

According to the described erase step of the embodiment of the invention, this erase step comprises:

One group of grid in most the grids of desiring in the memory cell array to erase verifies that this group grid has the grid of surpassing;

Applying most grid bias conditions erases to the first selected grid in above-mentioned that group grid; Satisfy the hot hole iunjected charge storage area that (band-to-band tunneling) caused to cause that source side or gate electrode side one of them or whole band are worn band, this charge storaging area is positioned at the first selected grid below;

Applying most grid bias conditions erases to the selected grid of the next one in above-mentioned that group grid; Satisfy the hot hole iunjected charge storage area that (band-to-band tunneling) caused to cause that source side or gate electrode side one of them or whole band are worn band; This charge storaging area is positioned at next selected grid below, and repeats above-mentioned steps all grids in applying above-mentioned grid bias condition to above-mentioned that group grid.

In the embodiment of this method, read with the decision data and comprise with high bias arrangement with low critical voltage STA representation:

In memory cell array, apply most grid bias conditions several grids at the most; Wherein these grid bias conditions are included on the selected grid in the memory cell array voltage that reads with respect to the substrate bias condition; This reads the critical voltage that voltage is higher than low critical voltage state; And these grid bias conditions are included in the counter-rotating bias voltage on other grids in the memory cell array; This reversal voltage enough reduces the counter-rotating in the multiple grid channel region, and wherein the multiple grid channel region is positioned at above-mentioned other grid belows, and this reversal voltage is higher than the critical voltage of high critical voltage state.

The above-mentioned multiple grid memory cell that is arranged in the array comprises most character lines, at least one row, is coupled to most grids of multiple grid memory cell; A most bit line with most character line vertical arrangements, and are arranged in delegation or multirow to be connected to the multiple grid memory cell; Select grid for most, at least one row, arrange, select the grid controlling signal to respond to connect the bit line in other multiple grid memory cell to most the relevant bit lines; And a selection wire, at least one row, be coupled to most and select grids, select the grid controlling signal to provide.In addition, a controller control majority bit line, most individual bit line and selection wire are biased into the multiple grid memory cell with conduction source electrode bias voltage and drain in array, and at least one row, conduct the most individual grids in grid bias to the multiple grid memory cell.

In certain embodiments, make the above-mentioned multiple grid memory cell and the array of multiple grid memory cell according to method of the present invention, the method comprises:

Semiconductor body with first conductivity type is provided;

On semiconductor body, form charge storing structure;

Deposition first grid conductor layer on charge storing structure;

Patterning first grid conductor layer is with most first grids on the definition charge storing structure; On continuous multiple grid channel region, this multiple grid channel region is in semiconductor body between the first region territory and the second electrode region with a gap arranged in series for most first grids;

To the sidewall that is less than most first grids, form insulating barrier;

Deposition second grid conductor layer is included between most the first grids on insulating barrier, and isolates most first grids with insulating barrier; Most second grids of definition on semiconductor body; A most first grid and most second grid arranged in series are on continuous multiple grid channel region; This multiple grid channel region is in semiconductor body between the first region territory and the second electrode region, to form the multiple grid memory cell.

In the embodiment of above-mentioned multiple grid memory cell, the insulating barrier on grid utilization in the memory cell array control gate lateral wall is separated mutually with small distance, this manufacture method with in before said.In continuous multiple grid channel region, this distance for individual other grid, comprises the distance less than 10 nanometers in fact less than the length of grid.

State with other purposes for letting on the present invention, feature and advantage can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended graphicly, elaborates as follows.

Description of drawings

Fig. 1 is a kind of charge-trapping memory cell of convention.

Fig. 2 A and Fig. 2 B are to cause that FN wears then the bias arrangement that the charge-trapping memory cell to convention stylizes.

Fig. 3 is the configuration of a kind of charge-trapping memory cell array with enable nand gate of convention, and with a kind of bias arrangement memory cell selected in the memory cell array is stylized.

Fig. 4 is the multiple grid memory cell with two control grids.

Fig. 5 is the graphical sysmbol of multiple grid memory cell as shown in Figure 4.

Fig. 6 is the multiple grid memory cells with two control grids, and is stylized in the storage area that is positioned at below the selected memory cell in memory cell array with a kind of bias arrangement.

Fig. 7 A to Fig. 7 D is the multiple grid memory cells with two control grids, and the storage area that is positioned at below the selected memory cell is read in memory cell array with individual other bias arrangement.

Fig. 8 is the multiple grid memory cells with two control grids, and is erased in the storage area that is positioned at below the selected memory cell in memory cell array with a kind of bias arrangement.

Fig. 9 is the multiple grid memory cells with two control grids, and is erased in the storage area that is positioned at below the selected memory cell in memory cell array with selectable bias arrangement.

Figure 10 is the multiple grid memory cell with N control grid.

Figure 11 is the graphical sysmbol of multiple grid memory cell as shown in Figure 4.

Figure 12 is the multiple grid memory cell with N control grid, and is stylized in the storage area that is positioned at below the selected memory cell in memory cell array with a kind of bias arrangement.

Figure 13 is the multiple grid memory cell with N control grid, and the storage area that is positioned at below the selected memory cell is read in memory cell array with a kind of bias arrangement.

Figure 14 is the multiple grid memory cell with N control grid, and is erased in the storage area that is positioned at below the selected memory cell in memory cell array with a kind of bias arrangement.

Figure 15 is the multiple grid memory cell with N control grid, and is erased in the storage area that is positioned at below the selected memory cell in memory cell array with selectable bias arrangement.

Figure 16 applies the simplified flow chart that the bias arrangement of Figure 14 and Figure 15 is erased.

Figure 17 is the multiple grid memory cell with N control grid, in memory cell array near first grid and the final grid, with Circuits System conduction source pole tension and drain voltage to semiconductor body.

Figure 18 is the multiple grid memory cell with N control grid, in memory cell array near first grid and the final grid, with the selection gridistor

Figure 19 is the multiple grid memory cell with N control grid, with selectable execution mode, in memory cell array near first grid and the final grid, to selection grid conduction source pole tension and drain voltage to semiconductor body.

Figure 20 is the multiple grid memory cell with N control grid, with another selectable execution mode, in memory cell array near first grid and the final grid, to selection grid conduction source pole tension and drain voltage to semiconductor body.

Figure 21 is the multiple grid memory cell with N control grid, with selectable Circuits System, in memory cell array near first grid and the final grid, to selection grid conduction source pole tension and drain voltage to semiconductor body.

Figure 22 is the multiple grid memory cell with N+1 (odd number) control grid, stores data as the control grid with the grid of remembering even number in the hundred million born of the same parents row.

Figure 23 is the multiple grid memory cell with N+1 (odd number) control grid, stores data as the control grid with the grid of remembering odd number in the hundred million born of the same parents row.

Figure 24 A to Figure 24 F is the making flow process of multiple grid memory cell.

Figure 25 is in the making flow process like the multiple grid memory cell of Figure 24 A to Figure 24 F, passes the step that charge storing structure forms source electrode and drain alloy.

Figure 26 A to Figure 26 D is the making flow chart like the multiple grid memory cell of Figure 22 or Figure 23.

Figure 27 is the calcspar that comprises the integrated circuit of multiple grid memory cell.

Figure 28 is the multiple grid memory cell with two control grids and two storage areas, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 29 is the multiple grid memory cell with two control grids and two storage areas, under selected control grid, carries out erase data with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 30 is the multiple grid memory cell with two control grids and two storage areas, under selected control grid, carries out erase data with selectable bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 31 is the multiple grid memory cell with two control grids and two storage areas, and the left side bit 1-1 that is positioned at the first control grid below is stylized with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 32 is the multiple grid memory cell with two control grids and two storage areas, and the right side bit 1-2 that is positioned at the first control grid below is stylized with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 33 is the multiple grid memory cell with two control grids and two storage areas, and the left side bit 2-1 that is positioned at the second control grid below is stylized with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 34 is the multiple grid memory cell with two control grids and two storage areas, and the right side bit 2-2 that is positioned at the second control grid below is stylized with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 35 is the multiple grid memory cell with two control grids and two storage areas, and the left side bit 1-1 that is positioned at the first control grid below is read with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 36 is the multiple grid memory cell with two control grids and two storage areas, and the right side bit 1-2 that is positioned at the first control grid below is read with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 37 is the multiple grid memory cell with two control grids and two storage areas, and the left side bit 2-1 that is positioned at the second control grid below is read with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 38 is the multiple grid memory cell with two control grids and two storage areas, and the right side bit 2-2 that is positioned at the second control grid below is read with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 39 is the multiple grid memory cell with N control grid and two storage areas, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 40 is the multiple grid memory cell with N control grid and two storage areas, under selected control grid, erases with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 41 is the multiple grid memory cell with N control grid and two storage areas, under selected control grid, erases with selectable bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 42 is the multiple grid memory cell with N control grid and two storage areas, and the left side bit that is positioned at selected control grid below is stylized with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 43 is the multiple grid memory cell with N control grid and two storage areas, and the right side bit that is positioned at selected control grid below is stylized with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 44 is the multiple grid memory cell with N control grid and two storage areas, and the left side bit that is positioned at selected control grid below is read with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 45 is the multiple grid memory cell with N control grid and two storage areas, and the right side bit that is positioned at selected control grid below is read with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 46 is the layout of one of multiple grid memory cell section.

Figure 47 is the first selectable layout of one of multiple grid memory cell section.

Figure 48 is the second selectable layout of one of multiple grid memory cell section.

Figure 49 is the 3rd a selectable layout of one of multiple grid memory cell section.

Figure 50 is the 4th a selectable layout of one of multiple grid memory cell section.

Figure 51 is the layout of one of multiple grid memory cell block, and this block comprises most sections.

1,103-1～103-N, 501,502,603-1～603-N: control grid

750～756,760～766: the control grid

11,50,51,201,209,173-1～173-N+1: grid

12,52,105,605: the top dielectric layer

13: the charge-trapping material

14,54,107,607: end dielectric layer

15,16,55,56,101,102: electrode

202,203,205,206,212,213,503,504,601,602: electrode

17,31～34,58: channel region 20～26: doped region

53,106,302,606: electric charge capture layer

57,500: substrate 60,110: electronic signs

70,71,104-1～104-N, 184-1～184-N+1: charge storaging area

604-1-1～604-N-1,604-1-2～604-N-2: charge storaging area

73,74,75,77,120,121,125,126,127,128: the reversal zone

510,512,514,516: the reversal zone

615,616,625,626,635,636,645,646: the reversal zone

76,78,130,131: hot hole

100: substrate 150,151: Circuits System

207,208,214,215: gate dielectric layer

210,211,710～716,720～726, SLG1, SLG2: select grid

250～257: step 301: bottom oxide

303: top oxide layer 304: polysilicon layer

304X, 306X: gate electrode 307: source electrode

308: drain electrode 340: separator

341～347: gap 349: source electrode

350: drain 351～356: stack layer

400: memory array 401: column decoder

402, WL ₁～WL ₄: character line 403: row decoder

404, BL ₁, BL ₂, BL _N-3～BL _N+3: the bit line

405: bus-bar 406: square

407: data bus 411: the data input line

412: data output line 450: integrated circuit

505,506,511,513,515,517: symbol

610-1～610-N, 611-1～611-N, 617,627: symbol

600: semiconductor body

700～706,740～746: the multiple grid memory cell

718,728,748,749,758: contact window

719,769: source electrode line 800: section

802～811: contact hole

I: label

F: characteristic size

SLG3, SLG4: controlling signal

Vg, Vs, Vd, Vb: bias voltage

Embodiment

Below will do detailed explanation to the embodiment of the invention, and simultaneously with reference to Fig. 4 to Figure 51.

As employed; Stylize and be meant the then selected regional critical voltage of memory of bit ground setting of a bit; Be meant critical voltage to the condition of erasing (erase condition) of setting selected memory region or memory district and erase, it quickflashing (flash) that comprises whole array or partial array is erased.In an embodiment of the present invention, the write step of data comprises, at first, to the processing of erasing of a selected block, so that the memory district in the block is set to the critical voltage of erasing, is generally the wherein a kind of of high or low critical voltage state.Then,, be set to the state of stylizing, be generally the wherein another kind of of high or low critical voltage state, and stay memory district selected in the block in erased status with the memory district that will select to the processing that stylizes of the memory district in the block.The embodiment of said technology comprises stylizing and is meant the critical voltage that improves the memory district and erases and be meant the product and the method for the critical voltage that reduces the memory district, and stylizes and be meant the critical voltage that reduces the memory district and erase and be meant the product and the method for the critical voltage that improves the memory district.

Fig. 4 is according to a kind of bigrid memory cell of the present invention, comes to be stylized in selected zone with a kind of bias arrangement.The bigrid memory cell comprise respectively left and right sides electrode district with the n+ doped region channel region 58 in formed electrode 55,56 and left and right sides grid 50,51 and the substrate 57.Connecting the bigrid memory cell to the bit line, or other Circuits System are to provide bias voltage as electrode electrode 55,56 for doped region.Channel region 58 be continuous p type zone and in substrate electrode 55, between 56, do not have doped region significantly and isolate the part of the channel region under left and right sides grid 50,51.The charge-trapping structure for example comprise for the top dielectric layer 52 of representative thickness, electric charge capture layer 53 with about 9 nanometers with for example be the end dielectric layer 54 of representative thickness with about 6 nanometers.The charge-trapping structure is formed between the channel region 58 in left and right sides grid 50,51 and the substrate of p type.Electric charge capture layer 53 comprises and for example is the silicon nitride of about 6 nanometer thickness or the layer of material of other structures that it can be with the charge-conduction that in selected memory cell, is captured to influencing in the zone of other regional critical voltages in the memory cell array in fact.In certain embodiments, grid 50,51 comprises n type or p type polysilicon.Other representational grid materials comprise titanium nitride (TiN), platinum (Pt) and other H.D metal or material.Each storage area can store the data of a bit or multidigit unit.For instance, utilize the rank, critical voltage position of stylizing are set up in the zone more, can store multidigit unit in each zone.

Fig. 5 is a kind of graphical sysmbol of grid memory cell, and this grid memory cell is as shown in Figure 4, the wherein corresponding doped

region electrode

55,56 of source electrode and drain difference, and control grid 1 corresponding grid 50, and control grid 2 corresponding grids 51.

Fig. 6 is a kind of bias arrangement that is stylized in memory district selected in the bigrid memory cell, and this grid memory cell is as shown in Figure 4.According to bias arrangement, utilize substrate 57 ground connection, apply the Vg of about 18V ₁To grid 50, apply about 10V to grid 51, and doped

region electrode

55,56 one of them ground connection, and another also ground connection or suspension joint, cause with the zone of electronic signs 60 representatives that FN wears and satisfy being arranged in charge storing structure below the grid 50.

Fig. 7 A to Fig. 7 D is the bias arrangement that in the bigrid memory cell, reads data, and this grid memory cell is as shown in Figure 4.In Fig. 7 A to Fig. 7 B, read the data of " bit 1 (bit 1) " of representing the bigrid memory cell by source side or drain side joint receipts 2V, wherein this data storage is being positioned at receiving grid pole tension Vg ₁Grid 50 under charge storaging area 70.In Fig. 7 C to Fig. 7 D, read the data of " bit 2 (bit 2) " of representing the bigrid memory cell by source side or drain side joint receipts 2V, wherein this data storage is being positioned at receiving grid pole tension Vg ₂Grid 51 under charge storaging area 71.

Fig. 7 A is when reading " bit 1 " at charge storaging area 70, applies positive 2V as drain and make the bias arrangement of electrode 55 ground connection as source electrode at electrode 56.The grid voltage Vg that is applied in grid 51 ₂Enough high and make and produce reversal zone 73 in electrode 55, the channel region between 56.Utilization is by grid voltage Vg ₂The reversal zone 73 that produces will be coupled near the zone in the channel region of charge storaging area 70 at the voltage on source electrode or the drain.Memory cell is set the grid voltage Vg that is applied to grid 50 ₁On low critical voltage, and under the high critical voltage.In one embodiment, the grid voltage Vg that is applied ₁Be about 2V.Fig. 7 B reads identical " bit 1 " to

opposite electrode

55,56 to be biased in the charge storaging area 70.

Fig. 7 C is when reading " bit 2 " at charge storaging area 71, applies positive 2V as drain and make the bias arrangement of electrode 55 ground connection as source electrode at electrode 56.The grid voltage Vg that is applied in grid 50 ₁Enough high and make and produce reversal zone 74 in electrode 55, the channel region between 56.Utilization is by grid voltage Vg ₁The reversal zone 74 that produces will be coupled near the zone in the channel region of charge storaging area 71 at the voltage on source electrode or the drain.Memory cell is set the grid voltage Vg that is applied to grid 51 ₂On low critical voltage, and under the high critical voltage.In one embodiment, the grid voltage Vg that is applied ₁Be about 2V.Fig. 7 D reads identical " bit 2 " to

opposite electrode

55,56 to be biased in the charge storaging area 71.

Fig. 8 and Fig. 9 are the bias arrangement that when memory cell as shown in Figure 4 is carried out erase data, can select; These two kinds of bias arrangement are operated with each grid one bit in the multiple grid memory cell, and are suitable for combining the bias voltage that stylizes shown in Figure 6 to use.Please with reference to Fig. 8, the bias arrangement of erasing of in the storage area that is arranged under the control gate utmost point 50, erase " bit 1 " comprises when electrode 55 ground connection and when applying about 5V to electrode 56, applies the grid voltage Vg of pact-5V ₁To grid 50 and the grid voltage Vg that applies about 10V ₂To grid 51.So just, under grid 51, produce reversal zone 75, and produce hot hole 76 in the substrate under grid 50.Hot hole is injected into the storage area of " bit 1 ", replaces electronics and reduces the critical voltage of the storage area under the grid 50.

Please with reference to Fig. 9, the storage area of control grid 50 under being arranged in, the selectable bias arrangement of erasing of erase " bit 1 " comprises when electrode 56 ground connection and when applying about 5V to electrode 55, applies the grid voltage Vg of pact-5V ₁To grid 50 and the grid voltage Vg that applies about 10V ₂To grid 51.So just, under grid 51, produce reversal zone 77, and produce hot hole 78 in the substrate under grid 50.Hot hole is injected into the storage area of " bit 1 ", replaces electronics and reduces the critical voltage of the storage area under the grid 50.In certain embodiments,, apply bias arrangement shown in Figure 9 again by applying bias arrangement shown in Figure 8 earlier, so that the CHARGE DISTRIBUTION in the storage area reaches balance, and can erase " bit 1 ".

Figure 10 is one embodiment of the invention, wherein in the multiple grid memory cell, has two grids of surpassing, and embodiment shown in Figure 4 is extended to N grid on single continuous channel region in substrate 100.Multiple grid memory cell shown in Figure 10 is included in first electrode 101 and second electrode 102 that forms with flush type diffusion (buried diffusion) in the substrate 100.Most control grid 103-1～103-N are disposed on the charge storing structure, and wherein this charge storing structure comprises top dielectric layer 105, electric charge capture layer 106 and end dielectric layer 107.Charge storaging area 104-1～104-N in the electric charge capture layer 106 is disposed in the substrate in electrode 101, continuous channel region between 102.As shown in the figure, a kind of bias arrangement applies grid voltage Vg ₁～Vg _NTo controlling grid 103-1～103-N, apply source voltage Vs to electrode 101, and apply drain voltage Vd to electrode 102.Certainly, source voltage and drain voltage can be applied to electrode 102 and electrode 101 on the contrary respectively.

Can do selection according to special embodiment at single multiple grid memory cell shown in figure 10.For instance, N equals 8 in one embodiment.In another embodiment, can be greater than or less than 8.

Figure 11 is a kind of graphical sysmbol of multiple grid memory cell, and this grid memory cell is shown in figure 10, wherein source electrode and drain difference counter electrode 101,102, and control grid 1 corresponding grid 103-1, and the corresponding grid 103-N of control grid N.

Figure 12 is a kind of bias arrangement that in the multiple grid memory cell, is stylized in selected memory district, and it is said similar with Figure 10.According to bias arrangement,,, apply the Vg of 18V by substrate 100 ground connection when electrode 101,102 one of them ground connection and another also ground connection or suspension joint ₂To grid 103-2, apply about 10V to grid 103-1 and～103-N, cause with the zone of electronic signs 110 expressions that FN wears in the charge storing structure under grid 103-2 and satisfy.

Figure 13 is a kind of demonstration bias arrangement that in charge storaging area 104-5, reads " bit 5 ", wherein, the electrode 102 as drain is applied positive 2V, and will be as electrode 101 ground connection of source electrode.Grid voltage Vg ₁～Vg ₄With Vg ₆～Vg _NSufficiently highly in electrode 101, channel region between 102, producing reversal zone 120,121.Grid voltage Vg ₁～Vg ₄With Vg ₆～Vg _NThe reversal zone 120,121 that is produced will be coupled near the zone in the channel region of charge storaging area 104-5 at the voltage on source electrode or the drain.Memory cell is set the grid voltage Vg that is applied to grid 103-5 ₅On low critical voltage, and under the high critical voltage.In this example, the grid voltage Vg that is applied ₅Be about 2V.

Figure 14 and Figure 15 are the bias arrangement that when memory cell shown in figure 10 is carried out erase data, can select; These two kinds of bias arrangement are operated with each grid one bit in the multiple grid memory cell, and are suitable for combining the bias voltage that stylizes shown in Figure 12 to use.Please with reference to Figure 14, the bias arrangement of erasing of in the storage area that is arranged under the control gate utmost point 103-3, erase " bit 3 " comprises when electrode 101 ground connection and when applying about 5V to electrode 102, applies the grid voltage Vg of pact-5V ₃To grid 103-3 and the grid voltage Vg that applies about 10V ₁～Vg ₂With Vg ₄～Vg _NTo grid 103-1～103-2 and 103-4～103-N.So just, under grid 103-1～103-2, produce reversal zone 125,, and produce hot hole 130 in the substrate under grid 103-3 with generation reversal zone 126 under grid 103-4～103-N.Hot hole is injected into the storage area of " bit 3 ", replaces electronics and reduces the critical voltage of the storage area under the grid 103-3.

Please with reference to Figure 15, the storage area of control grid 103-3 under being arranged in, the selectable bias arrangement of erasing of erase " bit 3 " comprises when electrode 102 ground connection and when applying about 5V to electrode 101, applies the grid voltage Vg of pact-5V ₃To grid 103-3 and the grid voltage Vg that applies about 10V ₁～Vg ₂With Vg ₄～Vg _NTo grid 103-1～103-2 and 103-4～103-N.So just, under grid 103-1 and 103-2, produce reversal zone 127,, and produce hot hole 131 in the substrate under grid 103-3 with generation reversal zone 128 under grid 103-4～103-N.Hot hole is injected into the storage area of " bit 3 ", replaces electronics and reduces the critical voltage of the storage area under the grid 103-3.

In certain embodiments,, apply bias arrangement shown in Figure 15 again,, and can erase " bit 3 " or bit that other are selected so that the CHARGE DISTRIBUTION in the storage area reaches balance by applying bias arrangement shown in Figure 14 earlier.

Figure 16 is the erase step flow chart that is applicable to like Figure 14 and bias arrangement shown in Figure 15, and wherein this step is to be used for each bit district is applied bias voltage, with near the generation hot hole in bit district.At first, step 250 begins the whole data in the memory cell are erased, and this memory cell for example is a memory cell shown in Figure 10.Then, in step 251, set index i=1, wherein the grid 1～N in the corresponding memory cell of index i.Then, in step 252, (current bit) applies a bias arrangement to existing bit.This bias arrangement can be shown in figure 14, shown in figure 15 or other bias arrangement.Next, in step 253, utilize to test whether i=N judges whether bit districts all in the memory cell is erased.Carry out step 254, increase index i, and in step 251, apply the next bit district in bias arrangement to the memory cell.If i equals N, in step 255, the verification step of erasing.Come again, in step 256, judge that memory cell makes not through the verification step of erasing.Were it not for through, then restart in this embodiment from step 251.If memory cell is through the checking of erasing, process ends in step 257 then.Other embodiment comprise the step of the memory cell of most the parallel connections of erasing, and the memory cell of parallel connection for example is the memory cell of one group of shared same group of bit line.Its handling process can be erased after step 252 and before the increase index i to each bit district and tested, and when authentication failed, carry out step 252 again, with checking and the retry step of erasing.

Figure 17 is an embodiment of multiple grid memory cell shown in figure 10; To near the electrode zone grid 103-1 and the 103-N, wherein grid 103-1 and 103-N are arranged in the memory cell grid row of semiconductor body with source electrode bias voltage and drain bias conduction in utilization.Circuits System 150,151 can the many forever modes of power be accomplished, and it comprises the doped region electrode that uses like the electrode among Figure 10 101,102, and utilizes contact (contact) supply voltage to the electrode 101,102 with conductor thought material.Electrode 101,102 can be regional tie point (local contact point), and it is to be disposed at metal level or the internal connection-wire structure (not illustrating) in other retes in the integrated circuit with connection electrode.Optionally, electrode 101,102 can be delegation's multiple grid shared conductor lines, and be coupled to Circuits System, this Circuits System along above-mentioned multiple grid supply voltage to any one.

Figure 18 is another embodiment that conduction source electrode bias voltage and drain are biased into the Circuits System of semiconductor body.In this embodiment, first select gridistor to comprise grid 201, be positioned at the doped region and the doped region that is positioned at electrode 203 of electrode 202.The second selection gridistor comprises grid 209, is positioned at the doped region and the doped region that is positioned at electrode 206 of electrode 205.The doped region that is positioned at electrode 202 and electrode 206 is coupled to overall bit line or other bit line structures, to transmit voltage electrode extremely separately.Bias voltage is coupled to the doped region that is positioned at electrode 203 and electrode 205, puts on control voltage SLG1, the SLG2 of grid 201,209 with response.Gate dielectric layer 207 is disposed on electrode 202, the channel region between 203, and wherein gate dielectric layer 207 for example is the silicon dioxide layer of individual layer.Likewise, gate dielectric layer 208 is disposed on electrode 205, the channel region between 206.

Figure 19 is another embodiment that conduction source electrode bias voltage and drain are biased into the Circuits System of semiconductor body.In this embodiment, first select grid 210 and second to select grid 211 to be disposed at respectively on semiconductor body and the gate dielectric layer 214,215.The first selection grid 210 and the second selection grid 211 are disposed at relative two ends of electrode 212, the row of the grid between 213 respectively, and continuous channel region is arranged under the charge storaging area of multiple grid memory cell.The difference of Figure 19 and Figure 18 has been to omit the doped region that is positioned at electrode 203 and electrode 205.By selecting grid 210 and second to select to produce the reversal zone under the grid 211 first; Doped region through being positioned at electrode 212 and electrode 213 applies bias voltage, so that voltage self-electrode 212,213 is conducted to channel region continuous under the charge storaging area that is arranged in the multiple grid memory cell.

Figure 20 is another embodiment that conduction source electrode bias voltage and drain are biased into the Circuits System of semiconductor body.The difference of Figure 20 and Figure 19 is that charge storing structure extends to first and selects grid 210 and second to select under the grid 211, and wherein charge storing structure comprises top dielectric layer 105, electric charge capture layer 106 and end dielectric layer 107.

Figure 21 is another embodiment that conduction source electrode bias voltage and drain are biased into the Circuits System of semiconductor body.The difference of Figure 20 and Figure 10 is that charge storing structure extends to and is positioned on doped region electrode 101 and the electrode 102 that wherein charge storing structure comprises top dielectric layer 105, electric charge capture layer 106 and end dielectric layer 107.

Figure 22 and Figure 23 are the embodiment of heavy grid memory cell, wherein whenever just are disposed on the storage area and conduct control grid at a distance from a grid, to read or to write data.In these two embodiment, select gate configuration between each control grid.In like Figure 22 and embodiment shown in Figure 23, preferably the row of the grid in the multiple grid memory cell comprise the odd number grid.Therefore, the final grid in the memory cell array can be regarded as grid N+1.In Figure 22, the even number grid is as controlling grid to store data.Data storage structure can be continuous between all grids, or segmented structure as shown in the figure, stores data and only be positioned under the control grid.Therefore; In order to control stylizing and read of multiple grid memory cell; When grid 174-1,174-3,174-5～174-N+1 as selecting grid when producing the reversal zone, grid 173-2,173-4,173-6～173-N are disposed at charge storaging area 184-2,184-4,184-6～184-N.

In Figure 23, the odd number grid is as controlling grid to store data.Data storage structure can be continuous between all grids, or segmented structure as shown in the figure, stores data and only be positioned under the control grid.Therefore; In order to control stylizing and read of multiple grid memory cell; When grid 174-2,174-4,174-6～174-N as selecting grid when producing the reversal zone, grid 173-1,173-3,173-5～173-N+1 are disposed at charge storaging area 184-1,184-3,184-5～184-N+1.

Figure 24 A to Figure 24 F is the making flow process profile of multiple grid memory cell shown in figure 10.At first, please with reference to Figure 24 A, be provided the semiconductor-based end 300, substrate 300 for example is p type silicon base or other semiconductor-based ends.In an embodiment of the present invention, substrate 300 utilizes so-called Mitsui (triple-well) technology to isolate, and wherein substrate 300 comprises the p type zone that is embedded in the n type zone, and n type zone is embedded in the p type zone.Be about to form in the basal region of multiple grid memory cell, forming bottom oxide 301, electric charge capture layer 302 and top oxide layer 303.Above-mentioned rete can utilize the various technology of knowing to form, comprise thermal oxidation method, chemical vapour deposition technique, electricity slurry enhanced chemical vapor deposition method, high density plasma enhanced chemical sedimentation, atomic layer deposition method or other that know with emerging technology.

Then, please with reference to Figure 24 B, after forming bottom oxide 301, electric charge capture layer 302 and top oxide layer 303, in suprabasil zone formation one deck polysilicon layer 304 or other conductive gate material of being about to form the multiple grid memory cell.Polysilicon layer 304 can utilize the various technology of knowing to form.

Then,, polysilicon layer 304 is carried out pattern etched, to form gate electrode 304X please with reference to Figure 24 C.In certain embodiments, gate electrode 304X, inwardly extends in parallel and crosses the zone that forms memory cell with the direction towards the diagram face as the character line structure.

Next,, cover most gate electrode 304X, comprise the sidewall of covering grid electrode 304X with insulating barrier 305 please with reference to Figure 24 D.The material of insulating barrier 305 is an insulating material, for example is silicon dioxide, silicon nitride or other insulating material.The sidewall of insulating barrier 305 covering grid electrode 304X, isolated with the isolated grid of inserting in the space.In one embodiment, the thickness of the insulating barrier 305 on the gate electrode 304X sidewall is less than 100 nanometers.The characteristic size F that has a minimum in an embodiment, and above-mentioned thickness is preferably less than 0.1F.In general, the thickness of insulating barrier is as much as possible little, in fact less than the length of gate electrode 304X.

Come again,, deposit second polysilicon layer, between gate electrode 304X, to form gate electrode 306X please with reference to Figure 24 E.The method that forms second polysilicon layer comprises chemical vapour deposition technique or other technologies, can fill up the space effectively.As shown in the figure, gate electrode 306X has the height identical with gate electrode 304X.In other embodiments, not necessarily has identical height between the electrode.In certain embodiments, the technology of planarization can be used the cmp technology.

As known that gate electrode 304X and gate electrode 306X can comprise that with silicide or metal be the top layer of material, to promote conductivity.

Afterwards, please with reference to Figure 24 F, the charge storing structure that will have bottom oxide 301, electric charge capture layer 302, top oxide layer 303 and polysilicon layer carries out patterning and etching, to expose the ion implantation region territory in the substrate 300.With n type alloy implant electrode zone, to form source electrode 307 and drain electrode 308.Via Figure 24 A to Figure 24 F, accomplish and similar multiple grid memory cell shown in Figure 10.Likewise, structural variation can be accomplished with the technology of knowing apace.

Figure 25 is the treatment step of an embodiment, and wherein in substrate in the doped region of source electrode 307 and drain electrode 308, bottom oxide 301, electric charge capture layer 302 are not removed with top oxide layer 303.Therefore, implantation step is different with Figure 24 F, and it must pass the material layer that is used for forming the charge-trapping structure.

Figure 26 A to Figure 26 D is a flow process profile of making multiple grid memory cell shown in figure 22.At first, identical with Figure 24 A to Figure 24 B, the semiconductor-based end 300, be provided.Be about to form in the basal region of multiple grid memory cell, forming bottom oxide 301, electric charge capture layer 302 and top oxide layer 303.Then, please with reference to Figure 26 A, accomplish the memory cell with storage area, this storage area is arranged in the below of memory cell even number grid.In Figure 26 A to Figure 26 D, the memory cell of the storage area of even number grid below.Structure among Figure 24 B is carried out patterning and etching, but different with Figure 24 C, not with top oxide layer 303 as etch stop layer.Above-mentioned etch process passes the material layer (301,302,303) as charge storaging area, and stays stack layer 351～356, and it comprises the charge storaging area that is positioned at polysilicon control grid utmost point below.In the step of Figure 26, form separator 340 with isolation stack layer 351～356, and one deck gate dielectric layer is provided in gap 341～347.Wherein, the material of separator 340 for example is a silicon dioxide.In the step of Figure 26 C, fill up gap 341～347 with polysilicon.In the step of Figure 26 D, implant source electrode 349 and drain 350 to accomplish memory cell.

Figure 27 is the simplification calcspar according to the integrated circuit that one embodiment of the invention illustrated.Integrated circuit 450 is included in the memory array 400 that forms with multiple grid, the charge-trapping memory cell of these memory array 400 small scopes at semiconductor-based the end.Column decoder (row decoder) 401 is coupled to most character lines 402 of multiple grid memory cell and is coupled to the selection gate line, and arranges along the column direction of memory array 400.Row decoder (column decoder) 403 is coupled to most the bit lines of arranging along the column direction of memory array 400 404, and with transfer source pole tension and drain voltage, and the multiple grid memory cell of remembering certainly in the array 400 reads data.By address (address) to row decoder 403 and column decoder 401 are provided on bus-bar 405.Sensing amplifier in square 406 (sense amplifiers) is coupled to row decoder 403 with data input structure (data-in structure) via data bus 407.From the I/O port on the integrated circuit 450 (input/output port) or inner or outside to integrated circuit 450 and the data of coming, the data input structure to the square 406 is provided via data input line (data-in line) 411 by other data source.Sensing amplifier from the square 406 and data of coming be fed to the I/O port on the integrated circuit 450 via data output line (data out line) 412, or it is inner or outside to integrated circuit 450 to be fed to other data purposes.

In this example; The controller control bias arrangement of using bias state machine (bias arrangement state machine) to carry out provides the function of voltage (bias arrangement supply voltage) 408, and the checking and the verifying voltage that stylizes for example read, stylize, erase, erase.Controller can use the specific purposes logic circuitry of knowing (special-purpose logic circuitry) to carry out.In another embodiment, controller comprises the processor (processor) of general objects, and it can be carried out on identical integrated circuit, carries out the operation of computer program with control element.In other embodiments, utilize the processor that combines specific purposes logic circuitry and general objects, can be used as controller.

Figure 28 is one embodiment of the invention, and wherein memory cell has 501,502, and is positioned at each control and has the two data storage area under grid.Memory cell comprises the semiconductor-based end 500, and the semiconductor-based end 500 has the n type electrode 503,504 as the source electrode of memory cell and drain.As shown in the figure, charge storaging area has 4 bits, and wherein bit 1-1 and bit 1-2 are positioned under the control grid 501, and bit 2-1 and bit 2-2 are positioned under the control grid 502.Bias voltage Vg ₁With Vg ₂Be applied to control grid 501,502 respectively.In certain embodiments, each the data storage district under each grid in the memory cell can store and surpass 1 bit.According to electrode in the memory cell as the function of source electrode or the function of drain, apply bias voltage Vs to electrode 503,504 one of them, and bias voltage Vd another to the electrode 503,504.Apply bias voltage Vb to substrate 500.Apply bias arrangement to stylize, to erase in charge storage region and to read data.

Figure 29 and Figure 30 are the selectable bias arrangement of the storage area under specific grid of erasing.In the bias arrangement of Figure 29, by the positive grid voltage Vg that applies about 8V ₁To controlling grid 501, apply about 0V to controlling grid 502, and apply pact-10V to source electrode 503, drain electrode 504 and substrate 500, between the charge-trapping district under substrate 500 and the control grid 501, produce FN and wear (symbol 505 is represented) then.FN wears and makes the critical voltage of memory cell increase then, and has set up high critical voltage erased status.In the bias arrangement of Figure 30, when source electrode 503 and drain electrode 504 suspension joints, by the negative grid voltage Vg that applies pact-8V ₁ To controlling grid 501, apply about 0V to controlling grid 502, and apply about 10V to substrate 500, generation FN wears (symbol 506 is represented) then between control grid 501 and the charge-trapping district that controls under the grid 501.FN wears and makes the critical voltage of memory cell increase then, and has set up high critical voltage erased status.

Figure 31 to Figure 34 is based on hot hole and injects, and to two bias arrangement that charge storaging area stylizes under each grid in the memory cell, it is suitable for being used in combination with the bias arrangement of erasing among Figure 30 like Figure 29.Shown in figure 31, inject by the hot hole that uses bias arrangement as shown in the figure, can bit 1-1 be stylized, wherein control grid 501 and receive Vg ₁=-5V, control grid 502 receives Vg ₂=+10V, electrode 503 receives Vs=+5V, and electrode 504 receives Vd=0V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 510 in control grid 502 belows, and on control grid 502, causes high relatively voltage.In addition, the caused hot hole in contiguous n+ implantation region in channel region, with symbol 511 expressions, the iunjected charge memory structure, replacing electronic also reduces the critical voltage of memory cell in charge storaging area for bit 1-1.Wherein, the n+ implantation region is as the usefulness of electrode 503.

Shown in figure 32, inject by the hot hole that uses bias arrangement as shown in the figure, can bit 1-2 be stylized, wherein control grid 501 and receive Vg ₁=-5V, control grid 502 receives Vg ₂=+10V, electrode 503 receives Vs=0V, and electrode 504 receives Vd=+5V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 512 in control grid 502 belows, and on control grid 502, causes high relatively voltage.In addition, contiguous reversal zone 512 caused hot holes in channel region, with symbol 513 expressions, the iunjected charge memory structure, replacing electronic also reduces the critical voltage of memory cell in charge storaging area for bit 1-2.

Shown in figure 33, inject by the hot hole that uses bias arrangement as shown in the figure, can bit 2-1 be stylized, wherein control grid 501 and receive Vg ₁=+10V, control grid 502 receives Vg ₂=-5V, electrode 503 receives Vs=+5V, and electrode 504 receives Vd=0V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 514 in control grid 501 belows, and on control grid 501, causes high relatively voltage.In addition, contiguous reversal zone 514 caused hot holes in channel region, with symbol 515 expressions, the iunjected charge memory structure, replacing electronic also reduces the critical voltage of memory cell in charge storaging area for bit 2-1.

Shown in figure 34, inject by the hot hole that uses bias arrangement as shown in the figure, can bit 2-2 be stylized, wherein control grid 501 and receive Vg ₁=+10V, control grid 502 receives Vg ₂=-5V, electrode 503 receives Vs=0V, and electrode 504 receives Vd=+5V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 516 in control grid 501 belows, and on control grid 501, causes high relatively voltage.In addition, the caused hot hole in contiguous n+ implantation region in channel region, with symbol 517 expressions, the iunjected charge memory structure, replacing electronic also reduces the critical voltage of memory cell in charge storaging area for bit 2-2.Wherein, the n+ implantation region is as the usefulness of electrode 504.

Figure 35 to Figure 38 is to two bias arrangement that charge storaging area reads under each grid in the memory cell, and it is suitable for like the bias arrangement and be used in combination like the bias arrangement that stylizes among Figure 31 to Figure 34 of erasing among Figure 29 and Figure 30.Shown in figure 35, use counter-rotating as shown in the figure to read bias arrangement and can read bit 1-1, wherein control grid 501 and receive Vg ₁=2V, control grid 502 receives Vg ₂=+10V, electrode 503 receives Vs=0V, and electrode 504 receives Vd=+2V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 510 in control grid 502 belows, and on control grid 502, causes high relatively voltage.Read bias arrangement for counter-rotating, be stored in the electric charge in the zone of bit 1-1, the critical bias of memory cell is fixed.If erased and set up high critical voltage state, then there is not current flowing under the bias arrangement reading in the charge storage region of bit 1-1.Selectively, if stylized and set up low critical voltage state, reading the passage that then has the current flowing memory cell under the bias arrangement in the charge storage region of bit 1-1.

Shown in figure 36, use counter-rotating as shown in the figure to read bias arrangement and can read bit 1-2, wherein control grid 501 and receive Vg ₁=+2V, control grid 502 receives Vg ₂=+10V, electrode 503 receives Vs=+2V, and electrode 504 receives Vd=0V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 512 in control grid 502 belows, and on control grid 502, causes high relatively voltage.If erased and set up high critical voltage state, then there is not current flowing under the bias arrangement reading in the charge storage region of bit 1-2.Selectively, if stylized and set up low critical voltage state, reading the passage that then has the current flowing memory cell under the bias arrangement in the charge storage region of bit 1-2.

Shown in figure 37, use counter-rotating as shown in the figure to read bias arrangement and can read bit 2-1, wherein control grid 501 and receive Vg ₁=+10V, control grid 502 receives Vg ₂=+2V, electrode 503 receives Vs=0V, and electrode 504 receives Vd=+2V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 514 in control grid 501 belows, and on control grid 501, causes high relatively voltage.If erased and set up high critical voltage state, then there is not current flowing under the bias arrangement reading in the charge storage region of bit 2-1.Selectively, if stylized and set up low critical voltage state, reading the passage that then has the current flowing memory cell under the bias arrangement in the charge storage region of bit 2-1.

Shown in figure 38, use counter-rotating as shown in the figure to read bias arrangement and can read bit 2-2, wherein control grid 501 and receive Vg ₁=+10V, control grid 502 receives Vg ₂=+2V, electrode 503 receives Vs=+2V, and electrode 504 receives Vd=0V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 516 in control grid 501 belows, and on control grid 501, causes high relatively voltage.If erased and set up high critical voltage state, then there is not current flowing under the bias arrangement reading in the charge storage region of bit 2-2.Selectively, if stylized and set up low critical voltage state, reading the passage that then has the current flowing memory cell under the bias arrangement in the charge storage region of bit 2-2.

The memory cell structure of Figure 28 has two grids, and each grid and two storage areas get in touch, and this kind memory cell structure extends the embodiment among Figure 39, and it has N grid, and N is greater than 2.Multiple grid memory cell among Figure 39 is formed in the semiconductor body 600 with p type alloy.N-type electrode 601,602 is as the source electrode and the drain of multiple grid memory cell.Charge storing structure comprises top dielectric layer 605, the electric charge capture layer 606 and end dielectric layer 607 on electrode 601, continuous channel region between 602.Control grid 603-1～603-N is positioned on charge storing structure and the channel region.According to illustrated embodiment, each control grid 603-1～603-N and two charge storaging areas are got in touch.Therefore, as shown in the figure, charge storaging area 604-1-1,604-1-2 and control grid 603-1 get in touch.Charge storaging area 604-2-1,604-2-2 and control grid 603-2 get in touch.Charge storaging area 604-3-1,604-3-2 and control grid 603-3 get in touch.Charge storaging area 604-4-1,604-4-2 and control grid 603-4 get in touch.Charge storaging area 604-5-1,604-5-2 and control grid 603-5 get in touch.Charge storaging area 604-6-1,604-6-2 and control grid 603-6 get in touch.Charge storaging area 604-(N-1)-1,604-(N-1)-2 and control grid 603-(N-1) contact.Charge storaging area 604-N-1,604-N-2 and control grid 603-N get in touch.Circuits System and memory cell are got in touch provides bias voltage, to stylize, to erase and to read the data that is stored in the charge storaging area.Bias voltage comprises being applied to respectively controls the last Vg of grid 603-1～603-N ₁～Vg _NBias voltage comprises Vs that is applied to electrode 601 and the Vd that is applied to electrode 602.At last, bias voltage comprises the Vb that is applied to semiconductor body 600.Semiconductor body 600 is included in the insulation layer among more above-mentioned embodiment, and it is arranged in the big semiconductor-based end.

Figure 40 to Figure 45 be used for erasing, stylize and read in the typical bias arrangement of memory cell.

Figure 40 and Figure 41 are alternative bias arrangement.In Figure 40, use positive grid voltage FN to wear then bias arrangement and erase and in the multiple grid memory cell, be positioned at the charge storaging area of selecting under the grid.Therefore, according to the bias arrangement among Figure 40, apply the Vg of pact+8V ₁, Vg ₃, Vg ₄, Vg ₆, Vg _(N-1)With Vg _NAnd the Vg of 0V ₂, Vg ₅With-Vd of 10V and control grid 603-1,603-3,603-4,603-6,603-N-1 and the 603-N that Vb erases selected.This bias arrangement causes that electronics wears then to charge storing structure from substrate, as is positioned at shown in symbol 610-1,610-3,610-4,610-6,610-N-1 and the 610-N of selected control grid 603-1,603-3,603-4,603-6,603-N-1 and 603-N below.For the storage area of getting in touch with each selected control grid, electronics is worn and is made critical voltage increase to the critical voltage of erasing of target then.The grid voltage of not selected control grid 603-2, the about 0V of 603-5 reception, its electronics that is not enough to cause the critical voltage state that enough serious interference had before been set up in not selected memory cell is worn then.

Figure 41 is that the grid voltage FN that bears wears bias arrangement then.According to the bias arrangement among Figure 41, apply the Vg of pact-8V ₁, Vg ₃, Vg ₄, Vg ₆, Vg _(N-1)With Vg _NAnd the Vg of 0V ₂, Vg ₅With+Vd of 10V and control grid 603-1,603-3,603-4,603-6,603-N-1 and the 603-N that Vb erases selected.This bias arrangement causes that electronics wears then to charge storing structure, shown in symbol 611-1,611-3,611-4,611-6,611-N-1 and 611-N from control grid 603-1,603-3,603-4,603-6,603-N-1 and 603-N.For the storage area of getting in touch with each selected control grid, electronics is worn and is made critical voltage increase to the target critical voltage of erasing then.The grid voltage of not selected control grid 603-2, the about 0V of 603-5 reception, its electronics that is not enough to cause the critical voltage state that enough serious interference had before been set up in not selected memory cell is worn then.

Figure 42 and Figure 43 are that the hot hole that causes for the memory cell among Figure 39 injects, and with band band are worn and are satisfied (band-to-band tunnelin) and carry out the left side and stylize in the right side.Use the bias arrangement among Figure 42 to be stylized in the storage area in left side, the storage area in this left side for example is the charge storaging area 604-5-1 of grid 603-5 below.According to the bias arrangement among Figure 42, not selected control grid 603-1～603-4 and 603-6～603-N receives the for example high voltage of about+10V, and selected control grid 603-5 receives the Vg of pact-5V ₅Electrode 601 receives the Vs of pact+5V, and electrode 602 receives the Vd of about 0V.Likewise, substrate receives the Vb of about 0V.High relatively voltage on not selected control grid produces reversal zone 615,616, and wherein reversal zone 615,616 couples the channel region of electrode 601,602 to control grid 603-5 below.The band of the hot hole that causes is worn then to band, and the edge of the reversal zone 615 below control grid 603-5 is caused; And iunjected charge storage area 604-5-1; Enough reduce the state that stylizes of critical voltage to the target of the storage area of getting in touch with selected control grid 603-5, left side, this band is worn then with symbol 617 expressions band.

Figure 43 is the bias arrangement that is stylized in the storage area of getting in touch with selected grid, right side.Use the bias arrangement among Figure 43 to be stylized in the storage area on right side, the storage area on this right side for example is the charge storaging area 604-3-2 of grid 603-3 below.According to the bias arrangement among Figure 43, not selected control grid 603-1～603-2 and 603-4～603-N receives the for example high voltage of about+10V, and selected control grid 603-3 receives the Vg of pact-5V ₅Electrode 601 receives the Vs of about 0V, and electrode 602 receives the Vd of pact+5V.Likewise, substrate receives the Vb of about 0V.High relatively voltage on not selected control grid produces reversal zone 625,626, and wherein reversal zone 625,626 couples the channel region of electrode 601,602 to control grid 603-3 below.The band of the hot hole that causes is worn then to band, and the edge of the reversal zone 626 below control grid 603-3 is caused; And iunjected charge storage area 604-3-2; Enough reduce the state that stylizes of critical voltage to the target of the storage area of getting in touch with selected control grid 603-3, left side, this band is worn then with symbol 627 expressions band.

Figure 44 and Figure 45 read bias arrangement for the counter-rotating on the left side of the memory cell of Figure 39 and right side.Use the bias arrangement among Figure 44 that the storage area in left side is read, the storage area in this left side for example is the charge storaging area 604-5-1 of control grid 603-5 below.According to the bias arrangement among Figure 44, not selected control grid 603-1～603-4 and 603-6～603-N receives the for example high voltage of about+10V, and selected control grid 603-5 receives the Vg of pact+2V ₅Electrode 601 receives the Vs of about 0V, and electrode 602 receives the Vd of pact+2V.Likewise, substrate receives the Vb of about 0V.High relatively voltage on not selected control grid produces reversal zone 635,636, and wherein reversal zone 635,636 couples the channel region of electrode 601,602 to control grid 603-5 below.If charge storaging area 604-5-1 has high critical voltage state (erasing), then electric current be locked in electrode 601, between 602.Selectively, if charge storaging area 604-5-1 has low critical voltage state (stylizing), then at electrode 601, cause electric current between 602.This electric current can be represented that data storage is in charge storaging area 604-5-1 by detecting.

Use the bias arrangement among Figure 45 that the storage area on right side is read, the storage area on this right side for example is the charge storaging area 604-3-2 of control grid 603-3 below.According to the bias arrangement among Figure 45, not selected control grid 603-1,603-2 and 603-4～603-N receives the for example high voltage of about+10V, and selected control grid 603-3 receives the Vg of pact+2V ₅Electrode 601 receives the Vs of pact+2V, and electrode 602 receives the Vd of about 0V.Likewise, substrate receives the Vb of about 0V.High relatively voltage on not selected control grid produces reversal zone 645,646, and wherein reversal zone 645,646 couples the channel region of electrode 601,602 to control grid 603-3 below.If charge storaging area 604-3-2 has high critical voltage state (erasing), then electric current be locked in electrode 601, between 602.Selectively, if charge storaging area 604-3-2 has low critical voltage state (stylizing), then at electrode 601, cause electric current between 602.This electric current can be represented that data storage is in charge storaging area 604-3-2 by detecting.

Figure 46 to Figure 51 is the typical embodiment of the array layout of multiple grid memory body, and it uses the symbol among Figure 11.Illustrated array layout can use the embodiment at independent and a plurality of bits of each memory cell of each memory cell, and is as described before, is included in each storage area of getting in touch with each control grid and stores the embodiment that surpasses a bit.

Figure 46 is the first layout embodiment, and wherein multiple grid memory cell 700～706 has structure shown in Figure 180, and multiple grid memory cell 700～706 is along with bit line BL _N-3～BL _N+3Layout.Be arranged in parallel the character line to transmit bias voltage Vg ₁～Vg _NThe grid of extremely being correlated with in the multiple grid memory cell.Bit line BL _N-3～BL _N+3Be arranged transmit bias voltage Vs and bias voltage Vd one of them, pass the lower electrode of selecting grid 710～716 to multiple grid memory cell 700～706 respectively.Select grid 710～716 to be coupled to the bias line of arranging with the character line parallel, and delivery controlling signal SLG2.In addition, bit line BL _N-3To bit line BL _N+3Arrangement transmits another among bias voltage Vs and the bias voltage Vd, passes the electrode to top of selecting grid 720～726 to multiple grid memory cell 700～706 respectively.Select grid 720～726 to be coupled to the bias line of arranging with the character line parallel, and delivery controlling signal SLG1.Bit line BL _N-3～BL _N+3Generally on integrated circuit, use metal level to implement, and use source electrode or the drain electrode that is coupled to selection grid 710～716 or selection grid 720～726 like contact window 718,728.In illustrated array layout, multiple grid memory cell 706 is respectively through selecting grid 716,726 and bit line BL _N+3, BL _N+2Couple.Multiple grid memory cell 705 is respectively through selecting grid 715,725 and bit line BL _N+1, BL _N+2Couple.Multiple grid memory cell 704 is respectively through selecting grid 714,724 and bit line BL _N+1, BL _NCouple.Multiple grid memory cell 703 is respectively through selecting grid 713,723 and bit line BL _N-1, BL _NCouple.Multiple grid memory cell 702 is respectively through selecting grid 712,722 and bit line BL _N-1, BL _N-2Couple.Multiple grid memory cell 701 is respectively through selecting grid 711,721 and bit line BL _N-3, BL _N-2Couple.Multiple grid memory cell 700 is respectively through selecting grid 710,720 and bit line BL _N-3, BL _N-4(not illustrating) couples.In the embodiment of Figure 46, the multiple grid memory cell is arranged in parallel, and selects grids to come being connected of multiple grid memory cell independent in the array of controls and bit line with two.The source electrode of two adjacent parallel memory cells is coupled in together, and is coupled to independent bit line.Likewise, the drain of two adjacent parallel memory cells is coupled in together, and is coupled to independent bit line.

Figure 47 is selectable layout embodiment, and wherein multiple grid memory cell 700～706 has structure shown in Figure 180, and multiple grid memory cell 700～706 is along with bit line BL _N-3To bit line BL _N+3Layout.Be arranged in parallel the character line to transmit bias voltage Vg ₁～Vg _NThe grid of extremely being correlated with in the multiple grid memory cell.Bit line BL _N-3～BL _N+3Be arranged transmit bias voltage Vs and bias voltage Vd one of them, pass the upper electrode of selecting grid 720～726 to multiple grid memory cell 700～706 respectively.In addition, the horizontal source electrode line 719 that forms with the doped region that buries or metal level is arranged and transmits bias voltage Vs, passes the lower electrode of selecting grid 710～716 to multiple grid memory cell 700～706 respectively.Select grid 710～716 to be coupled to the bias line of arranging with the character line parallel, and delivery controlling signal SLG2.Bit line BL _N-3～BL _N+3Generally on integrated circuit, use metal level to implement, and use the drain electrode that is coupled to selection grid 720～726 like contact window 728.In illustrated array layout, multiple grid memory cell 706 is respectively through selecting grid 716,726 and bit line BL _N+3, source electrode line 719 couples.Multiple grid memory cell 705 through select grid 725 respectively with bit line BL _N+2, source electrode line 719 couples.Multiple grid memory cell 704 through select grid 724 respectively with bit line BL _N+1, source electrode line 719 couples.Multiple grid memory cell 703 through select grid 723 respectively with bit line BL _N, source electrode line 719 couples.Multiple grid memory cell 702 is respectively through selecting grid 722 and bit line BL _N-1, source electrode line 719 couples.Multiple grid memory cell 701 is respectively through selecting grid 721 and bit line BL _N-2, source electrode line 719 couples.Multiple grid memory cell 700 is respectively through selecting grid 720 and bit line BL _N-3, source electrode line 719 couples.In the embodiment of Figure 47, the source electrode of whole parallel memory cells is coupled in together in this district, and is coupled to the horizontal source electrode line vertical with bit line direction.The drain of each multiple grid memory cell is coupled to independent bit line, and not shared with contiguous bit line.

Figure 48 is another layout embodiment, and it is similar with the layout among Figure 46.Arrange and select grid 720～726 and 710～716, by once only there being a multiple grid memory cell to be connected to a bit line, so that decoding function to be provided.Specifically, select the gate electrode of grid 721,723 and 725 to be coupled to controlling signal SLG1, and select the gate electrode of grid 720,722,724 and 726 to be coupled to controlling signal SLG2.Likewise, select the gate electrode of grid 711,713 and 715 to be coupled to controlling signal SLG4, and select the gate electrode of grid 710,712,714 and 716 to be coupled to controlling signal SLG3.In addition configuration is all said similar with Figure 46.In the embodiment of Figure 48, select grid to control the independent multiple grid memory cell of being connected to of bit line by two.The source electrode of two adjacent parallel memory cells is coupled in together, and is coupled to independent bit line.Likewise, the drain of two adjacent parallel memory cells is coupled in together, and is coupled to independent bit line.Selecting grid is to be used for controlling contiguous parallel memory cell can not be connected to shared bit line at one time.

Figure 49 is the 3rd layout embodiment, and wherein multiple grid memory cell 740～746 has structure shown in Figure 20, and multiple grid memory cell 740～746 is along with bit line BL _N-3To bit line BL _N+3Layout.Be arranged in parallel the character line to transmit bias voltage Vg ₁～Vg _NThe grid of extremely being correlated with in the multiple grid memory cell.Bit line BL _N-3～BL _N+3Be arranged and transmit bias voltage Vs and one of them upper electrode of bias voltage Vd respectively to multiple grid memory cell 740～746.

Top control grid 750～756 in the multiple grid memory cell is coupled to the bias line of arranging with the character line parallel, and delivery controlling signal SLG1.In addition, bit line BL _N-3～BL _N+3Arrange transmit respectively among bias voltage Vs and the bias voltage Vd another extremely multiple grid memory cell 740～746 to lower electrode.Bottom control grid 760～766 is coupled to the bias line of arranging with the character line parallel, and delivery controlling signal SLG2.Bit line BL _N-3～BL _N+3Generally on integrated circuit, use metal level to implement, and use source electrode or the drain electrode that is coupled to selection grid 710～716 or selection grid 720～726 like contact window 748,749.In illustrated array layout, multiple grid memory cell 746 is coupled to bit line BL respectively _N+3, BL _N+2, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 746 control grid and bottom control grid.Multiple grid memory cell 745 is coupled to bit line BL respectively _N+1, BL _N+2, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 745 control grid and bottom control grid.Multiple grid memory cell 744 is coupled to bit line BL respectively _N+1, BL _N, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 744 control grid and bottom control grid.Multiple grid memory cell 743 is coupled to bit line BL respectively _N-1, BL _N, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 743 control grid and bottom control grid.Multiple grid memory cell 742 is coupled to bit line BL respectively _N-1, BL _N-2, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 742 control grid and bottom control grid.Multiple grid memory cell 741 is coupled to bit line BL respectively _N-3, BL _N-2, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 741 control grid and bottom control grid.Multiple grid memory cell 740 is coupled to bit line BL respectively _N-3, BL _N-4(not illustrating) is to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 740 control grid and bottom control grid.Operate top control grid and bottom control grid in each memory cell and keep the storage area got in touch with it, allow top control grid and bottom in each memory cell to control grid and can replace like the selection grid 710～716 and 720～726 in the array implement example of Figure 46 at low critical voltage state.In the embodiment of Figure 49, the multiple grid memory cell is arranged in parallel, and selects grids to come being connected of multiple grid memory cell independent in the array of controls and bit line with two.The source electrode of two adjacent parallel memory cells is coupled in together, and is coupled to independent bit line.Likewise, the drain of two adjacent parallel memory cells is coupled in together, and is coupled to independent bit line.

Figure 50 is the 4th layout embodiment, and wherein multiple grid memory cell 740～746 has structure shown in Figure 20, and multiple grid memory cell 740～746 is along with bit line BL _N-3～BL _N+3Layout.Be arranged in parallel the character line to transmit bias voltage Vg ₁～Vg _NThe grid of extremely being correlated with in the multiple grid memory cell.Bit line BL _N-3～BL _N+3Be arranged and transmit the upper electrode of bias voltage Vd respectively to multiple grid memory cell 740～746.Top control grid 750～756 in the multiple grid memory cell is coupled to the bias line of arranging with the character line parallel, and delivery controlling signal SLG1.In addition, the horizontal source electrode line 769 that forms with the doped region that buries or metal level is arranged and transmits the lower electrode of bias voltage Vs to multiple grid memory cell 740～746.Bottom control grid 760～766 is coupled to the bias line of arranging with the character line parallel, and delivery controlling signal SLG2.Bit line BL _N-3～BL _N+3Generally on integrated circuit, use metal level to implement, and use the drain electrode that is coupled to the multiple grid memory cell like contact window 758.In illustrated array layout, multiple grid memory cell 746 is coupled to bit line BL respectively _N+3With source electrode line 769, to respond signal SLG1, the SLG2 on the top of the multiple canopy utmost point memory cell 746 control canopy utmost point and bottom control grid.Multiple grid memory cell 745 is coupled to bit line BL respectively _N+2With source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 745 control grid and bottom control grid.Multiple grid memory cell 744 is coupled to bit line BL respectively _N+1With source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 744 control grid and bottom control grid.Multiple grid memory cell 743 is coupled to bit line BL respectively _NWith source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 743 control grid and bottom control grid.Multiple grid memory cell 742 is coupled to bit line BL respectively _N-1With source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 742 control grid and bottom control grid.Multiple grid memory cell 741 is coupled to bit line BL respectively _N-2With source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 741 control grid and bottom control grid.Multiple grid memory cell 740 is coupled to bit line BL respectively _N-3With source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 740 control grid and bottom control grid.Operate top control grid and bottom control grid in each memory cell and keep the storage area got in touch with it, allow top control grid and bottom in each memory cell to control grid and can replace like the selection grid 710～716 and 720～726 in the array implement example of Figure 47 at low critical voltage state.In the embodiment of Figure 50, the source electrode of whole parallel memory cells is coupled in together in this district, and is coupled to the horizontal source electrode line vertical with bit line direction.The drain of each multiple grid memory cell is coupled to independent bit line, and not shared with contiguous bit line.

Figure 51 is the layout of memory body block, and this memory body block comprises a plurality of sections of multiple grid memory cell, and these sections are similar with the section among Figure 46.This kind layout also can be utilized in the section structure of Figure 47 to Figure 50.In Figure 51, show first section 800 and second section 801.Between first section 800 and these two sections of the shared position of second section 801 in contact hole 802,803,804 and 805.First section 800 and the position shared contact hole 806,807 and 808 of section on it, this two section has identical layout.Likewise, second section 801 and the position shared contact hole 809,810 and 811 of section on it, this two section has identical layout.Repeat above-mentioned section forming a memory body block, and repeat these blocks on integrated circuit, to form a big array.In alternate embodiments, first section 800 and second section 801 can dispose with the mirror image mode around shared contact hole.Array can be utilized in the highdensity memory cell shown in figure 27, and this array comprises most memory body blocks shown in Figure 51.

In the embodiment of Figure 46 to Figure 48 and Figure 51, though each select grid between a multiple grid memory cell is only arranged, other embodiment be included in each select grid between surpass a multiple grid memory cell.Likewise, Figure 48 and Figure 49 illustrate between the contact hole that is connected to the bit line or be connected between the contact hole of the bit line in the horizontal source electrode line, in memory cell array, have the array of independent multiple grid memory cell.In other embodiments; A plurality of multiple grid memory cells can be arranged in memory cell array; Upper gate with memory cell array middle and upper part multiple grid memory cell is selected grid as top, and selects grid with the bottom grid of memory cell array middle and lower part multiple grid memory cell as the bottom.

The highdensity memory body that above-described technology provides each memory cell can store a plurality of bits, single processing made between it can use.In addition, stylize and the operation of erasing can utilize low-power to carry out.

Though the present invention discloses as above with embodiment; Right its is not in order to limiting the present invention, anyly has the knack of this art, in spirit that does not break away from the present invention and scope; When can doing a little change and retouching, so the claim person of defining that the present invention's protection range attaches after looking is as the criterion.

Claims

1. An integrated circuit memory element, comprising:

a semiconductor body;

A plurality of gates are arranged in series on the semiconductor body, and a plurality of isolation members are used to isolate the adjacent gates, and the isolation members fill the gaps between the adjacent gates, and the gates form a row of gates, the gates including a first gate and a final gate in the row of gates;

a charge storage structure disposed on the semiconductor body, the charge storage structure includes a plurality of charge trapping regions, the charge trapping regions are located in the gates in the series between the first gate and the final gate below, and the charge trapping regions under the gate row are connected to each other, and each charge trapping region includes a left storage region and a right storage region;

a first circuitry for conducting source bias and drain bias to the semiconductor body in the row of gates near the first gate and near the last gate; and

a second circuitry for conducting gate bias to the gates;

Wherein the semiconductor body includes a continuous multiple gate channel region, the multiple gate channel region is located under the gates in the gate column, and the multiple gate channel region has n-type conductivity and p-type conductivity sex one of them.

2. The integrated circuit memory device according to claim 1, wherein the charge trapping region is located under all of the gates.

3. The integrated circuit memory device of claim 1 , wherein the first circuitry includes a first conductive material arranged as a bit line, and the second circuitry includes a second conductive material arranged as a word line. conductive material.

4. The integrated circuit memory device of claim 1 , wherein the first circuitry includes a first conductive material arranged as a bit line, the first gate in the semiconductor body adjacent to the gate column. One of the poles is located in the semiconductor body adjacent to a second electrode region of the final gate in the gate column, wherein the first electrode region and the second electrode region have one of n-type conductivity and p-type conductivity 1; and an element adapted to selectively connect at least one of the first electrode region and the second electrode region to a bit line.

5. The integrated circuit memory device of claim 1 , wherein the first circuitry includes a first conductive material arranged as a bit line, the first gate in the semiconductor body adjacent to the gate column. One of the poles is located in the semiconductor body adjacent to a second electrode region of the final gate in the gate column, wherein the first electrode region and the second electrode region have one of n-type conductivity and p-type conductivity one.

6. The integrated circuit memory device of claim 1 , wherein the first circuitry includes a bit line including an additional gate adjacent to the first gate of the gate column and located at Above the multiple gate pass region, when selected, the additional gate is coupled to the decode circuitry and the multiple gate pass region is coupled to the bit line.

7. The integrated circuit memory device according to claim 1, wherein the first circuitry comprises a first bit line and a second bit line, the first bit line and the second bit line comprise a first additional gate adjacent to the first gate of the gate row and over the multiple gate pass region and a first additional gate adjacent to the final gate of the gate row and over the multiple gate pass region a second additional gate, when selected, the first additional gate and the second additional gate are coupled to decoding circuitry and the multi-gate channel region is coupled to the first bit line and the Second bit line.

8. The integrated circuit memory device according to claim 1, wherein the charge storage structure comprises a stack dielectric layer, a charge trapping dielectric layer and a top dielectric layer, wherein the stack dielectric layer comprises a bottom dielectric layer layer.

9. The integrated circuit memory device according to claim 1, wherein the charge storage structure comprises a stack dielectric layer, a charge trapping dielectric layer and a top dielectric layer, wherein the stack dielectric layer comprises a bottom dielectric layer layer, and wherein the charge trapping dielectric layer is composed of silicon nitride.

10. The integrated circuit memory device of claim 1 , further comprising a controller controlling the first circuitry and the second circuitry to establish a bias configuration to cause electron injection to tunnel to the charge trapping region , wherein the charge trapping region is located under a selected gate in the column of gates.

11. The integrated circuit memory device according to claim 1 , wherein the gate column comprises more than two gates, and the charge storage structure comprises a plurality of gate columns located under more than two of the gates charge trapping area.

12. An integrated circuit memory element, comprising:

a semiconductor body;

a plurality of word lines extending through the semiconductor body;

a plurality of bit lines aligned perpendicularly to the word lines through the semiconductor body;

a decoding circuitry on the semiconductor body, and the decoding circuitry is coupled to the word lines and the bit lines;

An array, including a plurality of multiple gate storage units, the array is coupled to the word lines and the bit lines, wherein the multiple gate storage units respectively include:

A plurality of gates are arranged in a gate column, and the gates are respectively coupled to word lines in the word lines, wherein the plurality of gates include a first gate and a first gate in the gate column. a final gate, and insulating members are used to isolate the adjacent gates in the gate row, and the insulating members fill the gap between the adjacent gates;

a charge storage structure on the semiconductor body, the charge storage structure comprising a plurality of charge trapping regions under the gates in the row of gates between the first gate and the final gate, and The charge trapping regions under the gate column are connected to each other, and each charge trapping region includes a left storage region and a right storage region respectively; and

A multiple gate channel region, the multiple gate channel region is continuous and located under the gates in the gate column, wherein the multiple gate channel region has n-type conductivity and p-type conductivity, wherein one of; and

a source electrode and a drain electrode located near the first gate and the final gate in the gate column, and at least one of the source electrode and the drain electrode is coupled to the bits One bit line in line.

13. The integrated circuit memory device according to claim 12, wherein the charge trapping region is located under all the gates, and the charge trapping regions under the gate series are connected to each other.

14. The integrated circuit memory device according to claim 12 , wherein the source electrode comprises a first electrode region adjacent to the first gate in the gate row in the semiconductor body, and the drain electrode comprises A second electrode region is adjacent to the final gate in the gate column in the semiconductor body, wherein the first electrode region and the second electrode region have one of n-type conductivity and p-type conductivity.

15. The integrated circuit memory device according to claim 12 , wherein the source electrode comprises a first electrode region adjacent to the first gate in the gate row in the semiconductor body, and the drain electrode comprises a second electrode region in the semiconductor body adjacent to the final gate in the gate column, wherein the first electrode region and the second electrode region have one of n-type conductivity and p-type conductivity; and a An element, coupled to the decoding circuit system, is suitable for selectively connecting at least one of the first electrode area and the second electrode area to the bit lines.

16. The integrated circuit memory device according to claim 12, wherein each of the multiple gate storage cells comprises an additional gate adjacent to the first gate of the gate column and located between the multiple gate channel region Above, when selected, the additional gate is coupled to the decoding circuitry and the multiple gate channel region is coupled to one of the source electrode and the drain electrode.

17. The integrated circuit memory device of claim 12, wherein the charge storage structure comprises a stack dielectric layer, a charge trapping dielectric layer and a top dielectric layer, wherein the stack dielectric layer comprises a bottom dielectric layer layer.

18. The integrated circuit memory device of claim 12, wherein the charge storage structure comprises a stack dielectric layer, a charge trapping dielectric layer and a top dielectric layer, wherein the stack dielectric layer comprises a bottom dielectric layer layer, and wherein the charge trapping dielectric layer is composed of silicon nitride.

19. The integrated circuit memory device according to claim 12 , further comprising a controller coupled to the word lines and the bit lines to establish the multi-gate memory cells in the array A biasing arrangement that causes electron injection to tunnel to the charge trapping region, wherein the charge trapping region is located under a selected gate in the column of gates.

20. The integrated circuit memory device according to claim 12 , further comprising a controller coupled to the word lines and the bit lines to establish the multi-gate memory cells in the array A biasing arrangement that causes electron emission to tunnel to the charge trapping region, wherein the charge trapping region is located under a selected gate in the column of gates.

21. The integrated circuit memory device according to claim 12 , wherein the gate column comprises more than two gates, and the charge storage structure comprises a plurality of gate columns located under more than two of the gates charge trapping area.

22. The integrated circuit memory device of claim 12, further comprising a controller coupled to the word lines and the bit lines to establish a plurality of bias configurations in the array for The multiple gate memory cells are read, programmed and erased.

23. A method of operating an integrated circuit memory element, the integrated circuit memory element comprising a semiconductor body, a plurality of gates arranged in series on the semiconductor body and forming a gate column, on the semiconductor body The gates in the gate row have a first gate and a final gate, and the adjacent gates in the gate row are isolated by insulating members, and the insulating members fill up the adjacent gates and a charge storage structure on the semiconductor body, wherein the charge storage structure includes a plurality of gates located under the gates between the first gate and the final gate in the gate column charge storage regions, and the charge storage regions under the gate row are connected to each other, and each charge storage region includes a left storage region and a right storage region respectively, wherein the semiconductor body includes a charge storage region located under the gates in the gate row A continuous multiple gate channel region having one of n-type conductivity and p-type conductivity; the method of operating the integrated circuit memory device includes applying a bias to a selected gate Voltage configuration to program data, the bias configuration includes:

applying a base bias condition to the semiconductor body in the multiple gate channel region;

applying a source bias condition to the semiconductor body near one of the first gate and the final gate in the gate row;

applying a drain bias condition to the semiconductor body near the other of the first gate and the final gate in the gate row; and

applying a plurality of gate bias conditions to the gates in the gate row, wherein the gate bias conditions include a programming voltage and an inversion voltage, wherein the selected gate in the gate row The programming voltage on the gate is sufficient to reduce the electron injection current to the charge trapping region under the selected gate relative to the substrate bias condition to establish a high threshold voltage state in the gate row The inversion voltage on the other gates is sufficient to reduce the inversion in the multiple gate pass region without effective electron injection into the charge storage regions below the other gates, wherein the multiple gate pass region located below these other gates.

24. The method of operating an integrated circuit memory device according to claim 23, further comprising applying a bias configuration for reading, the bias configuration comprising:

applying a plurality of gate bias conditions to the gates in the row of gates, wherein the gate bias conditions include relative to the substrate bias condition on the selected gate in the row of gates a read voltage, the read voltage is higher than the threshold voltage of the low threshold voltage state, and the gate bias conditions include a reverse bias on other gates in the gate column, the reverse voltage Sufficiently reducing inversion in the multiple gate channel region under the other gates, the inversion voltage is higher than the threshold voltage of the high threshold voltage state.

25. The method for operating an integrated circuit memory device according to claim 24, further comprising applying a bias configuration for erasing, the bias configuration comprising:

applying a plurality of gate bias conditions to the gates in the gate column, wherein the gate bias conditions include a plurality of voltages sufficient to cause electron ejection or hole injection from the charge trapping regions The charge trapping regions are used to establish a low threshold voltage state, wherein the charge trapping regions are located under the gates in the gate row.