CN113206141A - Multi-gate transistor and memory device using same - Google Patents
Multi-gate transistor and memory device using same Download PDFInfo
- Publication number
- CN113206141A CN113206141A CN202010472715.2A CN202010472715A CN113206141A CN 113206141 A CN113206141 A CN 113206141A CN 202010472715 A CN202010472715 A CN 202010472715A CN 113206141 A CN113206141 A CN 113206141A
- Authority
- CN
- China
- Prior art keywords
- gate
- channel
- sub
- voltage
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
Abstract
The invention discloses a multi-gate transistor and a memory device using the same, the multi-gate transistor comprises: a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region are positioned at two sides of the channel; and an intermediate layer formed between the channel and the gate group. After a first grid voltage and a second grid voltage are respectively applied to the first grid and the second grid of the grid group, at least one P sub-channel and at least one N sub-channel are induced in the channel, and the multi-grid transistor is equivalent to have a positive-negative-positive (PNPN) structure.
Description
Technical Field
The invention relates to a multi-gate transistor and a memory device using the same.
Background
With the rapid development of Artificial Intelligence (AI), big data analysis, etc., a hardware accelerator (hardware accelerator) has attracted more and more attention. For hardware accelerators, neural computing (neurosurgical computing) is the mainstream architecture because of its high computation and low power consumption.
Integrated-and-Fire (IF) circuits play an important role in neuromorphic computing. The main function of the integrated delivery circuit is to generate precise pulses to represent data by the number of pulses. Currently, the integrated circuit requires a large number of capacitors and differential amplifiers, and additional circuits are required to improve the fault tolerance and adjust the pulse frequency. Therefore, the circuit area of the integrated distribution circuit is not easy to shrink.
Disclosure of Invention
According to an embodiment of the present invention, a multi-gate transistor is provided, including: a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region are positioned at two sides of the channel; and an intermediate layer formed between the channel and the gate group. After a first grid voltage and a second grid voltage are respectively applied to the first grid and the second grid of the grid group, at least one P sub-channel and at least one N sub-channel are induced in the channel, and the multi-grid transistor is equivalent to have a positive-negative-positive (PNPN) structure.
According to another embodiment of the present invention, a memory device is provided, which includes: a memory array including a plurality of memory cells, a plurality of word lines, and a plurality of bit lines; a data transfer circuit coupled to the memory array; an integrated issue circuit coupled to the data transfer circuit, the data transfer circuit sending a plurality of operation results of the units of the memory array to the integrated issue circuit, the integrated issue circuit generating a plurality of pulses according to the operation results of the units of the memory array, wherein a number of the pulses represents the operation results of the units; and a control circuit coupled to the integrated distribution circuit and the memory array, the control circuit sending a control signal to the integrated distribution circuit and the memory array according to the pulses generated by the integrated distribution circuit, wherein the integrated distribution circuit comprises a multi-gate transistor as described above.
According to another embodiment of the present invention, there is provided a multi-gate transistor including: a doped drain region; a doped source region; a gate group including a first gate and a second gate; a doped channel, the doped drain region and the doped source region are positioned at two sides of the doped channel; and an intermediate layer formed between the doped channel and the gate group, wherein a first gate voltage and a second gate voltage are respectively applied to the first gate and the second gate of the gate group to enhance the channel sensing capability of the doped channel, and the multi-gate transistor is equivalent to have a positive-negative-positive (PNPN) structure.
For a better understanding of the above and other aspects of the invention, reference should be made to the following detailed description of the embodiments, taken in conjunction with the accompanying drawings, in which:
drawings
FIG. 1 is a functional block diagram of a memory device according to an embodiment of the invention.
Fig. 2A to 2F are schematic diagrams illustrating a multi-gate transistor according to an embodiment of the invention.
Fig. 3A to 3C are schematic diagrams illustrating a multi-gate transistor according to another embodiment of the invention.
[ notation ] to show
100 memory device
110 memory array
120 data transfer circuit
130 integrated dispensing circuit
140 control circuit
C is capacitor
T1 multiple-gate transistor
T2 suppressor transistor
INV inverter
T3 bias transistor
G1-G3 gate
D is drain region
S is source region
210 intermediate layer
220 undoped channel
220_1 to 220_3 sub-channels
310 intermediate layer
320 undoped channel
320_1 to 320_2 sub-channels
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
The technical terms in the specification refer to the technical terms commonly used in the field, for example, the technical terms are explained or defined by the specification, and the technical terms are interpreted according to the specification or the definition of the specification. Various embodiments of the present invention each have one or more technical features. A person skilled in the art may selectively implement some or all of the features of any of the embodiments, or selectively combine some or all of the features of the embodiments, where possible.
Referring to fig. 1, a functional block diagram of a memory device according to an embodiment of the invention is shown. The memory device 100 of FIG. 1 may be used as an emulated neural hardware accelerator, although the invention is not limited thereto. The memory device 100 includes: a memory array 110, a data transfer circuit (data transfer circuit)120, an integrated issue circuit 130, and a control circuit 140.
The memory array 110 includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. The architecture of the memory array 110 may not be particularly limited herein. The memory cells of the memory array 110 may be used to perform operations such as, but not limited to, Multiply and Accumulate (MAC) operations.
The data transmission circuit 120 is coupled to the memory array 110 for transmitting the operation results of the units of the memory array 110 to the integration and distribution circuit 130.
The integration and issue circuit 130 is coupled to the data transmission circuit 120 for generating pulses according to the operation results of the units of the memory array 110, wherein the number of the pulses may represent the operation results of the units.
The control circuit 140 is coupled to the integrated issue circuit 130 and the memory array 110. The control circuit 140 may send a control signal to the integrated distribution circuit 130 and the memory array 110 according to the pulse generated by the integrated distribution circuit 130 to adjust the pulse frequency, thereby improving the error tolerance.
The integrated issuing circuit 130 includes: a capacitor C, a multi-gate transistor T1, an inhibit transistor T2, an inverter INV, and a bias transistor T3.
The capacitor C is coupled to the data transmitting circuit 120 for temporarily storing the data transmitted from the data transmitting circuit 120.
The multi-gate transistor T1 is a transistor having at least 2 or more gates. The details of the multi-gate transistor T1 will be described further below. The multi-gate transistor T1 is coupled to the data transmission circuit 120, the inverter INV and the bias transistor T3. In particular, the multi-gate transistor T1 has a gate coupled to the capacitor C, a source grounded, and a drain coupled to the inverter INV.
The suppressor transistor T2 is coupled to the control circuit 140 and controlled by a control signal transmitted by the control circuit 140. When the control signal controls the suppressor transistor T2 to be turned on, the suppressor transistor T2 may form a discharge path, so that the capacitor C is discharged.
The inverter INV has an input terminal coupled to the multi-gate transistor T1 and the bias transistor T3, and an output terminal coupled to the control circuit 140. The inverter INV may output a pulse to the control circuit 140.
The bias transistor T3 has a gate receiving a bias voltage VA, a source coupled to the operating voltage VDD, and a drain coupled to the inverter INV.
Referring now to fig. 2A to 2F, schematic diagrams of a multi-gate transistor T1 according to an embodiment of the invention are shown. As shown in fig. 2A to 2F, the multi-gate transistor T1 includes: gates G1, G2 and G3, drain region (D), source region (S), interlayer (interlayer)210 and undoped channel 220. The drain region (D) is doped as a P + region and the source region (S) is doped as an N + region. The drain voltage VD and the source voltage VS applied to the drain region (D) and the source region (S) are, for example, but not limited to, +3V and 0V, respectively. In fig. 2A to 2F, the gate G1 of the multi-gate transistor T1 is coupled to the capacitor C. The gates G1, G2, and G3 may also be referred to as a gate group. The drain region (D) and the source region (S) are located at both sides of the undoped channel 220. In the following description, the channel is an undoped channel, but it should be understood that the invention is not limited thereto. In other possible embodiments of the present invention, the channel may also be a doped channel, which is also within the scope of the present invention.
The intermediate layer 210 may be, for example, but not limited to, a gate oxide layer or a charge storage layer. The charge storage layer may be, for example, but not limited to, a floating gate (floating gate) or a charge trapping structure (charge trapping structure). The charge trapping structure can be, for example, but not limited to, a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) layer or a tapered band Silicon-Oxide-Nitride-Oxide-Silicon (bensonos) layer.
The undoped channel 220 is sensed (induce) out of the three sub-channels 220_1, 220_2, and 220_3 according to gate voltages VG1, VG2, and VG3 applied to the gates G1, G2, and G3. In detail, the gate voltage VG1 applied to the gate G1 can induce the sub-channel 220_1 under the gate G1; the gate voltage VG2 applied to the gate G2 can induce the sub-channel 220_2 under the gate G2; and a gate voltage VG3 applied to the gate G3 can induce the sub-channel 220_3 under the gate G3.
In particular, if the gate voltage is less than the threshold voltage (Vth), a P-sub-channel will be induced under the gate; and if the gate voltage is greater than the threshold voltage (Vth), then an N-subchannel will be induced under the gate.
Referring to fig. 2C, VG1< Vth, VG2> Vth, and VG3> Vth, so the three sensed sub-channels 220_1, 220_2, and 220_3 are P sub-channel, N sub-channel, and N sub-channel, respectively. Therefore, as shown in fig. 2C, the multi-gate transistor T1 behaves like a PNPN structure, that is, from the right to the left in the drawing, the drain region, the three sub-channels and the source region are respectively a P + region, an N sub-channel, a P sub-channel, an N sub-channel and an N + region, so that the PNPN (positive and negative) structure can be equivalently regarded as the PNPN structure.
Further, in the embodiment of the invention, taking fig. 2C as an example, VG1< Vth, VG2> Vth, VG3> Vth are applied first to induce three sub-channels 220_1, 220_2 and 220_3, which are P sub-channel, N sub-channel and N sub-channel, respectively. After sensing the three sub-channels, the applied voltage VG1 can be removed (but voltages VG2 and VG3 are still maintained to keep the channels sensing). Then, when the memory device 100 is applied to the AI operation, the gate voltage of the gate G1 of the multi-gate transistor T1 is determined by the capacitor C and the inhibit transistor T2. That is, when the suppressor transistor T2 is turned off, the voltage across the capacitor C is the gate voltage of the gate G1 of the multi-gate transistor T1; and when the suppressor transistor T2 is turned on, the capacitor C is discharged and the gate voltage of the gate G1 of the multi-gate transistor T1 is 0V. Therefore, when the gate voltage of the gate G1 of the multi-gate transistor T1 (i.e., the voltage across the capacitor C) exceeds the threshold voltage, the multi-gate transistor T1 is turned on to output a pulse from the drain to the inverter INV; and, when the gate voltage of the gate G1 of the multi-gate transistor T1 (i.e., the voltage across the capacitor C) does not exceed the threshold voltage, the multi-gate transistor T1 is turned off and no pulse is output from the drain to the inverter INV.
Referring to fig. 2D, VG1< Vth, VG2< Vth, VG3> Vth, so the three sensed sub-channels 220_1, 220_2 and 220_3 are P sub-channels, P sub-channels and N sub-channels, respectively. Therefore, as shown in fig. 2D, the multi-gate transistor T1 behaves like a PNPN structure, i.e., from the right to the left in the drawing, the drain region, the three sub-channels and the source region are respectively a P + region, an N sub-channel, a P sub-channel and an N + region, and thus can be regarded as a PNPN structure.
Referring to fig. 2E, VG1> Vth, VG2< Vth, VG3> Vth, so the three sensed sub-channels 220_1, 220_2 and 220_3 are N, P and N sub-channels, respectively. Therefore, as seen in fig. 2E, the multi-gate transistor T1 behaves like a PNPN structure, i.e., from the right to the left in the drawing, the drain region, the three sub-channels and the source region are respectively a P + region, an N sub-channel, a P sub-channel and an N + region, and thus can be regarded as a PNPN structure.
Referring to fig. 2F, VG1> Vth, VG2< Vth, and VG3< Vth, so the three sensed sub-channels 220_1, 220_2, and 220_3 are N sub-channels, P sub-channels, and P sub-channels, respectively. Therefore, as shown in fig. 2F, the multi-gate transistor T1 behaves like a PNPN structure, i.e., from the right to the left in the drawing, the drain region, the three sub-channels and the source region are respectively a P + region, an N sub-channel, a P sub-channel and an N + region, and thus can be regarded as a PNPN structure.
Referring now to fig. 3A to 3C, schematic diagrams of a multi-gate transistor T1 according to another embodiment of the invention are shown. As shown in fig. 3A to 3C, the multi-gate transistor T1 includes: gates G1-G2, drain region (D), source region (S), interlayer 310, and undoped channel 320. In fig. 3A to 3C, the gate G1 of the multi-gate transistor T1 is coupled to the capacitor C.
The undoped channel 320 is induced into two sub-channels 320_1 and 320_2 according to the gate voltages VG1 and VG2 applied to the gates G1 and G2. In detail, the gate voltage VG1 applied to the gate G1 can induce the sub-channel 320_1 under the gate G1; and a gate voltage VG2 applied to the gate G2 can induce the sub-channel 320_2 under the gate G2.
In particular, if the gate voltage is less than the threshold voltage (Vth), a P-sub-channel will be induced under the gate; and if the gate voltage is greater than the threshold voltage (Vth), then an N-subchannel will be induced under the gate.
Referring to FIG. 3C, VG1> Vth, VG2< Vth, so that the two sensed sub-channels 320_1 and 320_2 are N sub-channel and P sub-channel, respectively. Therefore, as shown in fig. 3C, the multi-gate transistor T1 behaves like a PNPN structure, i.e., from the right to the left in the drawing, the drain region, the two sub-channels and the source region are respectively a P + region, an N sub-channel, a P sub-channel and an N + region, and thus can be regarded as a PNPN structure.
Of course, the present invention is not limited to the above examples, and the skilled person can deduce how to control the gate voltage so that the multi-gate transistor T1 behaves like a PNPN structure from the above description.
In other possible embodiments of the present invention, the channel may also be a doped channel, which is also within the scope of the present invention. When the channel is a doped channel, the channel sensing capability can also be enhanced by controlling the gate voltages applied to the multi-gate transistor, so that the multi-gate transistor (including the doped channel) behaves like a PNPN structure. In addition, in other possible embodiments of the present invention, regardless of the doping type of the doped channel of the multi-gate transistor, the multi-gate transistor (including the doped channel) can behave as a PNPN structure by controlling the gate voltage.
In addition, in other possible embodiments of the invention, the multi-gate transistor T1 may include 4 gates or more, which are not repeated as the principle is described above.
In the embodiment of the present invention, the multi-gate transistor T1 has at least 2 gates, and its channel is not doped, but the voltage control gate is used to form N-sub-channel and P-sub-channel in the undoped channel.
In an embodiment of the present invention, the multi-gate transistor T1 may generate a V-I (voltage-current) graph with a super-steep slope. When the multi-gate transistor T1 is turned on, the multi-gate transistor T1 generates a pulse (the potential of the pulse is the voltage across the capacitor C) to the inverter INV at the rear end. The control circuit 140 may output a control signal to a next stage or transmit the control signal back to the present stage for subsequent processing.
In the embodiment of the present invention, the multi-gate transistor T1 has a very small sub-threshold swing (SS), so the power consumption is also small.
The memory device of the embodiment of the invention can be applied to AI identification and steady state (homeostatis) operation and has the advantages of high identification rate, low power consumption and the like.
In the embodiment of the invention, the integrated transmitting circuit has the ultra-steep sub-threshold swing multi-gate transistor, so that a differential amplifier with a large circuit area can be completely replaced, and a timing accurate pulse (pulse) can be generated. In addition, by adjusting the threshold voltage of the multi-gate transistor, the multi-gate transistor itself can achieve frequency normalization (frequency normalization), so no additional circuit is required. Therefore, the memory device (which can be used for realizing a hardware accelerator) of the embodiment of the invention has the advantage of small circuit area.
In addition, the ultra-steep sub-threshold swing multi-gate transistor has high tolerance (high tolerance) to process variation (process variation) and circuit noise (circuit noise).
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202062967604P | 2020-01-30 | 2020-01-30 | |
| US62/967,604 | 2020-01-30 | ||
| US16/877,518 US11081595B1 (en) | 2020-01-30 | 2020-05-19 | Multi-gate transistor and memory device using the same |
| US16/877,518 | 2020-05-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113206141A true CN113206141A (en) | 2021-08-03 |
| CN113206141B CN113206141B (en) | 2025-05-13 |
Family
ID=77024946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010472715.2A Active CN113206141B (en) | 2020-01-30 | 2020-05-29 | Multi-gate transistor and memory device using the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113206141B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09265786A (en) * | 1996-03-28 | 1997-10-07 | Nec Corp | Semiconductor storage |
| CN1722445A (en) * | 2004-07-06 | 2006-01-18 | 旺宏电子股份有限公司 | Charge trapping non-volatile memory and method of operation thereof |
| CN102201453A (en) * | 2010-03-25 | 2011-09-28 | 台湾积体电路制造股份有限公司 | Memory cell and nonvolatile memory device and method of forming the same |
| CN104241284A (en) * | 2013-06-06 | 2014-12-24 | 旺宏电子股份有限公司 | Dual-mode transistor device and method of operation thereof |
| CN108985447A (en) * | 2018-06-15 | 2018-12-11 | 华中科技大学 | A kind of hardware pulse nerve network system |
-
2020
- 2020-05-29 CN CN202010472715.2A patent/CN113206141B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09265786A (en) * | 1996-03-28 | 1997-10-07 | Nec Corp | Semiconductor storage |
| CN1722445A (en) * | 2004-07-06 | 2006-01-18 | 旺宏电子股份有限公司 | Charge trapping non-volatile memory and method of operation thereof |
| CN102201453A (en) * | 2010-03-25 | 2011-09-28 | 台湾积体电路制造股份有限公司 | Memory cell and nonvolatile memory device and method of forming the same |
| CN104241284A (en) * | 2013-06-06 | 2014-12-24 | 旺宏电子股份有限公司 | Dual-mode transistor device and method of operation thereof |
| CN108985447A (en) * | 2018-06-15 | 2018-12-11 | 华中科技大学 | A kind of hardware pulse nerve network system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113206141B (en) | 2025-05-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI723878B (en) | Multi-gate transistor and memory device using the same | |
| US10818333B2 (en) | Circuitry for one-transistor synapse cell and operation method of the same | |
| Diorio et al. | Adaptive CMOS: from biological inspiration to systems-on-a-chip | |
| US9048830B2 (en) | Circuits for soft logical functions | |
| US8633732B2 (en) | Circuits for soft logical functions | |
| US11699721B2 (en) | Integrate-and-fire neuron circuit using single-gated feedback field-effect transistor | |
| Lu et al. | Optimal weight models for ferroelectric synapses toward neuromorphic computing | |
| CN113206141A (en) | Multi-gate transistor and memory device using same | |
| CN113903378B (en) | Ferroelectric transistor-based delay modulation method | |
| US20030098476A1 (en) | Synapse element with learning function and semiconductor integrated circuit device including the synapse element | |
| CN103279322B (en) | The threshold logic type carry lookahead adder that SET/MOS hybrid circuit is formed | |
| CN112836812B (en) | Neural network based on floating gate transistor | |
| Bikki et al. | Analysis of low power SRAM design with leakage control techniques | |
| Sowparna et al. | A proposal of energy efficient ferroelectric pdsoi lif neuron for spiking neural network applications | |
| KR102565801B1 (en) | Neuromorphic computing system | |
| CN112819148B (en) | Pulse neuron network based on floating gate transistor | |
| CN215730881U (en) | Bit unit and data analysis unit | |
| CN115688897B (en) | Low-power-consumption compact Relu activation function neuron circuit | |
| Chodankar et al. | Low power SRAM design using independent gate FinFET at 30nm technology | |
| Sharma et al. | Design and Performance Analysis of 4-input Multiplexer Tree using FGMOS | |
| CN215731719U (en) | A bit unit and data parsing unit | |
| US20230292533A1 (en) | Neural network system, high efficiency embedded-artificial synaptic element and operating method thereof | |
| CN116486850B (en) | Sense amplifying circuit, method and semiconductor memory | |
| CN118484622B (en) | Matrix multiplier circuit and method based on SRAM IMC | |
| US20230289577A1 (en) | Neural network system, high density embedded-artificial synaptic element and operating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |