CN113903378B - Ferroelectric transistor-based delay modulation method - Google Patents
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Abstract
The invention provides a delay modulation method based on a ferroelectric transistor, belonging to the field of neural network accelerators. The method constructs a delay modulation unit circuit which comprises an inverter structure formed by a ferroelectric transistor, an N-type MOSFET and a P-type MOSFET; wherein, the drain terminal of FeFET is connected to the source terminal of NMOS in the inverter, the source terminal of FeFET is connected to GND; during programming operation, the FeFET gate receives programming voltage pulses higher than the coercive voltage of the ferroelectric layer, and ferroelectric polarization overturning adjusts the threshold voltage of the device to realize weight programming; during local multiplication calculation operation, the gate end of the FeFET is biased at a voltage representing a non-destructive read mode of the input of the neural network, an initial calculation pulse acts on the input end of the inverter of the delay modulation unit, and the delay time of an output pulse relative to the input pulse is the result of local multiplication calculation. The invention can obviously reduce the hardware cost and is beneficial to the realization of large-scale time domain neural network accelerator chips.
Description
Technical Field
The invention relates to a neural network accelerator, in particular to a delay modulation method based on a ferroelectric transistor.
Background
With the explosive development of information technology, the human society has been moving into the era of "data explosion", and the data volume exponentially growing each year brings unprecedented pressure to the processing and calculation of data. Due to the architecture characteristics of the traditional von neumann computing architecture, the transmission of data between a storage unit and a computing unit causes a great deal of power consumption and energy consumption waste, and the problem becomes more and more serious in the background that the information society and even the intelligent society are accompanied by a huge data volume nowadays.
Researchers are inspired by a brain operation mode, a neural network (Neural Network) calculation architecture is provided, a distributed calculation network with integrated memory and high parallelism is constructed based on a connection mode of neurons, synapses and neurons, the processing efficiency of complex data is improved, and meanwhile, the problems of power consumption and energy consumption caused by a memory wall in the traditional von neumann calculation architecture can be avoided. In a classical artificial neural network (ARTIFICIAL NEURAL NETWORK), input feature vectors and weight matrices are subjected to vector matrix point multiplication to generate output vectors, and output activation value vectors are obtained through an activation function, wherein the dominant operation is multiply-accumulate operation. Currently, artificial neural networks have demonstrated computational efficiencies in image recognition, natural language processing, autopilot, and the like that exceed conventional general purpose computing units.
The artificial neural network architecture finally realizes the hardware of the whole network, and can completely get rid of the limitation of the bottleneck of the memory wall. Based on nonvolatile memory devices such as a resistance change memory device and a phase change memory device, the built in-memory computing architecture can accelerate the dominant multiply-accumulate operation in the artificial neural network and improve the energy efficiency of computation. The numerical information of the multiplication and addition operation is usually expressed as an analog voltage amplitude or current amplitude signal in the circuit, and a higher working voltage is required to ensure a higher signal dynamic range, so that the improvement of the energy efficiency of the system is limited. In order to solve the problem of scaling of working voltage, a time domain mixed signal calculation utilizing the accumulated propagation delay characteristic of an inverter chain is proposed to realize addition operation in vector matrix dot multiplication, the architecture is digital compatible, the analog signals accumulated in calculation are expressed on the delay time length, the dynamic range of the signals is irrelevant to the voltage, scaling of the working voltage of a system can be realized, and higher energy efficiency is expected to be realized. At present, only a time domain calculation delay modulation unit based on SRAM (static random Access memory) needs an additional current limiting circuit or an adjustable capacitance module to realize multiplication operation in vector matrix dot multiplication, so that the problem of high hardware cost and power consumption is faced.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention aims to provide a delay modulation method based on a ferroelectric transistor, which utilizes the polarization of a conventional ferroelectric transistor FeFET to gradually turn over under the action of gate voltage pulse, and gradually adjusts the threshold voltage of the FeFET, thereby adjusting the channel conductivity characteristic and realizing the storage of the neural network weight; and utilizing the characteristic of the three-terminal controllable switch of the FeFET to realize the local multiplication operation of the input value and the weight in the neural network.
The technical scheme provided by the invention is as follows:
A delay modulation method based on ferroelectric transistor is characterized in that: firstly, a delay modulation unit circuit based on ferroelectric transistors is constructed, and the circuit comprises: an inverter composed of an N-type ferroelectric transistor FeFET, an N-type MOSFET (NMOS) and a P-type MOSFET (PMOS); wherein the source end of the N-type ferroelectric transistor FeFET is connected with the ground potential, and the drain end of the N-type ferroelectric transistor is connected with the source end of the NMOS in the inverter; in the stage of programming the magnitude of the stored weight value of the FeFET, a programming voltage pulse (V program) which is higher than the coercive voltage (V C) of the ferroelectric layer and can enable ferroelectric polarization to be reversed acts on the gate end of the FeFET, changes the polarization state of the ferroelectric layer, adjusts the threshold voltage of the FeFET, and thus programs the stored weight (weight, w); when partial multiplication operation is carried out, an initial calculation pulse is input to the input end of an inverter in the delay modulation unit; an input voltage signal (x-input, V x) below the coercive voltage of the ferroelectric layer, which does not disrupt the ferroelectric polarization state, acts on the FeFET gate terminal, the FeFET operating in a non-destructive readout mode; when V x acts on the FeFET gate to make it fully on, corresponding to the case of input x=0, it can provide a higher pull-down drive current than NMOS in the inverter, where the propagation delay of the delay modulation unit is very negligible and, independently of the stored weights, represents a local multiplication operation x·w=0; when V x acts on the FeFET to make its driving capability weaker than the NMOS in the inverter, the pull-down current and delay time of the delay modulation unit are determined by the weights stored in the FeFET, corresponding to the case of input x=1, representing the local multiplication operation x·w=w. In summary, the local multiplication operation x·w may be implemented in FeFET-based delay-modulation units, the accumulation operation may be implemented by cascaded delay-modulation unit circuits, and the vector matrix multiplication may be implemented in a delay-modulation unit array.
The ferroelectric transistor-based delay modulation method can be expanded to realize the subarray topological structure of inverter multiplexing: an inverter composed of NMOS and PMOS, wherein the source end of NMOS is connected with the drain ends of a plurality of FeFETs which respectively represent the weight storage of a multi-layer network in the neural network to form a subarray; each feedforward multiply-accumulate operation only uses one layer of weight of the neural network to operate, and only one FeFET is in a working state, namely the gate end voltage of the FeFET is V x; the gate terminals of other FeFETs in the subarray are connected with a voltage V sel for turning off the FeFET channels, so that the FeFETs are in an off state; the propagation delay due to the partial multiplication of the delay modulation unit is determined only by the input V x and the selected weight FeFET. The sub-array topology of the inverter multiplexing can further improve the area efficiency of the system.
The FeFET used in the ferroelectric transistor-based delay modulation method of the invention has the following characteristics: when voltage is applied to the gate terminal so that the partial voltage of the ferroelectric layer is larger than the ferroelectric coercive voltage, the ferroelectric polarization is gradually reversed, namely programming voltage pulse is applied to the gate, so that the threshold voltage of the FeFET device can be adjusted step by step; when a voltage is applied to the gate terminal so that the partial pressure of the ferroelectric layer is lower than the ferroelectric coercive voltage, the FeFET operates in a non-destructive readout mode and can be used as a controllable switch. The FeFET used in the ferroelectric transistor-based delay modulation unit circuit of the present invention may be any ferroelectric transistor device having the above typical characteristics based on MFMIS, MFIS, MFS or the like, which is made of conventional ferroelectric materials such as perovskite type ferroelectric (PZT, BFO, SBT) and ferroelectric polymer (P (VDF-TrFE)), or HfO 2 Zr (HZO), hfO 2 Al (HfAlO), hfO 2 Si, hfO 2 Y, or the like, and HfO 2 doped ferroelectric materials.
Compared with the traditional MOSFET-based implementation mode, the ferroelectric transistor-based delay modulation method can obviously reduce hardware cost on the premise of realizing the local multiplication function of a time domain.
The ferroelectric transistor-based delay modulation method has the beneficial effects that:
1. The delay modulation method based on the ferroelectric transistor utilizes the gradual regulation and control effect of ferroelectric gradual polarization inversion on the threshold voltage of the ferroelectric transistor under the action of programming voltage higher than the coercive voltage of the ferroelectric layer, realizes the nonvolatile storage of the multivalue weight in the time domain neural network operation, obviously reduces the hardware cost compared with the implementation mode of the traditional CMOS circuit, and does not need a multi-bit SRAM storage unit to realize the storage of the multivalue weight in the time domain multiply-accumulate operation.
2. The time delay modulation method based on the ferroelectric transistor utilizes the characteristic of a controllable switch of the ferroelectric transistor with a three-terminal structure when a nondestructive read voltage lower than the coercive voltage of a ferroelectric layer acts on a gate terminal, and can realize the partial multiplication operation of a time domain time delay modulation unit only by an FeFET and an inverter consisting of NMOS and PMOS; the accumulated propagation delay characteristic of the inverter chain is utilized, the time domain accumulation operation is realized based on the cascade of the delay modulation units of the FeFET, and the time domain vector matrix multiplication operation can be realized by the array formed by the delay modulation units. Compared with the traditional implementation mode of the CMOS circuit, the hardware cost is obviously reduced, and a multiplication operation in multiply-accumulate is realized without an additional current limiting circuit or a variable capacitance module.
3. The ferroelectric transistor-based delay modulation method utilizes the channel turn-off characteristic of the ferroelectric transistor with a three-terminal structure under the action of non-destructive readout voltage, can realize the subarray topological structure of inverter multiplexing, realizes the localized storage and operation of the multi-layer weights of the neural network, and can further improve the area efficiency of the multiply-accumulate neural network acceleration circuit based on the time domain delay modulation unit.
Drawings
FIG. 1 is a schematic diagram of one embodiment of a ferroelectric transistor based delay modulation cell circuit of the present invention;
FIG. 2 is a schematic diagram of an array of ferroelectric transistor delay modulation cell circuits according to the present invention;
fig. 3 is a schematic diagram of a sub-array topology of inverter multiplexing of ferroelectric transistor based delay modulation cells.
In the figure:
1-input calculation pulse of time delay modulation unit
2-Delay of output pulse of delay modulation unit relative to input pulse
3-Ferroelectric transistor-based delay modulation unit circuit
Detailed Description
The invention will be further elucidated by means of specific embodiments in conjunction with the accompanying drawings.
The present embodiment implements a conventional ferroelectric transistor FeFET using Hf 0.5Zr0.5O2 ferroelectric material.
As shown in fig. 1, the present embodiment is a ferroelectric transistor-based delay modulation unit circuit including FeFET, NMOS, and PMOS; wherein NMOS and PMOS form an inverter structure; the drain end of the FeFET is connected with the source end of the inverter NMOS, the source end of the FeFET is connected with GND, and the gate end is used as a weight programming port and a neural network input port; in the programming weight stage, a programming voltage higher than a ferroelectric coercive voltage (V C) for programming the weight state of the FeFET acts on the gate terminal of the FeFET, and the threshold voltage of the FeFET, namely the weight size, is regulated; in the time domain calculation stage, the input x of the neural network acts on the gate terminal of the FeFET by the voltage V x, the initial input calculation pulse acts on the input terminal of the inverter, and the delay time of the output pulse relative to the initial input pulse is modulated by the value of the input x and the weight value stored in the FeFET, so that the local multiplication operation of the time domain is realized. The invention is based on an array structure formed by ferroelectric transistor delay modulation unit circuits, as shown in figure 2, each row of the array is a plurality of cascaded delay modulation unit circuits, and the array comprises a plurality of rows operated in parallel. The weight matrix of the neural network is stored in FeFETs of each unit in the array, and the input vector acts on each row of cascaded delay modulation unit circuits; the addition operation in the vector matrix dot multiplication is obtained by accumulating propagation delay through each row of cascaded delay modulation unit circuits.
As shown in fig. 3, this example is a sub-array topology based on inverter multiplexing of a ferroelectric transistor-based delay modulation unit circuit, including a plurality of FeFET cells and one inverter composed of NMOS and PMOS; wherein the drain terminals of the FeFETs are connected in parallel to the source terminal of the inverter NMOS; the gate of the FeFET receives either the input signal V x or the select signal V sel.
For a delay modulation unit based on FeFET, positive or negative gate voltage pulse is applied to the gate end of the FeFET in a programming stage, so that the partial voltage of a ferroelectric layer is larger than the coercive voltage of the ferroelectric layer, the ferroelectric polarization can be gradually turned over, the polarization turning quantity is positively related to the number of the applied pulses, and multi-value weight storage can be realized on the FeFET; in the operation stage, a non-destructive read voltage V x (such as V x＝0＝1.3V;Vx＝1＝0.7V),Vx and the pull-down current of a FeFET weight local product modulation delay modulation unit) is applied to the gate end of the FeFET, an initial calculation pulse is applied to the input end of an inverter of the delay modulation unit, and the output delay delta t is the operation result of local multiplication.
The delay modulation unit based on the ferroelectric transistor can be expanded to realize the subarray topological structure of the multiplexing of the inverter; the plurality of FeFETs respectively store weight connections of different layers in the neural network, for the operation of a certain layer of the neural network, only store FeFET action gate voltage V x (such as V x＝0＝1.3V;Vx＝1 =0.7V) of the weight of the layer to realize local multiplication operation, and the rest FeFET action gate voltages V sel(Vsel =0V) enable the FeFETs which do not participate in the operation to be in an off state; when an initial computation pulse is applied to the inverter input of the modulation unit of the multiplexing inverter, the propagation delay is determined only by the local product of the layer weight and the input. In conclusion, the invention can further reduce the hardware cost of the system.
Finally, it should be noted that the examples are disclosed for the purpose of aiding in the further understanding of the present invention, but those skilled in the art will appreciate that: various alternatives and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the disclosed embodiments, but rather the scope of the invention is defined by the appended claims.
Claims (3)
1. A delay modulation method based on ferroelectric transistor is characterized in that firstly, a delay modulation unit circuit based on ferroelectric transistor is constructed, and the delay modulation unit circuit comprises a plurality of inverters composed of N-type ferroelectric transistors FeFET, an N-type MOSFET and a P-type MOSFET; wherein the source end of the N-type ferroelectric transistor FeFET is connected with the ground potential, and the source end of the NMOS is connected with the drain ends of one or more N-type ferroelectric transistors FeFET; in the stage of programming the magnitude of the weight value stored in the N-type ferroelectric transistor FeFET, programming voltage pulse higher than the coercive voltage of the ferroelectric layer acts on the gate end of the N-type ferroelectric transistor FeFET, the polarization state of the ferroelectric layer is changed, and the threshold voltage of the N-type ferroelectric transistor FeFET is adjusted, so that the stored weight is programmed; when partial multiplication operation is carried out, an initial calculation pulse is input to the input end of an inverter in the delay modulation circuit; when an input voltage signal lower than the coercive voltage of the ferroelectric layer acts on the gate terminal of the N-type ferroelectric transistor FeFET, the N-type ferroelectric transistor FeFET works in a nondestructive read-out mode; representing a partial multiplication operation; When the input voltage signal acts on the N-type ferroelectric transistor FeFET to make its driving capability weaker than that of NMOS in the inverter, the pull-down current and delay time of the delay modulation circuit are determined by the weight stored in the N-type ferroelectric transistor FeFET, representing the local multiplication operation/>Each N-type ferroelectric transistor FeFET in the delay modulation unit circuit respectively represents the weight storage of a multi-layer network in the neural network to form a subarray; each feedforward multiply-accumulate operation only uses one layer of weight of the neural network to operate, only one N-type ferroelectric transistor FeFET is in a working state, and the gate ends of other N-type ferroelectric transistors FeFETs in the subarray are connected with a low voltage which is read nondestructively and is in an off state; the delay modulation circuit is determined only by the selected weight N-type ferroelectric transistor FeFET,
The delay modulation unit circuits form a delay modulation unit array through cascading, and vector matrix multiplication is realized in the delay modulation unit array.
2. The ferroelectric transistor-based delay modulation method according to claim 1, wherein said N-type ferroelectric transistor FeFET is based on MFMIS, MFIS, MFS structures.
3. The ferroelectric transistor based time delay modulation method according to claim 1, wherein said N-type ferroelectric transistor FeFET is made of perovskite ferroelectric, ferroelectric polymer material or HfO 2 Zr-doped, hfO 2 Al-doped, hfO 2 Si-doped, hfO 2 Y-doped material.
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