CN119495341A - A matrix computing device based on flexible RRAM storage and computing array - Google Patents
A matrix computing device based on flexible RRAM storage and computing array Download PDFInfo
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Abstract
The invention relates to a matrix operation device based on a flexible RRAM (resistive random Access memory) memory array, belongs to the technical field of integrated circuits, and solves the problem that the area of the memory array cannot be reduced under the condition of not affecting the precision in the prior art. The device comprises a flexible RRAM storage array, a multiplexer MUX, a subtractor and a matrix, wherein the flexible RRAM storage array outputs accumulated currents of all column storage units according to a plurality of rows of inputs, the multiplexer MUX selects one column of accumulated currents from all column storage units to send to the ADC, the ADC converts the received accumulated currents into digital signals to be sent to the subtractor, the popcount module receives the plurality of rows of inputs and obtains the number of 1 in the plurality of rows of inputs to be output to the multiplier, the multiplier multiplies the number of 1 by a fixed value beta and sends the product result to the subtractor, and the subtractor subtracts the product result from the digital signals to obtain the multiplication and addition result of the matrix. The high-precision calculation function of the small-area calculation array is realized, the energy efficiency is further improved, and the small-area calculation array is applied to a flexible calculation chip to manufacture electronic skin.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a matrix operation device based on a flexible RRAM memory array.
Background
At present, the trend of artificial intelligence perception research is that a machine can be more humanoid, and electronic skin can endow an intelligent robot with a touch perception function, so that great revolution is expected to be brought to the robot technology. The development direction of the electronic skin for touch perception is to integrate sensing, storage and operation into a whole to construct a sensing and storage integrated framework, so that the power consumption bottleneck of data carrying of the von neumann framework is solved, and the whole efficiency is improved by combining with sensing. Traditional von neumann architecture suffers from "memory wall bottleneck", and is high in power consumption and slow in speed, while in-memory computing technology can realize a more efficient computing system, and reduce computing power consumption. Since the convolution operation of a large number of multiply-add is a core component in the deep learning algorithm, in-memory computation and in-memory logic are well suited for artificial intelligence deep neural network applications and AI-based big data techniques. And BNN (Binarized Neural Networks) algorithm can reduce memory occupation, power consumption and area cost on the premise of keeping certain calculation precision, and improves calculation speed, so that the method is very suitable for edge calculation. RRAM (Resistive Random Access Memory) resistive random access memory, which is a novel nonvolatile memory, is always considered to be a novel device most likely to break through the limitation of the traditional device due to the advantages of simple structure, high integration level, low power consumption and the like, and is applied to in-memory calculation.
While flexible pressure sensor designs have achieved many achievements, flexible computing chips are still under investigation, which is also required to create truly flexible electronic skins. In-memory computing chips based on RRAM currently use XNOR operation based on 2T2R (2 RRAM and 2 MOS transistors to form a memory cell), so in order to further improve energy efficiency and apply the same to flexible computing chips to create electronic skins, a matrix computing device of flexible memory array based on 1T1R structure of flexible RRAM and IGZO TFT is needed.
Disclosure of Invention
In view of the above analysis, an embodiment of the present invention is directed to providing a matrix computing device based on a flexible RRAM memory array, so as to solve the problem that the memory array in the prior art has a large size and cannot be applied to electronic skin.
In one aspect, the embodiment of the invention provides a matrix operation device based on a flexible RRAM storage array, which comprises the flexible RRAM storage array, a multiplexer MUX, an analog-to-digital converter ADC, a popcount module, a multiplier and a subtracter;
The flexible RRAM storage and calculation array outputs the accumulated current of each column storage and calculation unit to a multiplexer MUX according to a plurality of rows of input and output;
The multiplexer MUX selects one column from the column storage units and sends the accumulated current of the column storage units to the analog-to-digital converter ADC;
The analog-to-digital converter ADC is used for converting the accumulated current output by the RRAM storage array into a digital signal and transmitting the digital signal to the subtracter;
The popcount module receives the multi-line input, acquires the number of 1 in the multi-line input, and outputs the number of 1 to the multiplier;
The multiplier multiplies the number of 1 by a fixed value beta and sends the product result to the subtracter;
The subtracter subtracts the product result from the digital signal to obtain the multiplication and addition result of the matrix.
Further, the flexible RRAM memory array comprises n×m memory units;
The word lines WL of each row of memory calculation units are sequentially connected, the source lines SL of each column of memory calculation units are sequentially connected, the bit lines BL of each column of memory calculation units are sequentially connected, and the bit lines BL are used for outputting the calculation results of the column of memory calculation units;
Each memory cell is of a 1T1R structure and comprises a transistor and a memristor.
Further, the transistor is an indium gallium zinc oxide thin film transistor IGZO TFT, and the memristor is RRAM;
And the grid electrode of the indium gallium zinc oxide thin film transistor IGZO TFT is connected with the word line WL of the memory cell, the drain electrode of the indium gallium zinc oxide thin film transistor IGZO TFT is connected with the bit line BL of the memory cell, the source electrode of the indium gallium zinc oxide thin film transistor IGZO TFT is connected with one end of the memristor RRAM, and the other end of the memristor RRAM is connected with the source line SL of the memory cell.
Further, the working modes of the flexible RRAM storage array comprise a writing weight mode and an reasoning working mode.
Furthermore, in the writing weight working mode, the connection voltages of the word line WL, the bit line BL and the source line SL are controlled, so that the resistance state of the memristor RRAM is changed, and thus the weight writing is realized.
Further, when the word line WL is connected to the high level, the bit line BL is connected to the write voltage Vw, and the source line SL is grounded, the conductance state of the memristor RRAM is the low-resistance state LRS, and the weight is assigned to be β+1;
When the word line WL is connected with a high level, the bit line BL is grounded, and the source line SL is connected with the write voltage Vw, the conductivity state of the memristor RRAM is a high-resistance state HRS, and the weight is assigned to be beta-1;
When the word line WL is connected to low level, it indicates that the memristor RRAM is not selected, and the resistance state of the memristor RRAM remains unchanged.
Further, the write weight mode adopts a half-voltage method, the write voltage Vw is greater than the threshold voltage of the memristor RRAM, and the half write voltage Vw is less than the threshold voltage of the memristor RRAM, so as to ensure that the state of the unselected memristor RRAM remains unchanged.
Further, in the reasoning working mode state, the bit line BL is connected to the read voltage Vr, the source line SL is grounded, the input of the memory cell is determined according to the high level or the low level of the bit line WL, the current value output by the memory cell is used as the product of the memory cell input and the memristor RRAM weight, and the currents output by the memory cells in each row of memory cells are converged in the bit line corresponding to the row of memory cells, so that the bit line output is the sum of the products of the memory cells in the row.
Further, when the word line WL is connected to a high level and the resistance state of the memristor RRAM is a high resistance state HRS, the input of the memory cell is 1, the low current I L is output, and the value of the low current I L is β -1;
When the word line WL is connected with a high level and the resistance state of the memristor RRAM is a low resistance state LRS, the input of the memory cell is 1, the high current I H is output, and the value of the high current I H is beta+1;
When the word line WL is connected to the low level, the IGZO TFT is turned off, the memory cell is not connected, and the input of the memory cell is 0, and the output current of the memory cell is 0.
Further, the β >1.
Compared with the prior art, the invention has at least one of the following beneficial effects:
1. According to the application, the flexible RRAM storage array of the 1T1R unit structure is selected, the indium gallium zinc oxide thin film transistor IGZO TFT and the memristor in the 1T1R unit structure are flexible structures, and compared with the traditional 2T2R structure, the flexible storage array has the advantages that the storage array area is doubled under the condition that the calculation accuracy is not affected, the energy efficiency is further improved, and the flexible characteristics are more suitable for being applied to manufacturing electronic skin.
2. The design of peripheral circuits such as an analog-to-digital converter ADC, a popcount module, a multiplier, a subtracter and the like improves the calculation accuracy of the matrix operation.
In the invention, the technical schemes can be mutually combined to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, like reference numerals being used to refer to like parts throughout the several views.
FIG. 1 is a circuit block diagram of a flexible RRAM memory array;
FIG. 2 is a table of computational encodings of RRAM memory arrays based on a 1T1R structure;
Fig. 3 is an overall circuit block diagram of an RRAM memory array.
Detailed Description
The following detailed description of preferred embodiments of the application is made in connection with the accompanying drawings, which form a part hereof, and together with the description of the embodiments of the application, are used to explain the principles of the application and are not intended to limit the scope of the application.
In one embodiment of the present invention, a matrix computing device based on a flexible RRAM memory array is disclosed, as shown in FIG. 1. The device comprises a flexible RRAM memory array, a multiplexer MUX, an analog-to-digital converter ADC, a popcount module, a multiplier and a subtracter;
The flexible RRAM storage and calculation array outputs the accumulated current of each column storage and calculation unit to a multiplexer MUX according to a plurality of rows of input and output;
The multiplexer MUX selects one column from the column storage units and sends the accumulated current of the column storage units to the analog-to-digital converter ADC;
The analog-to-digital converter ADC is used for converting the accumulated current output by the RRAM storage array into a digital signal and transmitting the digital signal to the subtracter;
The popcount module receives the multi-line input, acquires the number of 1 in the multi-line input, and outputs the number of 1 to the multiplier;
The multiplier multiplies the number of 1 by a fixed value beta and sends the product result to the subtracter;
The subtracter subtracts the product result from the digital signal to obtain the multiplication and addition result of the matrix.
Specifically, the function of the multiplier is to multiply the input by a fixed beta value, where the beta value is determined by the RRAM memory array performance,
For example, when the matrix is multiplied by [1,0,1,0,1] [ +1, -1, -1, -1], that is, the multiple row input is [1,0,1,0,1], a column weight of the RRAM memory array is [ +1, -1, -1, -1], the multiplication and addition result is-1, the multiple row input of the corresponding RRAM memory array is 10101, the resistance states of the corresponding RRAM cells are respectively β+1, β -1, and the accumulated current output by the RRAM memory array is input to the multiplexer, the multiplexer outputs the accumulated current of the column memory array to the analog-to-digital converter ADC, the current digital signal with the size of 3β -1 is output to the subtractor after the analog-to-digital conversion, the output of the popcount module is 3, and the output of the multiplier is-1, so that the scheme is completely consistent with the original multiplication and addition result.
Further, the flexible RRAM memory array comprises n×m memory units;
The word lines WL of each row of memory calculation units are sequentially connected, the source lines SL of each column of memory calculation units are sequentially connected, the bit lines BL of each column of memory calculation units are sequentially connected, and the bit lines BL are used for outputting the calculation results of the column of memory calculation units;
Each memory cell is of a 1T1R structure and comprises a transistor and a memristor.
Further, the transistor is an indium gallium zinc oxide thin film transistor IGZO TFT, and the memristor is RRAM;
And the grid electrode of the indium gallium zinc oxide thin film transistor IGZO TFT is connected with the word line WL of the memory cell, the drain electrode of the indium gallium zinc oxide thin film transistor IGZO TFT is connected with the bit line BL of the memory cell, the source electrode of the indium gallium zinc oxide thin film transistor IGZO TFT is connected with one end of the memristor RRAM, and the other end of the memristor RRAM is connected with the source line SL of the memory cell.
Further, the working modes of the flexible RRAM storage array comprise a writing weight mode and an reasoning working mode.
Specifically, when the bit line BL or the source line SL is connected to the write voltage Vw, the working mode of the flexible RRAM memory array is a write weight mode, and when the bit line BL is connected to the read voltage Vr, the working mode of the flexible RRAM memory array is an inference working mode.
Specifically, the input voltages of the word lines, the bit lines and the source lines connected by the array are controlled through the periphery fpga, namely, the word lines WL are connected with high level or low level so as to control the on-off of the transistors, whether the current memory cell is gated or not is selected, when the word lines WL are connected with high level, the transistors are conducted, namely, the memory cell is gated, and when the word lines WL are connected with low level, the transistors are not conducted, namely, the memory cell is not gated.
Furthermore, in the writing weight working mode, the connection voltages of the word line WL, the bit line BL and the source line SL are controlled, so that the resistance state of the memristor RRAM is changed, and thus the weight writing is realized.
Further, when the word line WL is connected to the high level, the bit line BL is connected to the write voltage Vw, and the source line SL is grounded, the conductance state of the memristor RRAM is the low-resistance state LRS, and the weight is assigned to be β+1;
When the word line WL is connected with a high level, the bit line BL is grounded, and the source line SL is connected with the write voltage Vw, the conductivity state of the memristor RRAM is a high-resistance state HRS, and the weight is assigned to be beta-1;
When the word line WL is connected to low level, it indicates that the memristor RRAM is not selected, and the resistance state of the memristor RRAM remains unchanged.
In the writing weight mode, the high-low resistance state of the RRAM is set by controlling the writing voltage Vw and the on-off state of a transistor of the memory unit, so that the arrangement of the weight in the RRAM array is completed, the output of the source line SL and the bit line BL are grounded or connected with the writing voltage, and the word line WL controls the on-off state of the transistor to control the weight writing of the RRAM in the memory unit. For example, when the word line WL <0> is connected to high, the source line SL is connected to ground, and the bit line BL is connected to a write voltage, the RRAM is programmed to a low resistance state.
Specifically, in the write weight mode and the inference mode of operation, since the memristor RRAM is a nonvolatile device, after the write weight mode completes the resistive state setting of the RRAM, the resistive state of the memristor RRAM is fixed and does not change unless a new programming voltage is applied to the word line WL, the bit line BL, and the source line SL.
Further, the write weight mode adopts a half-voltage method, the write voltage Vw is greater than the threshold voltage of the memristor RRAM, and the half write voltage Vw is less than the threshold voltage of the memristor RRAM, so as to ensure that the state of the unselected memristor RRAM remains unchanged.
Further, in the reasoning working mode state, the bit line BL is connected to the read voltage Vr, the source line SL is grounded, the input of the memory cell is determined according to the high level or the low level of the bit line WL, the current value output by the memory cell is used as the product of the memory cell input and the memristor RRAM weight, and the currents output by the memory cells in each row of memory cells are converged in the bit line corresponding to the row of memory cells, so that the bit line output is the sum of the products of the memory cells in the row.
Further, as shown in fig. 2, when the word line WL is connected to a high level and the resistance state of the memristor RRAM is a high resistance state HRS, the input of the register unit is 1, the low current I L is output, and the value of the low current I L is β -1;
When the word line WL is connected with a high level and the resistance state of the memristor RRAM is a low resistance state LRS, the input of the memory cell is 1, the high current I H is output, and the value of the high current I H is beta+1;
When the word line WL is connected to the low level, the IGZO TFT is turned off, the memory cell is not connected, and the input of the memory cell is 0, and the output current of the memory cell is 0.
The whole RRAM array can realize multiply-add calculation function under the reasoning working mode state, and the on-off of the TFT transistor is controlled through the word line WL, so that the input is realized, namely, when the word line WL is connected with high level, the TFT transistor is turned on, namely, the memory unit is gated to represent the input as 1, and when the word line WL is connected with low level, the transistor is turned off, namely, the unit is not connected, and the input is represented as 0. The source line SL is connected with the ground terminal, and the bit line BL is connected with the read voltage Vr and obtains corresponding accumulated current, namely a multiplication and addition result. The RRAM represents a weight distribution by a programmed high-low resistance state, and when one bit line BL of the RRAM array is selected, a current I H or I L is generated according to different high-resistance states or low-resistance states. For example, when the word line WL <0> is high and the RRAM is in a high resistance state, the memory cell generates the reference current I L, which represents the calculation result of the cell as β -1 (β > 1), and so on for the calculation case of a whole row of memory cells, the accumulated current obtained at the output bit line BL is the multiplication and addition result of a row of memory cells. Thus, only one TFT transistor and one RRAM may be used as one memory cell, thereby forming a memory array.
According to the scheme, the storage array area is doubled under the condition that the calculation accuracy is not affected, and the energy efficiency of the whole calculation chip can be improved by combining a peripheral circuit. In addition, the flexible IGZO TFT and the flexible RRAM are used as basic devices, a completely flexible memory array is constructed, and a matrix operation device based on the flexible RRAM memory array is constructed by combining a peripheral circuit, so that a good foundation is provided for subsequent manufacturing of complete electronic skin. Based on the RRAM storage array, a binary multiply-accumulate calculation mode is provided, and a good foundation is provided for the subsequent implementation of a hardware circuit for intelligent algorithm.
Further, the β >1.
Specifically, the application is equivalent to a modified binary calculation, the input of the word line WL is whether the control transistor is turned on or not, the high resistance state and the low resistance state of the memristor RRAM are determined by controlling the voltages accessed by the bit line BL and the source line SL in the writing weight mode, and the high resistance state and the low resistance state are actually positive values, so the low resistance state and the high resistance state are respectively encoded into beta+1 and beta-1, the output also correspondingly changes in the reasoning working mode, and the output is also binary high current and low current.
Further, the flexible RRAM memory array has a size of 64×64 and a total capacity of 4Kb.
Compared with the prior art, the matrix operation device based on the flexible RRAM storage array provided by the embodiment of the application has the advantages that the flexible RRAM storage array of a 1T1R unit structure is selected, the indium gallium zinc oxide thin film transistor IGZO TFT and the memristor in the 1T1R unit structure are of flexible structures, compared with the traditional 2T2R structure, the area of the storage array is reduced by one time under the condition that the calculation precision is not affected, the energy efficiency is further improved by combining with a peripheral circuit, and the flexible characteristic of the matrix operation device is more suitable for being applied to manufacturing electronic skin. The application provides a binary multiply-accumulate calculation mode based on the RRAM storage array, and provides a good foundation for realizing a hardware circuit for carrying out an intelligent algorithm subsequently.
Those skilled in the art will appreciate that all or part of the flow of the methods of the embodiments described above may be accomplished by way of a computer program to instruct associated hardware, where the program may be stored on a computer readable storage medium. Wherein the computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory, etc.
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention.
Claims (10)
1. A matrix operation device based on a flexible RRAM storage array is characterized by comprising the flexible RRAM storage array, a multiplexer mux, an analog-to-digital converter ADC, a popcount module, a multiplier and a subtracter;
The flexible RRAM storage and calculation array outputs the accumulated current of each column storage and calculation unit to a multiplexer MUX according to a plurality of rows of input and output;
The multiplexer MUX selects one column from the column storage units and sends the accumulated current of the column storage units to the analog-to-digital converter ADC;
The analog-to-digital converter ADC is used for converting the accumulated current output by the RRAM storage array into a digital signal and transmitting the digital signal to the subtracter;
The popcount module receives the multi-line input, acquires the number of 1 in the multi-line input, and outputs the number of 1 to the multiplier;
The multiplier multiplies the number of 1 by a fixed value beta and sends the product result to the subtracter;
The subtracter subtracts the product result from the digital signal to obtain the multiplication and addition result of the matrix.
2. The matrix computing device of claim 1, wherein the flexible RRAM memory array comprises n x m memory cells;
The word lines WL of each row of memory calculation units are sequentially connected, the source lines SL of each column of memory calculation units are sequentially connected, the bit lines BL of each column of memory calculation units are sequentially connected, and the bit lines BL are used for outputting the calculation results of the column of memory calculation units;
Each memory cell is of a 1T1R structure and comprises a transistor and a memristor.
3. The matrix operation device based on a flexible RRAM memory array of claim 2, wherein the transistor is an IGZO TFT, and the memristor is a RRAM;
And the grid electrode of the indium gallium zinc oxide thin film transistor IGZO TFT is connected with the word line WL of the memory cell, the drain electrode of the indium gallium zinc oxide thin film transistor IGZO TFT is connected with the bit line BL of the memory cell, the source electrode of the indium gallium zinc oxide thin film transistor IGZO TFT is connected with one end of the memristor RRAM, and the other end of the memristor RRAM is connected with the source line SL of the memory cell.
4. The matrix computing device of claim 3, wherein the operation modes of the flexible RRAM memory array include a write weight mode and an inference operation mode.
5. The matrix operation device based on the flexible RRAM memory array of claim 4, wherein in the write-weight operation mode, the resistance state of the memristor RRAM is changed by controlling the connection voltages of the word line WL, the bit line BL and the source line SL, so as to implement the weight writing.
6. The matrix operation device based on a flexible RRAM memory array according to claim 5, wherein when the word line WL is connected to a high level, the bit line BL is connected to a write voltage Vw, and the source line SL is grounded, the conductance state of the memristor RRAM is a low-resistance state LRS, and the weight is assigned to be β+1;
When the word line WL is connected with a high level, the bit line BL is grounded, and the source line SL is connected with the write voltage Vw, the conductivity state of the memristor RRAM is a high-resistance state HRS, and the weight is assigned to be beta-1;
When the word line WL is connected to low level, it indicates that the memristor RRAM is not selected, and the resistance state of the memristor RRAM remains unchanged.
7. The matrix operation device based on the flexible RRAM memory array of claim 6, wherein the write weight mode employs a half-voltage method, the write voltage Vw is greater than a threshold voltage of the memristor RRAM, and the half write voltage Vw is less than the threshold voltage of the memristor RRAM to ensure that the unselected memristor RRAM states remain unchanged.
8. The matrix operation device based on the flexible RRAM memory array of claim 7, wherein in the reasoning operation mode, the bit line BL is connected to the read voltage Vr, the source line SL is grounded, the input of the memory cell is determined according to whether the bit line WL is connected to the high level or the low level, the current value output by the memory cell is used as the product of the memory cell input and the memristor RRAM weight, and the currents output by the memory cells in each column of memory cells are converged in the bit line corresponding to the column of memory cells, so that the bit line output is the sum of the cell products of the column of memory cells.
9. The matrix operation device based on a flexible RRAM memory array of claim 8, wherein when the word line WL is connected to a high level and the resistance state of the memristor RRAM is a high resistance state HRS, the input of the memory cell is 1, the output of the memory cell is low current I L, and the value of the low current I L is β -1;
When the word line WL is connected with a high level and the resistance state of the memristor RRAM is a low resistance state LRS, the input of the memory cell is 1, the high current I H is output, and the value of the high current I H is beta+1;
When the word line WL is connected to the low level, the IGZO TFT is turned off, the memory cell is not connected, and the input of the memory cell is 0, and the output current of the memory cell is 0.
10. The matrix computing device based on the flexible RRAM storage array of claim 9, characterized in that said beta >1.
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