CN1679116B - Memory device and system based on processor - Google Patents
Memory device and system based on processor Download PDFInfo
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- CN1679116B CN1679116B CN038052393A CN03805239A CN1679116B CN 1679116 B CN1679116 B CN 1679116B CN 038052393 A CN038052393 A CN 038052393A CN 03805239 A CN03805239 A CN 03805239A CN 1679116 B CN1679116 B CN 1679116B
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0061—Timing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2281—Timing of a read operation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
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Abstract
The present invention relates to a method and apparatus for reading a programmable conductor random access memory (PCRAM) cell without refreshing the cell. A programmable conductor memory cell is read by a sense amplifier but without rewriting the contents of the memory cell. If a programmable contact memory cell has an access transistor, the access transistor is switched off to decouple the cell from a bit line after a predetermined amount of time. The predetermined amount of time is sufficiently long enough to permit the logical state of the cell to be transferred to the bit line and also sufficiently short to isolate the cell from the bit line before the sense amplifier operates. For programmable contact memory cells which do not utilize an access transistor, an isolation transistor may be placed in the bit line located between and serially connection of the portion of the bit line from the sense amplifier to the isolation transistor and the portion of the bit line from the isolation transistor to the memory cell. The isolation transistor, normally conducting, is switched off after the predetermined time past the time the bit line begins to discharge through the programmable contact memory cell, thereby isolating the programmable contact memory cell from the sense amplifier before a sensing operation begins.
Description
Invention field
The present invention relates to integrated memory circuit.Relate in particular to a kind of method that is used to read programmable conductor random access memory (PCRAM) unit.
Background of invention
Dynamic RAM (DRAM) integrated circuit (IC) array existed for three more than ten years and along with the progress of semiconductor fabrication and circuit design technique memory capacity has significantly been increased.The huge progress of these two kinds of technology has also realized high-caliber integrated, makes the remarkable reduction of memory array size and cost and the increase of turnout.
Fig. 1 is the synoptic diagram of a DRAM storage unit 100, comprises access transistor 101 and capacitor 102.Be coupled to the bit of the capacitor 102 of Vcc/2 potential source and transistor 101 with the form storage data of electric charge.Usually, the electric charge of the polarity electric charge of potential difference (PD) on the capacitor 102 of+Vcc/2 (for example corresponding to) is stored in the capacitor 102 so that represent a scale-of-two " 1 ", the electric charge of the opposite polarity electric charge of potential difference (PD) on the capacitor 102 of-Vcc/2 (for example corresponding to) is then represented a scale-of-two " 0 ", whether the gate coupled of transistor 101 is coupled to bit line 104 through these transistor 101 conductings to word line 103 thereby make this word line 103 control this electric capacity 102.The default setting of each word line 103 is earth potentials, and this earth potential makes transistor 101 be disconnected, therefore with capacitor 102 electrical isolations.
One of defective relevant with DRAM unit 100 is that the electric charge on this capacitor 102 may reduce naturally along with the time, even this capacitor 102 keeps electrical isolations.Therefore, DRAM unit 100 need refresh periodically.As described below in addition, after storage unit 100 has inserted,, also need to refresh for example as the part of read operation.
Fig. 2 illustrates the memory storage 200 that comprises a plurality of memory array 150a, 150b.(the element of representing same-type in the accompanying drawings usually with same numbers.For example, the sensor amplifier 300 of the sensor amplifier 300a among Fig. 2 and 300b and Fig. 3 has identical circuit.The letter suffix of small letter is generally used for distinguishing the different units of same type.But, upper case prefixes, for example " N " can represent to change relevant different circuit with the negative or positive type with " P ".) each of memory array 150a, 150b comprises that all a plurality of storage unit 100a-100d, 100e-100h are arranged in together by a plurality of storage unit 100 of lay, makes storage unit 100 not share a shared word line 103a-103d along given arbitrarily bit line 104a, 104a ', 104b, 104b '.On the contrary, storage unit 100 is not shared common 104a, a 104a ', 104b, 104b ' along random word line 103.Each memory array all has its oneself set of bit lines.For example, memory array 150a comprises bit line 104a, 104b, and memory array 150b comprises bit line 104a ', 104b '.The bit line of each phase adjacency pair of memory array 150a, 150b is coupled to shared sensor amplifier 300a, a 300b.For example, bit line 104a, 104a ' are coupled to sensor amplifier 300a, and bit line 104b 104b ' is coupled to sensor amplifier 300b.As following the explanation, sensor amplifier 300a, 300b are used to this sensing of conducting when storage unit 100a-100h is read out/refresh part.
Read a DRAM storage unit and comprise access and sensing/renewal operation.
The purpose of accessing operation is to be sent to the bit line 104 relevant with storage unit 100 being stored in electric charge on the capacitor 102.Begin bit line 104a, 104a ', 104b, 104b ' each is pre-charged to a predetermined current potential (for example Vcc/2) by each of bit line 104a, 104b being coupled to a potential source (not illustrating) accessing operation.Each of bit line 104a, 104b is all by electricity disconnection subsequently.Because the effect of the natural capacity of bit line 104a, 104a ', 104b, 104b ', bit line 104a, 104a ', 104b, 104b ' will float over this predetermined current potential.Subsequently, bring up to by the current potential of the handle word line (for example 103a) relevant and make transistor 101a, 101e start this word line 103a to the level that this word line 103a is coupled to grid with the storage unit that just is being read out (for example 100a).Be noted that because intrinsic stray capacitance between bit line 104 and word line 103 starting of word line 103 will make the current potential at each relevant bit line 104 that increase is arranged slightly.But in common DRAM system, compare with the amplitude that changes at the current potential of sharing owing to electric charge on the bit line that causes, the amplitude of this potential change is insignificant.Therefore, only with respect to the DRAM system, the further discussion of this stray capacitance effect will be omitted.
The feasible relative bit line 104a of each capacitor 102a, 102e, the 104b that is coupled to each storage unit 100a, the 100e of this word line 103a of the starting of word line 103a shares its electric charge.Bit line 104a ', 104b ' in another array 150b remain on precharge current potential.This electric charge is shared and is made the current potential of bit line 104a, 104b increase and decrease according to the electric charge that is stored among capacitor 102a, the 102e.Because only bit line 104a, the 104b of a memory array have changed its current potential, so between another bit line 104a ', the 104b ' that start word line 103a relevant bit line 104a, 104b with this and be correlated with, generate a difference current potential with same sensor amplifier 300a, 300b at each sensor amplifier 300a, 300b.Therefore, this accessing operation makes the bit line 104a relevant with the unit 100a that just is being read out, the current potential that 104b has be greater than or less than this precharge voltage.But this variation in current potential is little, and needs to amplify before it can be used.
This sense/refresh operation is used for two purposes.At first, the little variation of this sense/refresh operation in current potential is amplified to the bit line current potential that is coupled to this accessed unit.If this bit line has than the low current potential of this precharge current potential, then this bit line will be driven to earth potential in the sensing process.In addition, if this bit line has the current potential higher than this precharge current potential, then this bit line will be driven to Vcc in the sensing process.Second purpose of this sense/refresh operation is returned to the state that was had before this accessing operation by the state of charge in the capacitor of access unit.Because this accessing operation is by sharing this capacitor with this bit line, so watered down the electric charge that is stored on this capacitor.
Fig. 3 is a detailed maps of sensor amplifier 300, comprises a N-sensor amplifier 310N and a P-sensor amplifier part 310P.This N-sensor amplifier 310N and P-sensor amplifier 310P comprise node NLAT respectively
*And ACT.These nodes are coupled to controllable potential source (not illustrating).Node NLAT
*Be biased to the precharge potential (for example Vcc/2) of bit line 104 at first, and node ACT is biased to earth potential at first.In this original state, the transistor 301-304 of N and P-sensor amplifier 310N, 310P is cut off.This sense/refresh operation is a kind of two sections operations, and wherein this N-sensor amplifier 310N was triggered before this P-sensor amplifier 310P.
By node NLAT
*Current potential trigger N-sensor amplifier 310N from precharge potential (for example Vcc/2) band to earth potential.Along with node NLAT
*And the potential difference (PD) between bit line 104a, 104a ', 104b, the 104b ' is near the threshold potential of nmos pass transistor 301,302, and gate coupled begins conducting to the transistor of high voltage bit line.This will make the bit line of low-voltage towards NLAT
*The voltage discharge of node.Therefore, as node NLAT
*When reaching earth potential, the bit line of low-voltage also will reach earth potential.Because its gate coupled is to the digit line of the low-voltage of ground discharge, so the never conducting of another nmos pass transistor.
By the current potential of node ACT is taken to Vcc from earth potential, trigger this P-sensor amplifier 310P (after this N-sensor amplifier 310N has triggered).Along with the current potential of the bit line of low-voltage current potential (triggering formerly by this N-sensor amplifier 310N causes) closely, its gate coupled will begin conducting to the PMOS transistor of the bit line of this electronegative potential.This will make the bit line of this initial noble potential be charged to the current potential of Vcc.After this N and P-sensor amplifier 310N, 310P had triggered, this high voltage bit line was elevated to Vcc with its current potential, and the bit line of this electronegative potential is reduced to earth potential with its current potential simultaneously.Therefore, the process of triggering sensor amplifier 310N, 310P is amplified to a level that is suitable for using in digital circuit to the potential difference (PD) that is produced by this accessing operation.Specifically, if charging charge corresponding to a Binary Zero of this storage unit 100a storage, then relevant with the storage unit 100a that just is being read out bit line 104a is driven into earth potential by the precharge potential from Vcc/2; If or charging charge of this storage unit 100a storage corresponding to a binary one, then relevant with the storage unit 100a that just is being read out bit line 104a is driven into the Vcc current potential by the precharge potential from Vcc/2, thereby makes comparer (or differential amplifier) 350a that is coupled to bit line 104a, 104a ' export a Binary Zero or 1 according to the data of storing among the unit 100a on signal wire 351.In addition, the electric charge of original stored on the capacitor 102a of access unit is restored to its access status in advance.
Other form of the memory element in storage unit is used in the identification that keeps punching.Nearest research has concentrated on and can be programmed the resistive material that represents higher or lower stable ohmic state.A kind of programmable resistive element of such material can be by program (setting) to a high resistive state, and storage is a scale-of-two " 1 " data bit for example, or is programmed into a low-resistance sexual state, stores a scale-of-two " 0 " data bit.Can extract this data bit stored by the amplitude of a read current of this resistive memory element of process of an access device switching by detection, thus this stable resistance states of indicating it before to be programmed into.
Utilize solid electrolyte recently, for example the chalcogenide glass of metal-doped chalcogenide manufacturing has been studied as using at memory storage, for example the storage unit of the data-carrier store in the DRAM memory storage.United States Patent (USP) 5761115,5896312,5914893 and 6084796 has all been described this technology, and is hereby incorporated by reference.This storage unit is referred to as programmable conductor element (also being referred to as programmable metallization unit in addition).The characteristic of a unit like this is, generally includes the solid metal electrolyte, for example metal-doped chalcogenide and at the negative electrode and the anode of the lip-deep apart of this fast ionic conductor.The voltage application at the two ends of this negative electrode and anode makes Metal tree dendrite of its growth, and it changes the resistance and the electric capacity of this unit, can therefore be used to store data.
A kind of specific compromise able to programme bistable resistive material is an alloy system that comprises Ge:Se:Ag.A memory element that comprises a chalcogenide material has a natural stable state high resistive state, but can be used to a current impulse from the voltage of suitable polarity through this unit and be programmed into a low resistance state.This makes a programmable conductor, is referred to as also that a skeleton is grown and the resistance that reduces this unit between anode and negative electrode.Utilize suitable current impulse and polarity of voltage to rewrite a chalkogenide memory element (write the anti-phase of this unit and will arrive a low resistance state) simply, come this chalkogenide memory element of reprogramming, and therefore do not need to be wiped free of.And the memory element of chalcogenide material is intimate non-volatile, and for the low resistance state after keeping it to programme, it only needs seldom (for example weekly) to be connected to power supply or is refreshed.Such storage unit is different from the DRAM unit, and will not need to refresh just can be by access.
Though those for example relevant with the DRAM unit traditional sensor amplifier circuit can be read programmable conductor random access memory (PCRAM) unit, under a PCRAM background, do not need the natural refresh operation relevant with these sensor amplifiers.In fact do not wish that the PCRAM unit frequently rewrites, produce opposing to rewriteeing because frequent rewriting will make the PCRAM unit become.Therefore, need and thirst for a kind of circuit and method is read the PCRAM unit and do not refreshed them.
Brief summary of the invention
The present invention relates to a kind of method and apparatus, be used to read a PCRAM storage unit and do not refresh this storage unit.Programmable conductor in this PCRAM unit has been coupled to a later preset time of its bit line, and this programmable conductor is separated from this bit line electricity.This preset time is selected at this N and the P-sensor amplifier has started a time point before.In this way, this N and P-sensor amplifier can change the current potential on this bit line and not cause that the current potential of this change rewrites this PCRAM unit.Have in the PCRAM array of access transistor of the grid that is coupled to word line in use, can prohibit moving this word line by the preset time after this word line has started and put into practice the present invention.In not comprising the PCRAM array of access transistor, can on each bit line between this PCRAM unit and this sensor amplifier, add isolated transistor, this PCRAM unit from its relevant bitline separation.
One aspect of the present invention relates to a kind of memory device, comprising:
Be used for from the device of programmable conductor random access memory unit read data, described device comprises:
Place in circuit is used for during the read operation described programmable conductor random access memory unit being coupling between the bit line of addressing and the word line that starts and addressing and startup;
Be coupled to the sensor amplifier of the bit line of described addressing and startup, be used to read the logic state of described programmable conductor random access memory unit; And
Prevent circuit, be used to prevent the described read operation of described programmable conductor random access memory cell response and be refreshed, the described circuit that prevents comprises transistor, described transistor be connected the word line of described addressing and startup and be used for the driver of word line of described addressing and startup or ground between or be connected between the bit line and described sensor amplifier of described addressing and startup
The wherein said circuit that prevents makes that the word line of described addressing and startup is prohibited after the logic state of described programmable conductor random access memory unit is transferred to the bit line of described addressing and startup and read the logic state of described programmable conductor random access memory unit at described sensor amplifier before.
Another aspect of the present invention relates to a kind of system based on processor, comprising:
Processor; With
Storer, described storer also comprises:
Be used for from the device of programmable conductor random access memory unit read data, described device comprises:
Place in circuit is used for during the read operation described programmable conductor random access memory unit being coupling between the bit line of addressing and the word line that starts and addressing and startup;
Be coupled to the sensor amplifier of the bit line of described addressing and startup, be used to read the logic state of described programmable conductor random access memory unit; And
Prevent circuit, be used to prevent the described read operation of described programmable conductor random access memory cell response and be refreshed, the described circuit that prevents comprises transistor, described transistor be connected the word line of described addressing and startup and be used for the driver of word line of described addressing and startup or ground between or be connected between the bit line and described sensor amplifier of described addressing and startup
The wherein said circuit that prevents makes that the word line of described addressing and startup is prohibited after the logic state of described programmable conductor random access memory unit is transferred to the bit line of described addressing and startup and read the logic state of described programmable conductor random access memory unit at described sensor amplifier before.
Another aspect of the present invention relates to a kind of being used for from the method for programmable conductor random access memory unit read data, and described method comprises step:
The bit line and the reference bit lines of addressing are pre-charged to predetermined pre-charge voltage;
Start the word line of the addressing comprise described programmable conductor random access memory unit and the logical value in the described programmable conductor random access memory unit is transferred to the bit line of the addressing that is associated;
After the described logical value of described programmable conductor random access memory unit is transferred to the bit line of described addressing, prohibit the word line of moving described addressing;
The logical value of being read the bit line that is transferred to described addressing after prohibiting at the word line of described addressing; And
Be refreshed because of described read operation to prevent described programmable conductor random access memory unit by starting transistor read the logical value of described programmable conductor random access memory unit at sensor amplifier before, described transistor be connected the word line of described addressing and be used for the driver of word line of described addressing or ground between or be connected between the bit line and described sensor amplifier of described addressing.
Another aspect of the present invention relates to a kind of being used for from the method for programmable conductor random access memory unit read data, and described method comprises step:
Start the word line of the addressing be connected to described programmable conductor random access memory unit and the logical value in the described programmable conductor random access memory unit is transferred to the bit line of the addressing that is associated;
Disconnection is positioned on the bit line of the addressing that is associated and isolated transistor that be connected in series sensor amplifier and described programmable conductor random access memory unit, and wherein said disconnection is to measure first schedule time after the described startup of the word line of addressing to carry out; And
After described disconnection, read the logical value of the described programmable conductor random access memory unit that is transferred to described bit line at the sensor amplifier place.
Another aspect of the present invention relates to a kind of being used for from the method for programmable conductor random access memory unit read data, and described method comprises step:
First bit line that is coupled to the programmable conductor random access memory unit is carried out precharge, and described programmable conductor random access memory unit comprises array of programmable conductor memory elements;
Precharge second bit line;
Be increased in the voltage on described first bit line;
Connect the access transistor of described programmable conductor random access memory unit so that array of programmable conductor memory elements is coupled to described first bit line;
The word line of prohibiting moving addressing is to disconnect the access transistor of described programmable conductor random access memory unit, so that array of programmable conductor memory elements and described first bitline separation; And
Read the voltage on described first bit line and described second bit line at the sensor amplifier place, so that determine the logic state of described array of programmable conductor memory elements;
Wherein said taboo is moving be carry out at the preset time before described the reading and described second bit line before being changed, keep pre-charge voltage by read operation.
Another aspect of the present invention relates to a kind of being used for from the method for programmable conductor random access memory unit read data, and described method comprises step:
Connect isolated transistor, so that first bit line is coupled to sensor amplifier, described first bit line also is coupled to the array of programmable conductor memory elements of programmable conductor random access memory unit;
Described first bit line of precharge;
Precharge second bit line;
Increase the voltage on described first bit line;
Disconnect described isolated transistor, so that described array of programmable conductor memory elements is separated with described sensor amplifier;
Read the voltage on described first bit line and described second bit line, so that determine the logic state of described array of programmable conductor memory elements;
Wherein said disconnection is to carry out in first schedule time amount before described the reading and after the startup of the word line that is addressing.
Accompanying drawing is described
From the detailed description of the illustrated embodiments of the invention that provide below with reference to accompanying drawing with obvious above-mentioned and other advantage and feature of the present invention, wherein:
Fig. 1 is the synoptic diagram of a traditional DRAM unit;
Fig. 2 is the synoptic diagram of a traditional DRAM array;
Fig. 3 is the synoptic diagram of a traditional sensor amplifier;
Fig. 4 is the synoptic diagram of a PCRAM unit;
Fig. 5 is the synoptic diagram of a PCRAM array;
Fig. 6 A and 6B are sequential charts, and the voltage on this word and bit line when a PCRAM unit is read with high resistant and low resistive state respectively is described.
Fig. 7 is a process flow diagram of explanation the inventive method;
Fig. 8 is based on the system chart of a processor, comprises PCRAM in accordance with the principles of the present invention;
Fig. 9 is the synoptic diagram of the PCRAM array of second most preferred embodiment according to the present invention; With
Figure 10 is the synoptic diagram for the optional embodiment of a PCRAM unit of the PCRAM array utilization of Fig. 9.
The detailed description of most preferred embodiment of the present invention
Referring now to accompanying drawing,, wherein identical label is represented identical parts, and Fig. 4 illustrates a PCRAM unit 400, and Fig. 5 illustrates a memory storage 500 of being made up of a plurality of PCRAM unit 400a-400h.Shown in Fig. 4, PCRAM unit 400 comprises an access transistor 401, a programmable conductor memory element 402 and a unit plate 403.The gate coupled of this access transistor 401 is to word line 405 and a terminal is coupled to a bit line 406.An array fraction of this unit is shown in Figure 5, comprises bit line 406a, 406a ', 406b, 406b ' and word line 405a, 405b, 405c and 405d.As shown in Figure 5, bit line 406a, 406b are coupled to pre-charge circuit 501a, 105b separately, switchably a precharge potential are added to bit line 406a, 406a ', 406b, 406b '.The other end of this access transistor 401 is coupled to an end of array of programmable conductor memory elements 402, and another end of this array of programmable conductor memory elements 402 is coupled to a unit plate 403 simultaneously.This unit plate 403 can across topped be coupled to several other PCRAM unit.This unit plate 403 also is coupled to a potential source.Among the embodiment of example, this potential source is 1.25V (Vdd/2).
Fig. 5 illustrates the memory storage 500 that comprises a plurality of memory array 550a, 550b.Each memory array 550a, 550b comprise by a plurality of storage unit 400 of lay a plurality of storage unit 400a-400d, 400e-400h together, make along the not shared common word line 405a-405d of storage unit 400 that gives position line 406a, 406a ', 406b, 406b ' arbitrarily.On the contrary, this storage unit 400 is not shared shared bit line 406a, a 406a ', 406b, 406b ' along random word line 405a-405d.Each word line can switch to a word line driver 512a-512d via a transistor 510a-510d.In addition, each word line can also switchably be coupled to ground via transistor 520a-520d.The gate coupled of transistor 510a-510d, 520a-520d is used for selectively word line 405a-405d being coupled to this word line driver 512a-512b/ ground to signal wire 511a-511d, and from this word line driver 512a-512b/ be separated.Each memory array 550a, 550b have its oneself bit line setting.For example, memory array 550a comprises bit line 406a, 406b, and memory array 550b comprises bit line 406a ', 406b '.The bit line of each phase adjacency pair of memory array 550a, 550b is coupled to shared sensor amplifier 600a, a 600b.For example, bit line 406a, 406a ' are coupled to sensor amplifier 600a, and bit line 406b, 406b ' are coupled to sensor amplifier 600b.For simplicity, Fig. 5 illustrates a memory storage that only has two array 550a, 550b and eight unit 400a-400h.But, should be appreciated that real world memory devices will have a lot of unit and array.For example, a real memory storage can comprise millions of unit 400.
In this PCRAM device 500, read a PCRAM unit, for example unit 400a comprises and inserting and sensing operation.
The purpose of access operation is a little potential difference (PD) that is created between the bit line (for example 406a, 406a ') of the same sensor amplifier (for example 300a) that is coupled to this storage unit 400a that is read out.This little potential difference (PD) can be amplified to a required threshold value of comparer that is coupled to this bit line with rear drive by a sensor amplifier 300 subsequently, so that output terminal is corresponding to a value of this storage unit 400a content.Referring now to Fig. 7,, access operation is from bit line 406a, the 406a ' of the memory storage 500 of process pre-charge circuit 501a-501b, the precharge (step S1) of 406b, 406b '.Can cause this this bit line of precharging signal low value precharge by transient state, make transistor 502a-502d be conducting to bit line 406a, 406a ', 406b, 406b ' to this pre-charge voltage (Vdd).In case this precharging signal turns back to a high state of value, transistor 502a-502d stop conducting, but because the intrinsic electric capacity of this bit line, bit line 406a, 406a ', 406b, 406b ' will remain on predetermined period of this precharge potential.
In the embodiment of example, bit line 406a, 406a ', 406b, 406b ' are precharged to 2.5V, and unit plate 403a, 403b are constrained to 1.25V.The potential difference (PD) of this 1.25V between bit line and the unit plate will make this bit line discharge through this access transistor 401 (when it is during a conducting state) and 402 pairs of these unit plates of this array of programmable conductor memory elements.This discharge rate depends on the resistive state of this array of programmable conductor memory elements 402.Promptly a low-resistance sexual state will make the discharge of this bit line faster than a high resistive state.Along with bit line discharges, its voltage will descend to this cell board pole tension from this pre-charge voltage.
In memory storage 500, word line 405a-405d is earth potential normally.Access transistor 401a-401e is that normality disconnects.Referring now to Fig. 6 A and 6B,, in time T 1, the current potential by the handle word line 405a relevant with the unit 400a that will read takes predetermined level to and starts this word line 405a (step S2) from ground.Design this predetermined level to be created in the read-out voltage of this programmable contact 402a, as previously explained, this read-out voltage has less than the amplitude that writes voltage.In the embodiment of this example, word line 401a is moved to 2.25V.Because the threshold voltage of transistor 401a is 0.8V, so the current potential of the interface between transistor 401a and programmable contact 402a is 1.45V.Because the interface voltage between programmable contact 402a and this unit plate 403a is maintained at 1.25V, so this will produce the read-out voltage of 0.2V.
Because the intrinsic stray capacitance between word line 401a and its relevant bit line 406a, the current potential relevant with bit line 406a will increase along with the startup of word line 401a.In the embodiment of this example, the current potential among the bit line 406a has increased 0.1V and has arrived 2.6V.Be noted that the word line 405c, the 405d that are coupled to paratope line 406a ', 406b ' are maintained at earth potential.Therefore bit line 406a ', 406b ' are maintained at precharge potential, are 2.5V in the embodiment of this example.
The current potential of this increase of bit line 406a uses with the resistive combinations of states of two bistable states of this programmable contact 402a, makes a bit line (for example 406a) that is coupled to sensor amplifier (for example 300a) have than the greater or lesser voltage of another bit line that is coupled to same sensor amplifier 300a (for example 406a ').In fact, this stray capacitance between word line and correlative position line is used to realize an original state, and wherein relevant with the unit 400a that just is being read out bit line (for example 406a) is than the higher current potential of another bit line 406a ' that is coupled to same sensor amplifier 300a.If the design of this storer and operation make that this programmable contact 402a has a high resistive state, then bit line 406a slowly discharges, and causes the relative noble potential that it keeps it thus.But if this programmable contact 402a has a low resistive state, then bit line 406a makes bit line 406 be converted to the potential state lower than bit line 406a ' with a very fast speed discharge.Can see this two effects by comparison diagram 6A (effect in a programmable contact of high resistive state is described) and Fig. 6 B (effect in a programmable contact of low-resistance sexual state is described).
T2 (step S3) after the preset time t of T1, the current potential by the handle word line 405a relevant with unit 400a turns back to read (the step S4) that earth potential is prohibited this word line 405a.Can be by for example terminal 511a ground connection being realized that the taboo of word line is moving, this will make transistor 510a that word line driver 512a is coupled in series to word line 405a, so that stop its conducting.Thereby this will cut off access transistor 401a, 401 and prevent the further discharge of this bit line by programmable contact 402a, 402e.This potential difference (PD) that has also prevented the amplification that generates in this read operation process subsequently refreshes (writing) this programmable contact 402a, 402e.In situation seldom, may wish to refresh the content of this programmable contact 402a, 402e, this word line can be kept high level for a long time.By the dashed trace among Fig. 6 A and the 6B this operator scheme is shown.In the embodiment of this example, this preset time t is approximately 15 nanoseconds (being T2=T1+15ns)
Be noted that under the condition that does not deviate from spirit of the present invention, the value of t and T2 can change.Specifically, target of the present invention will reach and realize whenever this programmable contact is separated from this bit line electricity before writing the required threshold value of this programmable contact by be amplified to the potential difference (PD) that causes crossing over this programmable contact by sensor amplifier 310N, 310P at this bit-line voltage.So, though Fig. 6 A and 6B illustrate before any one startup that T2 appears at sensor amplifier 310N, 310P, but according to the electrical characteristics of memory storage 500, T2 can appear between the startup of for example this N-sensor amplifier 310N and P-sensor amplifier 310P.In any case the necessary enough length of preset time t is so that make the logic state of this programmable conductor 402a be reflected on this bit line 406a; That is, this bit line 406a voltage will change from this pre-charge voltage fully by the discharge of this programmable conductor 402a, makes two resistive states of this programmable conductor 402a and to amplify by this sensor amplifier 300a difference.
In period of time T 3, start N-sensor amplifier 310N (beginning of step S5).As point out with reference to the DRAM system front, start this N-sensor amplifier and make the bit line (for example 406a ') that has than electronegative potential be pulled to ground with this NLAT signal.In the embodiment of this example, T3 is approximately 30 nanoseconds after the T1.But be noted that under the condition that does not deviate from spirit of the present invention, the value of T3 can change.
In period of time T 4, start sensor amplifier 310P.As point out with reference to the DRAM system front, start this P-sensor amplifier and make bit line (for example 406a) be pulled to Vcc with high potential.In the embodiment of example, T4 is approximately 35 nanoseconds (end of step S5) after the T1.But be noted that under the condition that does not deviate from spirit of the present invention, the value of T4 can change.
In time T 5, the sensor amplifier 300a relevant with the unit 400a that just is being read out will make one of its bit line (for example 406a) at the Vcc current potential and another bit line (for example 406a ') at earth potential.Because a bit line that is coupled to sensor amplifier 300a is earth potential and another bit line is the Vcc current potential now, so comparer (or differential amplifier) 350 can be used for exporting a value corresponding to the content of the unit 400a on signal wire 351a.
Fig. 9 illustrates memory storage 900 according to other embodiments of the present invention.This optional embodiment designs for the PCRAM unit that does not comprise access transistor 401 and uses.For example, Figure 10 illustrates the example of a PCRAM unit 400 ', and it has used pair of diodes 1001a, 1001b to substitute an access transistor.As shown, this PCRAM unit 400 ' is characterised in that the array of programmable conductor memory elements 402 that is coupled to a bit line 104.This array of programmable conductor memory elements 402 also is coupled to word line via diode circuit 1002.Two diode 1001a, 1001b of the placement arranged side by side as shown in the figure of diode electrically route form.
Memory storage 900 is similar to the memory storage 500 of first embodiment very much.But memory storage 900 comprises new isolated transistor 901a-901d, and sensor amplifier 300a, 300d are connected in series to bit line 406a, 406a ', 406b, 406b '.Mode of operation in the memory storage 900 of the present invention is similar to memory storage 500 very much, but whether prohibiting moving word line 405a before detecting comes storage unit 400a is separated from the amplification voltage electricity on the bit line 406a, but the isolated transistor 901a of conducting is usually disconnected, thereby this bit line of shunt 406a.Bit line portion between sensing this transistor 901a and this sensor amplifier 300a is isolated bit line portion between transistor 901a and the pre-charge circuit 501a and sensor amplifier simultaneously then.
Fig. 8 is based on the system 800 of a processor, and for example the block diagram of a computer system comprises a PCRAM semiconductor memory 802 that combines description with another figure.Storer 802 can constitute as being installed in a memory module, for example resembles the pseudostatic ram module of SIMM, DIMM or one or more memory chip or the memory integrated circuit on other pseudostatic ram module.Should comprise processor 801, storer 802, mass storage 803 and I/O device 804 based on the system 800 of processor, each all is coupled to bus 805.Though what illustrate is single processor 801, should be appreciated that the processor that this processor 801 can be an any type, and can comprise multi-processor and/or several processor and coprocessor.Storer 802 shown in Fig. 9 has a plurality of PCRAM sign indicating number sections 500.But storer 802 can include only single PCRAM device 500, or the bigger a plurality of PCRAM devices 500 of situation shown in the ratio, and/or can comprise other form of memory, for example nonvolatile memory or cache memory.Though what illustrate is a mass storage 803, should can comprise a plurality of mass storage devices, possible dissimilar for example floppy disk, CDROM, CD-R, CD-RW, DVD, hard disk and the disk arrays of not comprising based on the system 800 of processor with limiting to.I/O device 804 can similarly comprise a plurality of dissimilar I/O devices, does not comprise keyboard, mouse, graphics card, monitor and network interface with limiting to.Though bus 805 illustrates with unified bus, can comprise a plurality of buses and/or bridge, they can be coupled to each other or by other parts bridge joint.Some of device 801-804 may only be coupled to bus 805, and other can be coupled to a plurality of buses 805.
The invention provides a kind of PCRAM unit 400 and use sensor amplifier to read the content of this unit 400 but do not rewrite the method for this location contents.By the amount of the schedule time after this programmable conductor 402 has been electrically coupled to this bit line 406 programmable conductor 402 of this unit 400 and bit line 406 isolation are realized preventing rewriteeing.This predetermined amount of time is corresponding to the time before the start-up time of N and P-sensor amplifier 310N, 310P.In the embodiment of example, 400 1 access transistors 401 in this PCRAM unit are used for electric coupling and the uncoupling of this unit to bit line.This access transistor 401 has a grid that is coupled to a word line.So in the embodiment of example, this word line is prohibited moving predetermined amount of time after it starts, thereby the startup that guarantees this N and P-sensor amplifier 310N, 310P does not rewrite this unit 400.In another embodiment, this PCRAM unit 400 does not comprise access transistor.For example this PCRAM unit changes the use diode into.Among the embodiment that why not uses access transistor in office, isolated transistor can be inserted between this programmable contact storage unit and the bit line relevant with this programmable contact storage unit.The isolated transistor of this common conducting can be disconnected by the preset time identical with most preferred embodiment after this word line has started, thereby realizes the equifinality of this programmable contact storage unit with the voltage isolation of the rising that produces in readout.
Though describe the present invention in detail, should be appreciated that the present invention is not limited to above-mentioned disclosed embodiment in conjunction with most preferred embodiment.On the contrary, but the present invention can be in conjunction with the number of variations that does not have described and the spirit and scope of the present invention to match so far, change, substitute or the equivalence design is gone up and improved.Therefore, the present invention will can't help above-mentioned explanation or accompanying drawing and limit, but only be limited by the scope of appending claims.
Claims (34)
1. memory device comprises:
Be used for from the device of programmable conductor random access memory unit read data, described device comprises:
Place in circuit is used for during the read operation described programmable conductor random access memory unit being coupling between the bit line of addressing and the word line that starts and addressing and startup;
Be coupled to the sensor amplifier of the bit line of described addressing and startup, be used to read the logic state of described programmable conductor random access memory unit; And
Prevent circuit, be used to prevent the described read operation of described programmable conductor random access memory cell response and be refreshed, the described circuit that prevents comprises transistor, described transistor be connected the word line of described addressing and startup and be used for the driver of word line of described addressing and startup or ground between or be connected between the bit line and described sensor amplifier of described addressing and startup
The wherein said circuit that prevents makes that the word line of described addressing and startup is prohibited after the logic state of described programmable conductor random access memory unit is transferred to the bit line of described addressing and startup and read the logic state of described programmable conductor random access memory unit at described sensor amplifier before.
2. memory device as claimed in claim 1, wherein said transistor are prohibited the word line of described addressing and startup.
3. memory device as claimed in claim 2, wherein said transistor is connected in series in the word line of described addressing and startup and is used between the driver of word line of described addressing and startup, and is switched on and is disconnected during described read operation so that prohibit the word line of moving described addressing and startup.
4. memory device as claimed in claim 2, wherein said transistor are connected between the word line and ground of described addressing and startup, and are disconnected and are switched on during described read operation so that prohibit the word line of moving described addressing and startup.
5. memory device as claimed in claim 1, wherein said transistor is connected in series between the bit line and described sensor amplifier of described addressing and startup, and the described transistor that is connected in series is being switched on during the read operation and had been disconnected before described programmable conductor random access memory unit can be refreshed.
6. memory device as claimed in claim 1, the wherein said circuit that prevents makes the word line of described addressing and startup be prohibited schedule time amount after described programmable conductor random access memory unit begins logic state is transferred to the bit line of described addressing and startup.
7. memory device as claimed in claim 6, wherein said sensor amplifier comprise that also first sensor amplifier part and second reads amplifier section.
8. memory device as claimed in claim 7, wherein said schedule time amount are to read before amplifier section is activated after described first sensor amplifier partly is activated and described second.
9. memory device as claimed in claim 7, wherein said first sensor amplifier partly is the N-sensor amplifier, and described second to read amplifier section be the P-sensor amplifier.
10. memory device as claimed in claim 1 also comprises:
Pre-charge circuit is used for bit line and another bit line precharge-to-precharge voltage with addressing and startup, and the bit line of wherein said addressing and startup and described another bit line are coupled to sensor amplifier.
11. memory device as claimed in claim 10, wherein said pre-charge circuit are read at sensor amplifier before the bit line of described addressing and startup precharge is carried out in addressing and the bit line and another bit line that start.
12. the system based on processor comprises:
Processor; With
Storer, described storer also comprises:
Be used for from the device of programmable conductor random access memory unit read data, described device comprises:
Place in circuit is used for during the read operation described programmable conductor random access memory unit being coupling between the bit line of addressing and the word line that starts and addressing and startup;
Be coupled to the sensor amplifier of the bit line of described addressing and startup, be used to read the logic state of described programmable conductor random access memory unit; And
Prevent circuit, be used to prevent the described read operation of described programmable conductor random access memory cell response and be refreshed, the described circuit that prevents comprises transistor, described transistor be connected the word line of described addressing and startup and be used for the driver of word line of described addressing and startup or ground between or be connected between the bit line and described sensor amplifier of described addressing and startup
The wherein said circuit that prevents makes that the word line of described addressing and startup is prohibited after the logic state of described programmable conductor random access memory unit is transferred to the bit line of described addressing and startup and read the logic state of described programmable conductor random access memory unit at described sensor amplifier before.
13. system as claimed in claim 12, wherein said transistor makes that the word line of described addressing and startup is prohibited.
14. system as claimed in claim 13, wherein said transistor is connected in series in the word line of described addressing and startup and is used between the driver of word line of described addressing and startup, and is switched on and is disconnected during described read operation so that prohibit the word line of moving described addressing and startup.
15. system as claimed in claim 13, wherein said transistor is connected between the word line and ground of described addressing and startup, and is disconnected and is switched on during described read operation so that prohibit the word line of moving described addressing and startup.
16. system as claimed in claim 12, wherein said transistor be connected in series in addressing and the bit line that starts and with sensor amplifier that addressing and the bit line that starts are associated between, the described transistor that is connected in series is being switched on during the read operation and had been disconnected before described programmable conductor random access memory unit can be refreshed.
17. system as claimed in claim 12, the wherein said circuit that prevents makes the word line of described addressing and startup be prohibited schedule time amount after described programmable conductor random access memory unit begins logic state is transferred to the bit line of described addressing and startup.
18. system as claimed in claim 17, wherein said sensor amplifier comprises that also first sensor amplifier part and second reads amplifier section.
19. system as claimed in claim 18, wherein said schedule time amount read before amplifier section is activated after described first sensor amplifier partly is activated and described second.
20. system as claimed in claim 18, wherein said first sensor amplifier partly is the N-sensor amplifier, and described second to read amplifier section be the P-sensor amplifier.
21. system as claimed in claim 12 also comprises:
Pre-charge circuit is used for bit line and another bit line precharge-to-precharge voltage with addressing and startup, and the bit line of wherein said addressing and startup and described another bit line are coupled to sensor amplifier.
22. system as claimed in claim 21, wherein said pre-charge circuit is read at sensor amplifier before the bit line of described addressing and startup precharge is carried out in addressing and the bit line and another bit line that start.
23. one kind is used for from the method for programmable conductor random access memory unit read data, described method comprises step:
The bit line and the reference bit lines of addressing are pre-charged to predetermined pre-charge voltage;
Start the word line of the addressing comprise described programmable conductor random access memory unit and the logical value in the described programmable conductor random access memory unit is transferred to the bit line of the addressing that is associated;
After the described logical value of described programmable conductor random access memory unit is transferred to the bit line of described addressing, prohibit the word line of moving described addressing;
The logical value of being read the bit line that is transferred to described addressing after prohibiting at the word line of described addressing; And
Be refreshed because of described read operation to prevent described programmable conductor random access memory unit by starting transistor read the logical value of described programmable conductor random access memory unit at sensor amplifier before, described transistor be connected the word line of described addressing and be used for the driver of word line of described addressing or ground between or be connected between the bit line and described sensor amplifier of described addressing.
24. method as claimed in claim 23, wherein said taboo is moving to be that predetermined amount of time after startup comprises the word line of addressing of described programmable conductor random access memory unit is carried out.
25. method as claimed in claim 23, wherein said sensor amplifier comprise that the first sensor amplifier unit and second reads amplifier unit, wherein said reading further comprise,
Start the first sensor amplifier unit; And
Second schedule time after the described first sensor amplifier unit starting starts second and reads amplifier unit.
26. method as claimed in claim 25, wherein said taboo is moving to be to measure first schedule time after the described startup of the word line of addressing to carry out.
27. method as claimed in claim 26, wherein said first schedule time amount be after the described startup of the described first sensor amplifier unit and described second read the described startup of amplifier unit before.
28. method as claimed in claim 26, wherein said first schedule time amount be before the described startup of the described first sensor amplifier unit and described second read the described startup of amplifier unit before.
29. one kind is used for from the method for programmable conductor random access memory unit read data, described method comprises step:
Start the word line of the addressing be connected to described programmable conductor random access memory unit and the logical value in the described programmable conductor random access memory unit is transferred to the bit line of the addressing that is associated;
Disconnection is positioned on the bit line of the addressing that is associated and isolated transistor that be connected in series sensor amplifier and described programmable conductor random access memory unit, and wherein said disconnection is to measure first schedule time after the described startup of the word line of addressing to carry out; And
After described disconnection, read the logical value of the described programmable conductor random access memory unit that is transferred to described bit line at the sensor amplifier place.
30. method as claimed in claim 29, wherein said sensor amplifier comprise that the first sensor amplifier unit and second reads amplifier unit, wherein said reading further comprise,
Start the first sensor amplifier unit; And
Second schedule time after the described startup of the described first sensor amplifier unit starts second and reads amplifier unit.
31. method as claimed in claim 30, wherein said first schedule time amount be after the described startup of the described first sensor amplifier unit and described second read the described startup of amplifier unit before.
32. method as claimed in claim 30, wherein said first schedule time amount be before the described startup of the described first sensor amplifier unit and described second read the described startup of amplifier unit before.
33. one kind is used for from the method for programmable conductor random access memory unit read data, described method comprises step:
First bit line that is coupled to the programmable conductor random access memory unit is carried out precharge, and described programmable conductor random access memory unit comprises array of programmable conductor memory elements;
Precharge second bit line;
Be increased in the voltage on described first bit line;
Connect the access transistor of described programmable conductor random access memory unit so that array of programmable conductor memory elements is coupled to described first bit line;
The word line of prohibiting moving addressing is to disconnect the access transistor of described programmable conductor random access memory unit, so that array of programmable conductor memory elements and described first bitline separation; And
Read the voltage on described first bit line and described second bit line at the sensor amplifier place, so that determine the logic state of described array of programmable conductor memory elements;
Wherein said taboo is moving be carry out at the preset time before described the reading and described second bit line before being changed, keep pre-charge voltage by read operation.
34. one kind is used for from the method for programmable conductor random access memory unit read data, described method comprises step:
Connect isolated transistor, so that first bit line is coupled to sensor amplifier, described first bit line also is coupled to the array of programmable conductor memory elements of programmable conductor random access memory unit;
Described first bit line of precharge;
Precharge second bit line;
Increase the voltage on described first bit line;
Disconnect described isolated transistor, so that described array of programmable conductor memory elements is separated with described sensor amplifier;
Read the voltage on described first bit line and described second bit line, so that determine the logic state of described array of programmable conductor memory elements;
Wherein said disconnection is to carry out in first schedule time amount before described the reading and after the startup of the word line that is addressing.
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| CN201110044307.8A CN102169725B (en) | 2002-01-04 | 2003-01-06 | Memory device and the system based on processor |
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| US10/035,197 US6909656B2 (en) | 2002-01-04 | 2002-01-04 | PCRAM rewrite prevention |
| PCT/US2003/000239 WO2003058634A1 (en) | 2002-01-04 | 2003-01-06 | Pcram rewrite prevention |
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| EP1468422B1 (en) | 2012-03-07 |
| CN1679116A (en) | 2005-10-05 |
| JP2005515577A (en) | 2005-05-26 |
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| KR100616208B1 (en) | 2006-08-25 |
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| US6909656B2 (en) | 2005-06-21 |
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| CN102169725B (en) | 2015-10-28 |
| US20050146958A1 (en) | 2005-07-07 |
| KR20040075053A (en) | 2004-08-26 |
| CN102169725A (en) | 2011-08-31 |
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