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CN1649253A - Crystal Accelerated Oscillator Circuit - Google Patents

Crystal Accelerated Oscillator Circuit Download PDF

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CN1649253A
CN1649253A CN 200410002408 CN200410002408A CN1649253A CN 1649253 A CN1649253 A CN 1649253A CN 200410002408 CN200410002408 CN 200410002408 CN 200410002408 A CN200410002408 A CN 200410002408A CN 1649253 A CN1649253 A CN 1649253A
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amplifier
flip
flop
crystal
amplifier group
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CN100414834C (en
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林盟智
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Sunplus Technology Co Ltd
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Abstract

The invention relates to a crystal acceleration oscillation circuit, which comprises a quartz oscillation crystal for generating an oscillation signal, an amplifier group, a feedback resistor, a first trigger, a second trigger and amplifier switch logic. The amplifier group is used for amplifying the oscillation signal; the feedback resistor is used for establishing a direct current working bias voltage of the amplifier group; the input end of the first trigger is connected with the output end of the amplifier group so as to trigger the first trigger by the amplified oscillating signal to generate a first clock output; the input end of the second trigger is connected with the output end of the amplifier group so as to trigger the second trigger by the amplified oscillating signal to generate a second clock output, wherein the second trigger has a hysteresis voltage which is more than a preset value; the amplifier switch is logically connected to the second flip-flop to gradually decrease the amplification intensity of the amplifier group when the second flip-flop is detected to generate the second clock output.

Description

晶体加速振荡电路Crystal Accelerated Oscillator Circuit

技术领域technical field

本发明是关于一种晶体振荡电路,尤指一种可确保振荡的晶体加速振荡电路The invention relates to a crystal oscillation circuit, especially to a crystal acceleration oscillation circuit capable of ensuring oscillation

背景技术Background technique

图1显示一传统的晶体振荡电路(Crystal Oscillator),其包括一反相放大器11、一回授电阻12、一石英振荡晶体13、一组电容对14、及一施密特触发器16,其中,反相放大器11用于信号放大,以提供整体晶体振荡回路信号增益(Gain),施密特触发器16是由反相放大器11产生的放大信号所触发而输出时钟信号CLK,回授电阻12用于建立反相放大器11的直流工作偏压,石英振荡晶体13用以产生具有一谐振(resonance)频率的振荡信号,电容对14用于使整体晶体振荡回路的并联谐振(Parallelresonance)非常接近串联谐振(Series resonance),而晶体振荡回路的振荡频率介于两者之间。FIG. 1 shows a traditional crystal oscillator circuit (Crystal Oscillator), which includes an inverting amplifier 11, a feedback resistor 12, a quartz oscillator crystal 13, a group of capacitor pairs 14, and a Schmitt trigger 16, wherein , the inverting amplifier 11 is used for signal amplification to provide the overall crystal oscillator circuit signal gain (Gain), the Schmitt trigger 16 is triggered by the amplified signal generated by the inverting amplifier 11 and outputs the clock signal CLK, and the feedback resistor 12 Used to establish the DC operating bias of the inverting amplifier 11, the quartz oscillator crystal 13 is used to generate an oscillation signal with a resonance frequency, and the capacitor pair 14 is used to make the parallel resonance (Parallelresonance) of the overall crystal oscillator circuit very close to series Resonance (Series resonance), and the oscillation frequency of the crystal oscillation circuit is between the two.

以前述的晶体振荡电路,由于反相放大器11的信号频宽、放大增益会随着工作电压、制程参数、负载电容对变化,而这种变动在许多实际应用常会造成晶体振荡电路起振时间过长或甚至无法振荡。With the aforementioned crystal oscillator circuit, since the signal bandwidth and amplification gain of the inverting amplifier 11 will vary with the operating voltage, process parameters, and load capacitance pairs, and this change will often cause the crystal oscillator circuit to start oscillating too long in many practical applications. long or even unable to oscillate.

为解决前述的问题,现有提出如图2所示的改良晶体振荡电路,其是以并联多个反相放大器11来达到使晶体振荡器快速起振的目的,图3显示其反相放大器11的切换方式,其首先是在电源电压起始时(步骤S301),打开所有反相放大器11(此时称为Strongmode),由于此时的放大器11的放大增益非常高,故能达到使晶体振荡器快速起振的目的。但此时的放大器耗电也非常大,为了达到省电的需求,所以将产生的时钟CLK送入N-bit计数器17(步骤S302),在经过2N个时钟后,计数器17计时终了,只保留维持晶体振荡电路继续振荡的一个基本反相放大器11(此时称为Weak mode),而将其余的反相放大器11关闭(步骤S303)。In order to solve the aforementioned problems, an improved crystal oscillator circuit as shown in Figure 2 is currently proposed, which uses a plurality of inverting amplifiers 11 in parallel to achieve the purpose of quickly starting the crystal oscillator, and Figure 3 shows its inverting amplifier 11 Switching mode, it first is when the power supply voltage starts (step S301), turns on all inverting amplifiers 11 (this time called Strongmode), because the amplification gain of the amplifier 11 at this time is very high, so it can achieve crystal oscillation The purpose of quick start-up of the device. But the amplifier power consumption of this moment is also very big, in order to reach the demand of power saving, so the clock CLK that will produce is sent into N-bit counter 17 (step S302), after passing through 2 N clocks, counter 17 timing finishes, only One basic inverting amplifier 11 that maintains the crystal oscillator circuit to continue to oscillate is reserved (called Weak mode at this time), and the rest of the inverting amplifiers 11 are turned off (step S303 ).

前述的改良晶体加速振荡电路锥可通过由并联多个反相放大器11来达到快速起振的目的,然而,当起振之后,由于只保留了一个基本反相放大器11,因此,起振后的晶体振荡电路仍如同传统的晶体振荡电路一般,会因为工作电压、制程参数、负载电容对之变化,而导致晶体振荡电路不振荡的问题。The aforesaid improved crystal accelerated oscillation circuit cone can achieve the purpose of fast start-up by connecting multiple inverting amplifiers 11 in parallel. However, after starting the oscillation, since only one basic inverting amplifier 11 is reserved, the The crystal oscillating circuit is still the same as the traditional crystal oscillating circuit, and the crystal oscillating circuit will not oscillate due to changes in the operating voltage, process parameters, and load capacitance.

发明内容Contents of the invention

本发明的一目的是在提供一种晶体加速振荡电路,其可确保一定会振荡,不会因制程、负载电容和电源电压的变动而停止振荡。An object of the present invention is to provide a crystal speed-up oscillation circuit, which can ensure that it will oscillate and will not stop oscillating due to changes in manufacturing process, load capacitance and power supply voltage.

本发明的另一目的是在提供一种晶体加速振荡电路,其能有效地缩短起振时间。Another object of the present invention is to provide a crystal accelerated oscillator circuit, which can effectively shorten the start-up time.

本发明的再一目的是在提供一种晶体加速振荡电路,其可将耗电流自动调整到最小。Another object of the present invention is to provide a crystal speed-up oscillator circuit, which can automatically adjust the current consumption to the minimum.

本发明的又一目的是在提供一种晶体加速振荡电路,其可更换不同频率的电晶体振荡器,而不会造成不振荡的问题或是耗电流过大的问题。Another object of the present invention is to provide a crystal speed-up oscillation circuit, which can be replaced with transistor oscillators of different frequencies without causing the problem of non-oscillation or excessive current consumption.

为达成上述目的,本发明的晶体加速振荡电路包括:一石英振荡晶体,用以产生一振荡信号;一放大器组,用以将该振荡信号放大,而在其输出端产生一放大振荡信号,其中,在电源开启时,该放大器组具有最大放大强度;一回授电阻,其跨接于该放大器组,用以建立该放大器组的直流工作偏压;一第一触发器,其输入端连接于该放大器组的输出端,以便由该放大振荡信号触发该第一触发器而产生一第一时钟输出;一第二触发器,其输入端连接于该放大器组的输出端,以便由该放大振荡信号触发该第二触发器而产生一第二时钟输出,其中,该第二触发器具有一大于一预设值的迟滞电压;以及,一放大器开关逻辑,其连接至该第二触发器,以当检测出该第二触发器有产生第二时钟输出时,逐渐减低该放大器组的放大强度。To achieve the above object, the crystal acceleration oscillation circuit of the present invention includes: a quartz oscillator crystal, used to generate an oscillation signal; an amplifier group, used to amplify the oscillation signal, and generate an amplified oscillation signal at its output terminal, wherein , when the power is turned on, the amplifier group has the maximum amplification strength; a feedback resistor, which is connected across the amplifier group, is used to establish the DC working bias voltage of the amplifier group; a first flip-flop, whose input terminal is connected to The output end of the amplifier group, so that the first flip-flop is triggered by the amplified oscillation signal to generate a first clock output; the input end of a second flip-flop is connected to the output end of the amplifier group, so as to be amplified by the amplified oscillation A signal triggers the second flip-flop to generate a second clock output, wherein the second flip-flop has a hysteresis voltage greater than a preset value; and an amplifier switch logic is connected to the second flip-flop to when When it is detected that the second flip-flop generates the second clock output, the amplification strength of the amplifier group is gradually reduced.

附图说明Description of drawings

图1是显示一传统晶体振荡电路;Figure 1 shows a conventional crystal oscillator circuit;

图2是显示一改良的传统晶体振荡电路;Fig. 2 shows an improved traditional crystal oscillator circuit;

图3是显示改良的传统晶体振荡电路的反相放大器的切换流程;Fig. 3 shows the switching process of the inverting amplifier of the improved traditional crystal oscillator circuit;

图4是本发明的晶体加速振荡电路的一实施例;Fig. 4 is an embodiment of the crystal accelerated oscillation circuit of the present invention;

图5是本发明的晶体加速振荡电路的反相放大器的切换流程;Fig. 5 is the switching process of the inverting amplifier of the crystal accelerated oscillation circuit of the present invention;

图6是本发明的晶体加速振荡电路的另一实施例。FIG. 6 is another embodiment of the crystal accelerated oscillation circuit of the present invention.

具体实施方式Detailed ways

为能更了解本发明的技术内容,特举0较佳具体实施例说明如下。In order to better understand the technical content of the present invention, the preferred specific embodiments are illustrated as follows.

图4为本发明的晶体加速振荡电路的一实施例,其包括一放大器组41、一回授电阻42、一石英振荡晶体43、一组电容对44、一第一触发器46、一第二触发器47、及一放大器开关逻辑48。其中,该放大器组41包括多数个并联的放大器411,用于信号放大,以提供整体晶体振荡回路信号增益(Gain),该等放大器411较佳为反相放大器;该回授电阻42跨接于该放大器组41,用以建立放大器组的直流工作偏压(Direct current operationbias);该石英振荡晶体43跨接于该回授电阻42及该放大器组41,用以产生一具有一谐振(resonance)频率的振荡信号;该电容对44的电容441及442分别连接于该石英振荡晶体43的两端,以用于使整体晶体振荡回路的串联谐振(Series resonance)非常接近并联谐振(Parallel resonance),而晶体振荡回路的振荡频率介于两者之间。Fig. 4 is an embodiment of the crystal acceleration oscillation circuit of the present invention, and it comprises an amplifier group 41, a feedback resistor 42, a quartz oscillator crystal 43, a group of capacitance pair 44, a first flip-flop 46, a second flip-flop 47, and an amplifier switching logic 48. Wherein, the amplifier group 41 includes a plurality of parallel amplifiers 411 for signal amplification to provide the overall crystal oscillator circuit signal gain (Gain), these amplifiers 411 are preferably inverting amplifiers; the feedback resistor 42 is connected across The amplifier group 41 is used to establish the DC operating bias (Direct current operation bias) of the amplifier group; the quartz oscillator crystal 43 is connected across the feedback resistor 42 and the amplifier group 41 to generate a resonance frequency oscillation signal; the capacitance 441 and 442 of the capacitance pair 44 are respectively connected to the two ends of the quartz oscillator crystal 43, so as to make the series resonance (Series resonance) of the overall crystal oscillation circuit very close to the parallel resonance (Parallel resonance), The oscillation frequency of the crystal oscillation circuit is between the two.

前述的第一触发器46是为一具有较小迟滞电压的小振幅史密斯触发器(Small-swing Schmitt-trigger),其输入端连接于该放大器组41的输出,以便由该放大器组41所输出的放大信号触发而产生时钟输出CLK,此小振幅的史密斯触发器亦可以一般的反相放大器替代。前述的第二触发器47是为一具有较大迟滞电压的大振幅史密斯触发器(Large-swing Schmit-trigger),其输入端连接于该放大器组41的输出,用以检测该放大器组41的放大信号输出振幅,当其大于该第二拖密特触发器47的迟滞电压时,则产生一增强时钟输出XCLK,以馈入该放大器开关逻辑48。Aforesaid first flip-flop 46 is a small-amplitude Smith trigger (Small-swing Schmitt-trigger) with less hysteresis voltage, and its input terminal is connected to the output of this amplifier group 41, so that by this amplifier group 41 output The amplified signal triggers to generate the clock output CLK, and this small-amplitude Smith trigger can also be replaced by a general inverting amplifier. The aforementioned second trigger 47 is a large-amplitude Smith trigger (Large-swing Schmit-trigger) with a larger hysteresis voltage, and its input terminal is connected to the output of the amplifier group 41 to detect the output of the amplifier group 41. When the output amplitude of the amplified signal is greater than the hysteresis voltage of the second dragmitter 47 , an enhanced clock output XCLK is generated to feed into the amplifier switching logic 48 .

前述放大器开关逻辑48是用以调整开启的反相放大器的数目,以节省耗电流,图5显示前述放大器开关逻辑48的切换方式,首先,在电源启动时将该放大器组41此的所有反相放大器全部打开(步骤S501),因此,晶体加速振荡电路将很快地起振,而由于此时所有放大器411均打开而耗电流较大,且为避免一次关闭放大器411而导致晶体加速振荡电路在起振后又无法振荡的问题,因此,放大器开关逻辑48是在该第二触发器47有产生增强时钟输出XCLK时(步骤S502),逐一减低该放大器组41的放大强度(步骤S503),亦即,逐一关闭该放大器组41的放大器411,直到该第二触发器47未有产生增强时钟输出XCLK或该放大器组41只剩一开启的放大器411时(步骤S504)。The aforementioned amplifier switching logic 48 is used to adjust the number of inverting amplifiers turned on to save current consumption. FIG. 5 shows the switching mode of the aforementioned amplifier switching logic 48. The phase amplifiers are all turned on (step S501), therefore, the crystal acceleration oscillation circuit will start up quickly, and because all the amplifiers 411 are turned on at this time, the current consumption is relatively large, and the crystal acceleration oscillation is caused to avoid closing the amplifiers 411 once The problem that the circuit cannot oscillate after starting to oscillate, therefore, the amplifier switching logic 48 reduces the amplification strength of the amplifier group 41 one by one (step S503) when the second flip-flop 47 generates an enhanced clock output XCLK (step S502). , that is, turn off the amplifiers 411 of the amplifier group 41 one by one until the second flip-flop 47 does not generate the enhanced clock output XCLK or only one amplifier 411 is turned on in the amplifier group 41 (step S504).

于前述的切换流程中,当开始没有增强时钟输出XCLK时,表示该放大器组41的放大强度已被减弱无法使第二触发器47产生增强时钟输出XCLK,但由于前述第二触发器47是为一大振幅史密斯触发器,其迟滞电压远大于该第一触发器46,因此,放大器组41的放大强度仍足以使第一触发器46产生时钟输出CLK,因而确保在关闭反相放大器以节省耗电流之后,晶体加速振荡电路仍可振荡。In the foregoing switching process, when there is no enhanced clock output XCLK at the beginning, it means that the amplification strength of the amplifier group 41 has been weakened so that the second flip-flop 47 cannot generate the enhanced clock output XCLK, but because the aforementioned second flip-flop 47 is for Large amplitude Smith trigger, its hysteresis voltage is much larger than this first flip-flop 46, therefore, the amplification strength of amplifier group 41 is still enough to make the first flip-flop 46 generate the clock output CLK, thus ensure that the inverting amplifier is turned off to save power consumption. After the current flow, the crystal accelerated oscillation circuit can still oscillate.

前述的放大器开关逻辑48可为一N位元计数器,此计数器用以计数该增强时钟输出XCLK的时脉数,以当计数终了时,关闭该放大器组41的一反相放大器,再重置计数器并重新计数。The aforementioned amplifier switching logic 48 can be an N-bit counter, which is used to count the number of clock pulses of the boosted clock output XCLK, so that when the count ends, an inverting amplifier of the amplifier group 41 is turned off, and the counter is reset and recount.

图6显示本发明的晶体加速振荡电路的另一实施例,其于前一实施例的不同处在于放大器组61是由多数个并联的电流源611及一由该等电流源所控制的放大器612所构成,此放大器612较佳为一电流控制反相放大器,而该放大器开关逻辑48是以逐一关闭该放大器组61的电流源611来达成逐一减低该放大器组61的放大强度的作用。Fig. 6 shows another embodiment of the crystal accelerated oscillation circuit of the present invention, and its difference from the previous embodiment is that the amplifier group 61 is composed of a plurality of parallel current sources 611 and an amplifier 612 controlled by these current sources As a result, the amplifier 612 is preferably a current-controlled inverting amplifier, and the amplifier switching logic 48 turns off the current sources 611 of the amplifier group 61 one by one to reduce the amplification strength of the amplifier group 61 one by one.

由以上的说明可知,本发明的晶体加速振荡电路是通过由以多数放大器同时启动、且在大振幅的史密斯触发器产生时钟信号时,逐一降低放大器的放大强度,直至大振幅的史密斯触发器未有产生时钟信号,而达成振荡的目的,其具有下述的优点:As can be seen from the above description, the crystal accelerated oscillation circuit of the present invention is to reduce the amplification strength of the amplifiers one by one when the large-amplitude Smith trigger generates a clock signal by simultaneously starting with a large number of amplifiers until the large-amplitude Smith trigger does not There is a clock signal to achieve the purpose of oscillation, which has the following advantages:

一、保证此振荡电路一定会振荡,不会因制程、负载电容和电源电压的变动而停止振荡;1. Ensure that the oscillating circuit will oscillate and will not stop oscillating due to changes in manufacturing process, load capacitance and power supply voltage;

二、能有效地缩短振荡电路的起振时间;2. It can effectively shorten the start-up time of the oscillating circuit;

三、振荡电路的开启的反相放大器数目会自动调整到最少,故耗电流也会自动调整到最小;及3. The number of activated inverting amplifiers of the oscillation circuit will be automatically adjusted to the minimum, so the current consumption will also be automatically adjusted to the minimum; and

四、在某些应用需要更换不同频率的石英振荡晶体,此架构仍可适用。4. In some applications, it is necessary to replace the quartz oscillator crystal with a different frequency, and this structure is still applicable.

上述实施例仅是为了方便说明而举例而已,本发明所主张的权利范围自应以申请专利范围所述为准,而非仅限于上述实施例。The above-mentioned embodiments are only examples for convenience of description, and the scope of rights claimed by the present invention should be based on the scope of the patent application, rather than limited to the above-mentioned embodiments.

Claims (10)

1.一种晶体加速振荡电路,其特征在于,包括;1. A crystal accelerated oscillation circuit, characterized in that, comprising; 一石英振荡晶体,用以产生一振荡信号;A quartz oscillating crystal is used to generate an oscillating signal; 一放大器组,用以将该振荡信号放大,而在其输出端产生一放大振荡信号,其中,在电源开启时,该放大器组具有最大放大强度;An amplifier group is used to amplify the oscillating signal to generate an amplified oscillating signal at its output terminal, wherein, when the power is turned on, the amplifier group has the maximum amplification strength; 一回授电阻,其跨接于该放大器组,用以建立该放大器组的直流工作偏压;a feedback resistor connected across the amplifier group to establish a DC working bias voltage of the amplifier group; 一第一触发器,其输入端连接于该放大器组的输出端,以便由该放大振荡信号触发该第一触发器而产生一第一时钟输出;A first flip-flop, the input end of which is connected to the output end of the amplifier group, so that the first flip-flop is triggered by the amplified oscillation signal to generate a first clock output; 一第二触发器,其输入端连接于该放大器组的输出端,以便由该放大振荡信号触发该第二触发器而产生一第二时钟输出,其中,该第二触发器具有一大于一预设值的迟滞电压;以及A second flip-flop whose input end is connected to the output end of the amplifier group, so that the second flip-flop is triggered by the amplified oscillating signal to generate a second clock output, wherein the second flip-flop has a value greater than a preset value of the hysteresis voltage; and 一放大器开关逻辑,其连接至该第二触发器,以当检测出该第二触发器有产生第二时钟输出时,逐渐减低该放大器组的放大强度。An amplifier switching logic, connected to the second flip-flop, is used to gradually reduce the amplification strength of the amplifier group when it is detected that the second flip-flop generates a second clock output. 2.如权利要求1所述的晶体加速振荡电路,其特征在于,所述该第一触发器为一第一施密特触发器,该第二触发器为一第二施密特触发器,该第二施密特触发器的迟滞电压大于该第一施密特触发器的迟滞电压。2. The crystal accelerated oscillation circuit according to claim 1, wherein the first trigger is a first Schmitt trigger, the second trigger is a second Schmitt trigger, The hysteresis voltage of the second Schmitt trigger is greater than that of the first Schmitt trigger. 3.如权利要求1所述的晶体加速振荡电路,其特征在于,所述该第一触发器为一反相放大器,该第二触发器为一施密特触发器。3. The crystal accelerated oscillator circuit as claimed in claim 1, wherein the first flip-flop is an inverting amplifier, and the second flip-flop is a Schmitt trigger. 4.如权利要求2所述的晶体加速振荡电路,其特征在于,其更包含分别连接于该石英振荡晶体的两端的一组电容对。4. The crystal accelerated oscillation circuit as claimed in claim 2, further comprising a set of capacitor pairs respectively connected to two ends of the quartz oscillator crystal. 5.如权利要求2所述的晶体加速振荡电路,其特征在于,所述该放大器组包括多数个并联的反相放大器。5. The crystal accelerated oscillator circuit as claimed in claim 2, wherein the amplifier group comprises a plurality of inverting amplifiers connected in parallel. 6.如权利要求5所述的晶体加速振荡电路,其特征在于,所述该放大器开关逻辑是在检测出该第二触发器有产生第二时钟输出时,逐一关闭该放大器组的反相放大器,直到该第二触发器未有产生第二时钟输出或该放大器组只剩一开启的反相放大器时。6. The crystal accelerated oscillation circuit according to claim 5, wherein the amplifier switching logic is to turn off the inverting amplifiers of the amplifier group one by one when detecting that the second flip-flop generates a second clock output , until the second flip-flop does not generate the second clock output or there is only one inverting amplifier turned on in the amplifier group. 7.如权利要求6所述的晶体加速振荡电路,其特征在于,所述该放大器开关逻辑包括一计数器,该计数器用以计数该第二时钟输出时,以当计数终了时,关闭该放大器组的一反相放大器。7. The crystal accelerated oscillation circuit according to claim 6, wherein the amplifier switching logic comprises a counter, the counter is used to count the output of the second clock, so that when the count ends, the amplifier group is turned off an inverting amplifier. 8.如权利要求2所述的晶体加速振荡电路,其特征在于,所述该放大器组包括多数个并联的电流源及一电流控制反相放大器,该电流控制反相放大器是由该等并联的电流源所控制。8. The crystal accelerated oscillator circuit as claimed in claim 2, wherein the amplifier group includes a plurality of parallel current sources and a current control inverting amplifier, and the current control inverting amplifier is formed by the parallel connection controlled by the current source. 9.如权利要求8所述的晶体加速振荡电路,其特征在于,所述该放大器开关逻辑是在检测出该第二触发器有产生第二时钟输出时,逐一关闭该放大器组的电流源,直到该第二触发器未有产生第二时钟输出或该放大器组只剩一开启的电流源时。9. The crystal accelerated oscillation circuit according to claim 8, wherein the amplifier switching logic is to turn off the current sources of the amplifier group one by one when detecting that the second flip-flop generates a second clock output, Until the second flip-flop does not generate the second clock output or only one current source is turned on in the amplifier group. 10.如权利要求9所述的晶体加速振荡电路,其特征在于,所述该放大器开关逻辑包括一计数器,该计数器用以计数该第二时钟输出时,以当计数终了时,关闭该放大器组的一电流源。10. The crystal accelerated oscillator circuit according to claim 9, wherein the amplifier switch logic comprises a counter, the counter is used to count the output of the second clock, so that when the count ends, the amplifier group is turned off of a current source.
CNB2004100024089A 2004-01-29 2004-01-29 Crystal Accelerated Oscillator Circuit Expired - Fee Related CN100414834C (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104965471A (en) * 2015-07-13 2015-10-07 杭州晟元芯片技术有限公司 Power consumption configurable oscillation circuit processing circuit and method
CN109831161A (en) * 2019-01-25 2019-05-31 广州全盛威信息技术有限公司 Crystal oscillating circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2716869B2 (en) * 1990-11-29 1998-02-18 株式会社東芝 Oscillation circuit
US5486795A (en) * 1993-04-22 1996-01-23 Rockwell International Corporation Low power crystal oscillator
JP3141816B2 (en) * 1997-06-19 2001-03-07 日本電気株式会社 Oscillator circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104965471A (en) * 2015-07-13 2015-10-07 杭州晟元芯片技术有限公司 Power consumption configurable oscillation circuit processing circuit and method
CN109831161A (en) * 2019-01-25 2019-05-31 广州全盛威信息技术有限公司 Crystal oscillating circuit
CN109831161B (en) * 2019-01-25 2023-04-28 广州全盛威信息技术有限公司 Crystal oscillation circuit

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