WO2016000654A1

WO2016000654A1 - Digital output buffer and control method therefor

Info

Publication number: WO2016000654A1
Application number: PCT/CN2015/083257
Authority: WO
Inventors: 陈锋
Original assignee: 王玮冰
Priority date: 2014-07-03
Filing date: 2015-07-03
Publication date: 2016-01-07
Also published as: CN104320122B; CN104320122A

Abstract

A digital output buffer and the control method therefor are disclosed. The digital output buffer includes a timing generator(1), an integrator(2), a residual current detector(3), an energy storage device(4), an inductor L, a load capacitor CL, a first transistor SW1, a second transistor SW2 and a third transistor SW3. The energy storage device(4), the inductor L, the load capacitor CL, the first transistor SW1, the second transistor SW2 and the third transistor SW3 constitute the main circuit of the digital output buffer, and the integrator(2) and the residual current detector(3) constitute the negative feedback circuit of the digital output buffer. Thereby, the power consumption of the digital output buffer can be effectively reduced.

Description

Digital output buffer and control method thereof

Technical field

The present invention relates to the field of output buffer technologies, and in particular, to a digital output buffer and a control method thereof.

Background technique

As the frequency of the digital signal rises, the digital output buffer consumes a large amount of power when it buffers the output of the data. Therefore, it is necessary to design a digital output buffer that reduces power consumption.

Chinese Patent Publication No. CN103269217, published on August 28, 2013, the name of the invention is an output buffer, the application discloses an output buffer comprising first and second transistors and a self-biasing circuit, first The transistor has a control electrode, an input electrode coupled to the output end, and an output electrode, and the second transistor has a control electrode, an input electrode coupled to the output electrode of the first transistor, and an output electrode coupled to the reference voltage, and the self-bias circuit is coupled to the output end And a control electrode of the first transistor. The downside is that the output buffer consumes a lot of power.

Summary of the invention

The object of the present invention is to overcome the technical problem of large power consumption of the existing digital output buffer, and to provide a digital output buffer capable of reducing power consumption and a control method thereof.

In order to solve the above problems, the present invention is implemented by the following technical solutions:

The invention provides a digital output buffer comprising a timing generator, an integrator, a residual current detector, an energy storage device, an inductance L, a load capacitance CL, a first switching tube SW1, and a second opening The switch SW2 and the third switch SW3 are connected to each other. The other end of the accumulator is electrically connected to the first conductive end of the third switch SW3, and the second switch is the second switch SW3. The conductive terminal is electrically connected to one end of the inductor L, and the other end of the inductor L is electrically connected to the upper plate of the load capacitor CL, the first conductive end of the first switch tube SW1, and the first conductive end of the second switch tube SW2. The second conductive terminal of the capacitor CL and the second conductive terminal of the second switching transistor SW2 are both grounded, and the second conductive terminal of the first switching transistor SW1 is electrically connected to the power supply VDD, and the first switching transistor SW1 The control terminal, the control terminal of the second switch SW2 and the control terminal of the third switch SW3 are respectively electrically connected to the timing generator, and the two detection ends of the residual current detector are respectively the first of the third switch SW3 The conductive end and the second conductive end are electrically connected, the output end of the residual current detector is electrically connected to the input end of the integrator, and the output end of the integrator is electrically connected to the second input end of the timing generator. The first input of the timing generator is the signal input of the digital output buffer.

In the technical solution, the energy storage device, the inductor L, the load capacitance CL, the first switch tube SW1, the second switch tube SW2 and the third switch tube SW3 constitute a main circuit of the digital output buffer, and its function is through the control A switch tube SW1, a second switch tube SW2, and a third switch tube SW3 are used to control the LC oscillation to carry the charge on the accumulator to the load capacitor CL according to the input signal Din, or to charge the charge on the CL according to the input signal. Din is moved to the accumulator without loss, so that the low-to-high transition and the high-to-low transition can be achieved at the output port Dout. The accumulator can be implemented with a capacitor or voltage source. The first switch tube SW1 and the second switch tube SW2 enhance the level of the digital output port Dout, and maintain Dout at a low level of low resistance and a low level of low resistance.

During the process of the input signal Din transitioning from a low level to a high level and then from a high level to a low level, the digital output buffer operates in four stages of T1, T2, T3, and T4, and timing generation occurs. The device controls the first switch tube SW1, the second switch tube SW2, and the third switch tube SW3 to operate.

When the input signal Din transitions from a low level to a high level, the interval T1 is entered, the third switch tube SW3 is turned on, the first switch tube SW1 and the second switch tube SW2 are turned off, and the charge stored in the accumulator passes through the first The three-switching tube SW3 is supplied to the inductor L. Since the inductor L and the load capacitor CL form a series resonant circuit, the load capacitor CL is charged with a voltage due to resonance, and the voltage of the upper plate can freely oscillate to VDD. In the T1 interval, the current in the inductor L increases from 0 to the positive direction. After reaching the peak value, the voltage of the plate on the load capacitor CL oscillates to the highest point, and the current in the inductor L returns to zero.

Then enter the T2 interval, the current in the inductor L returns to 0, which is the end point of the T1 interval, and is the starting point of the T2 interval. The first switch SW1 is turned on, the second switch SW2 and the third switch SW3 are disconnected, and the power supply VDD is boosted to the upper plate of the load capacitor CL through the first switch SW1, and the voltage of the upper plate of the load capacitor CL is reached. VDD, the output port Dout outputs a high level.

When the input signal Din transitions from a high level to a low level, the T3 interval is entered, the third switch tube SW3 is turned on, and the first switch tube SW1 and the second switch tube SW2 are turned off. The charge on the load capacitor CL passes through the inductor L, and the third switch SW3 is recovered by the accumulator. In this process, the voltage on the load capacitor CL oscillates freely from VDD to 0, and the current in the inductor L increases from 0 to the maximum point and then returns to 0.

Then enter the T4 interval, the current in the inductor L returns to 0, which is the end point of the T3 interval, and is the starting point of the T4 interval. The second switch SW2 is turned on, and the first switch SW1 and the third switch SW3 are turned off. The upper plate of the load capacitor CL is reinforced to GND via the second switch SW2, and the output port Dout outputs a low level.

The integrator and residual current detector form the negative feedback circuit of the digital output buffer. Since the current in the inductor L needs to end at the 0 point in the T1 phase and the T3 phase, the power consumption is reduced, and the circuit noise is generated by the high-frequency oscillation of the residual current in the inductor L. It is therefore important that the timing generator controls the duration of the T1 phase and the T3 phase.

The durations of the T1 phase and the T3 phase are the same, both being time T. The timing generator takes the time value corresponding to the Dsgm value of the latest received integrator output as the value of the time T. The integrator output Dsgm value includes the following steps: the integrator pre-sets an initial value to Dsgm, the initial value corresponds to a T time value, and the residual current detector detects when the timing generator controls the third switch tube SW3 to turn on T time. To the residual current in the inductor L, output the Dcmp value to the integrator, the Dcmp value reflects the direction of the residual current, or the Dcmp value reflects the direction and magnitude of the residual current. The integrator integrates the initial value of Dsgm and the received Dcmp value to obtain The latest Dsgm value and output the Dsgm value to the timing generator. The timing generator determines a corresponding time value according to the received Dsgm value, and uses the time value as the value of the time T.

Advantageously, the digital output buffer further comprises an error detector, a data processor and a frequency divider, the output of the integrator being further electrically coupled to the input of the error detector, the output of the error detector The end is electrically connected to the input end of the data processor, the output end of the data processor is electrically connected to the second output end of the frequency divider, the first input end of the frequency divider and the first input end of the timing generator Electrically connected, the output of the frequency divider is electrically coupled to the clock signal input of the error detector, the clock signal input of the integrator, and the clock signal input of the residual current detector.

The error detector, data processor, and divider form another negative feedback circuit for the digital output buffer. The error detector receives the Dsgm value of the integrator output, and calculates the error value Err of the received Dsgm value, and the error detector inputs the error value Err to the data processor, the data processor Calculating the frequency division multiple Fsel of the frequency divider according to the error value Err, and transmitting the frequency division multiple Fsel to the frequency divider, the frequency divider divides the input signal Din according to the frequency division multiple Fsel, and outputs a clock signal CLK corresponding to the frequency. To the error detector, integrator and residual current detector. The residual current detector and integrator are both triggered by the clock signal CLK. If the clock signal CLK is always operating at the highest frequency, then the entire circuit consumes a large amount of power. If the clock signal CLK is always operating at the lowest frequency, the overall circuit has weak anti-interference ability and the corresponding speed is slow. The negative feedback circuit consisting of error detector, data processor and frequency divider makes the digital output buffer save power and has strong anti-interference ability.

Preferably, the energy storage device is a capacitor or a voltage source.

The present invention provides a digital output buffer control method comprising the following steps:

S1: the timing generator reads the input signal Din, when the input signal Din jumps from a low level to a high level, then step S2 is performed, when the input signal Din jumps from a high level to a low level, then step S4 is performed;

S2: the timing generator controls the third switch tube SW3 to be turned on for T time, and controls the first switch tube SW1 and the second switch tube SW2 to be turned off for T time;

S3: At the end of the T time, the timing generator controls the first switch SW1 to be turned on, and controls the second switch SW2 and the third switch SW3 to be turned off;

S4: The timing generator controls the third switch tube SW3 to be turned on for T time, and controls the first switch tube SW1 and the second switch tube SW2 to be turned off for T time;

S5: At the end of the T time, the timing controller controls the second switch tube SW2 to be turned on, and controls the first switch tube SW1 and the third switch tube SW3 to be turned off;

The timing generator takes the time value corresponding to the Dsgm value of the newly received integrator output as the value of the time T, and the integrator output Dsgm value includes the following steps: the integrator pre-sets an initial value to the Dsgm, the initial value corresponding to a time value That is, the time value is the initial value of the time T. When the timing generator controls the third switch tube SW3 to turn on the T time, that is, when the third switch tube SW3 is turned off, the residual current detector detects the residual current in the inductor L. , the Dcmp value is output to the integrator, the Dcmp value reflects the direction of the residual current, or the Dcmp value reflects the direction and magnitude of the residual current, and the integrator integrates the initial value of Dsgm and all received Dcmp values to obtain the latest Dsgm value, and The Dsgm value is output.

Preferably, the error detector receives the Dsgm value of the integrator output, and calculates the error value Err of the received Dsgm value, the error detector inputs the error value Err to the data processor, and the data processor calculates the score according to the error value Err. The frequency division multiple of the frequency converter Fsel, and the frequency division multiple Fsel is sent to the frequency divider, the frequency divider divides the input signal Din according to the frequency division multiple Fsel, and outputs the clock signal CLK corresponding to the frequency to the error detector and the integrator And residual current detectors.

Preferably, the method for calculating the error value Err by the error detector comprises the steps of: averaging the recently received N Dsgm values to obtain an average value Dref, and then according to the formula Err=c*(Dsgm-Dref ), c is a constant, and the error value Err is calculated.

Preferably, the method for calculating the frequency division multiple Fsel by the data processor comprises the following steps: the data processor according to the formula Fsel=Fsel0+a*|Err|, Fsel0 is a positive constant, a is a positive coefficient, and the frequency division multiple is calculated. The value of Fsel. Fsel linearly adjusts the divider output frequency. Linear algorithm, the smaller the error Err corresponds to the smaller frequency divider output frequency, corresponding to the smaller circuit power consumption, but the slower the adjustment rate; the larger the error Err corresponds to the larger the frequency divider output frequency , corresponding to the larger circuit power consumption, but the faster the adjustment rate. The advantage is that the control is simple.

Preferably, the method for calculating the frequency division multiple Fsel by the data processor comprises the following steps: the data processor calculates a score according to the formula Fsel=Fsel0+b*e^|Err|, Fsel0 is a positive constant, and b is a positive coefficient. The value of the frequency multiple Fsel. The advantage of the exponential algorithm is that when the error |Err| is in a large range, the whole circuit works at a very low frequency, saving power and quiet; when the error is large, the Fsel is rapidly increased, the circuit operating frequency rises rapidly, and the circuit is adjusted. The rate increases rapidly while the power consumed by the circuit increases rapidly.

Preferably, the method for calculating the frequency division multiple Fsel by the data processor comprises the following steps: the data processor adopts a sigma-delta algorithm according to a first-order Z-domain expression: Fsel(Z)=Err(Z)+(1- 1/Z) *E(Z), E(Z) is the quantization noise, and the value of the frequency division multiple Fsel is calculated. The output of Fsel(Z) can be output to at least two states, which simplifies the design of the divider. The advantage of the algorithm using sigma-delta is that it can simplify the design of the frequency divider. The disadvantage is that quantization noise is introduced, but the sigma-delta algorithm itself can push the noise to the high frequency end, so that the power is coupled into the system through the substrate coupling. Noise near the signal frequency point is negligible.

The substantial effect of the invention is that the power consumption of the digital output buffer is effectively reduced, and the digital output buffer has strong anti-interference ability, and the circuit noise of the residual current high-frequency oscillation in the inductor L is avoided.

DRAWINGS

1 is a block diagram of a circuit principle connection of the present invention;

2 is a schematic structural view of an error detector;

Figure 3 is a flow chart of the operation of the present invention;

4 is a timing chart of control signals for one duty cycle of the present invention.

In the figure: 1, timing generator, 2, integrator, 3, residual current detector, 4, energy storage, 5, error detector, 6, data processor, 7, frequency divider, 8, error operator 9, dynamic reference generator.

detailed description

The technical solutions of the present invention will be further specifically described below by way of embodiments and with reference to the accompanying drawings.

Embodiments: The present invention provides a digital output buffer, as shown in FIG. 1, which includes a timing generator 1, an integrator 2, a residual current detector 3, an energy storage device 4, an error detector 5, and a data processor. 6. Frequency divider 7, inductor L, load capacitor CL, first switch tube SW1, second switch tube SW2 and third switch tube SW3, one end of the energy storage device 4 is grounded, the other end of the energy storage device 4 and the third switch tube The first conductive end of the SW3 is electrically connected, and the second conductive end of the third switch SW3 is electrically connected to one end of the inductor L. The other end of the inductor L and the upper plate of the load capacitor CL and the first guide of the first switch SW1 The first end of the second switch tube SW2 is electrically connected, the second end of the capacitor CL and the second end of the second switch SW2 are grounded, and the second end of the first switch SW1 is The power supply VDD is electrically connected, and the control end of the first switch SW1, the control end of the second switch SW2, and the control end of the third switch SW3 are electrically connected to the timing generator 1, respectively, and the two detecting ends of the residual current detector 3 Connected to the first conductive end and the second conductive end of the third switch SW3, respectively, and the output of the residual current detector 3 The terminal is electrically connected to the input of the integrator 2, the output of the integrator 2 is electrically connected to the second input of the timing generator 1 and the input of the error detector 5, and the first input of the timing generator 1 is a digital output. The signal input end of the buffer, the output of the error detector 5 is electrically connected to the input of the data processor 6, the output of the data processor 6 and the frequency divider 7 The second output terminal is electrically connected, the first input end of the frequency divider 7 is electrically connected to the first input end of the timing generator 1, the output end of the frequency divider 7 and the clock signal input end of the error detector 5, and the integrator The clock signal input terminal of 2 is electrically connected to the clock signal input terminal of the residual current detector 3.

The energy storage device, the inductor L, the load capacitor CL, the first switch tube SW1, the second switch tube SW2 and the third switch tube SW3 constitute a main circuit of the digital output buffer, and its function is to control the first switch tube SW1 The second switch tube SW2 and the third switch tube SW3 control the LC oscillation to carry the charge on the accumulator to the load capacitor CL non-destructively according to the input signal Din, or to transfer the charge on the CL to the storage signal Din without loss according to the input signal Din. On the energy device, the output from the low level to the high level and the high level to the low level can be realized at the output port Dout. The accumulator is a capacitor. The first switch tube SW1 and the second switch tube SW2 enhance the level of the digital output port Dout, and maintain Dout at a low level of low resistance and a low level of low resistance.

As shown in Figure 4, during the transition of the input signal Din from low to high, and then from high to low, the digital output buffer operates as T1, T2, T3, and T4. In four stages, the timing generator controls the first switching transistor SW1, the second switching transistor SW2, and the third switching transistor SW3 to operate.

When the input signal Din transitions from a high level to a low level, the T3 interval is entered, the third switch tube SW3 is turned on, and the first switch tube SW1 and the second switch tube SW2 are turned off. The charge on the load capacitor CL is recovered by the accumulator via the inductor L and the third switch SW3. In this process, the voltage on the load capacitor CL oscillates freely from VDD to 0, and the current in the inductor L increases from 0 to the maximum point and then returns to 0.

The durations of the T1 phase and the T3 phase are the same, both being time T. The timing generator takes the time value corresponding to the Dsgm value of the latest received integrator output as the value of the time T. The integrator output Dsgm value includes the following steps: the integrator pre-sets an initial value to Dsgm, the initial value corresponds to a T time value, and the residual current detector detects when the timing generator controls the third switch tube SW3 to turn on T time. Residual current to inductor L, output Dcmp value to integrator, Dcmp The value reflects the direction of the residual current, or the direction and magnitude of the residual current of the Dcmp value. The integrator integrates the initial value of Dsgm and the received Dcmp value to obtain the latest Dsgm value, and outputs the Dsgm value to the timing generator. The timing generator determines a corresponding time value according to the received Dsgm value, and uses the time value as the value of the time T.

The error detector, data processor, and divider form another negative feedback circuit for the digital output buffer. The error detector receives the Dsgm value of the integrator output, and calculates the error value Err of the received Dsgm value, the error detector inputs the error value Err to the data processor, and the data processor calculates the frequency divider based on the error value Err The frequency division multiple Fsel is sent to the frequency divider multiplier, and the frequency divider divides the input signal Din according to the frequency division multiple Fsel, and outputs the clock signal CLK corresponding to the frequency to the error detector, the integrator and the residual current. detector. The residual current detector and integrator are both triggered by the clock signal CLK. If the clock signal CLK is always operating at the highest frequency, then the entire circuit consumes a large amount of power. If the clock signal CLK is always operating at the lowest frequency, the overall circuit has weak anti-interference ability and the corresponding speed is slow. The negative feedback circuit consisting of error detector, data processor and frequency divider makes the digital output buffer save power and has strong anti-interference ability.

As shown in FIG. 2, the error detector 5 comprises an error operator 8 and a dynamic reference generator 9, the input of the dynamic reference generator 9 being electrically connected to the output of the integrator 2, the output of the dynamic reference generator 9 and the error The first input end of the arithmetic unit 8 is electrically connected, the second input end of the error computing unit 8 is electrically connected to the output end of the integrator 2, and the output end of the error computing unit 8 is electrically connected to the input end of the data processor 6, and the error operation The clock signal input of the device 8 and the clock signal input of the dynamic reference generator 9 are electrically connected to the output of the frequency divider 7. Dynamic reference generator 9 based on input The characteristic of the Dsgm value extracts the reference signal information Dref, which reflects the time information of the current zero crossing on the inductor L, which is compared with the Dsgm value to generate an output error value Err.

The present invention provides a digital output buffer control method suitable for the above-described digital output buffer, which comprises the following steps:

The charge stored in the accumulator is supplied to the inductor L via the third switch SW3. Since the inductor L and the load capacitor CL form a series resonant circuit, the load capacitor CL is charged with a voltage due to resonance, and the voltage of the upper plate can be freely oscillated to VDD. In this process, the current in the inductor L increases from 0 to the positive direction. After reaching the peak value, the voltage of the plate on the load capacitor CL oscillates to the highest point, and the current in the inductor L returns to zero.

The power supply VDD is boosted to the upper plate of the load capacitor CL through the first switch SW1, the voltage of the upper plate of the load capacitor CL reaches VDD, and the output port Dout outputs a high level.

The charge on the load capacitor CL is recovered by the accumulator via the inductor L and the third switch SW3. In this process, the voltage on the load capacitor CL oscillates freely from VDD to 0, and the current in the inductor L increases from 0 to the maximum point and then returns to 0.

The upper plate of the load capacitor CL is reinforced to GND via the second switch SW2, and the output port Dout outputs a low level.

The error detector receives the Dsgm value of the integrator output, and calculates the error value Err of the received Dsgm value, the error detector inputs the error value Err to the data processor, and the data processor calculates the frequency divider based on the error value Err The frequency division multiple Fsel is sent to the frequency divider multiplier, and the frequency divider divides the input signal Din according to the frequency division multiple Fsel, and outputs the clock signal CLK corresponding to the frequency to the error detector, the integrator and the residual current. detector.

The workflow of the digital output buffer is shown in Figure 3.

The error detector calculates the error value Err by the following steps: the error detector averages the recently received N Dsgm values to obtain an average value Dref, and then according to the formula Err=c*(Dsgm-Dref), c is a constant , the error value Err is calculated.

The method for calculating the frequency division multiple Fsel by the data processor includes the following steps: the data processor calculates the value of the frequency division multiple Fsel according to the formula Fsel=Fsel0+a*|Err|, Fsel0 is a positive constant, and a is a positive coefficient. Fsel linearly adjusts the divider output frequency. Linear algorithm, the smaller the error Err corresponds to the smaller frequency divider output frequency, corresponding to the smaller circuit power consumption, but the slower the adjustment rate; the larger the error Err corresponds to the larger the frequency divider output frequency , corresponding to the larger circuit power consumption, but the faster the adjustment rate. The advantage is that the control is simple.

The data processor calculates the frequency division multiple Fsel by the following steps: the data processor according to the formula Fsel=Fsel0+b*e^|Err|, Fsel0 is a positive constant, b is a positive coefficient, and the frequency division multiple is calculated. The value of Fsel. The advantage of the exponential algorithm is that when the error |Err| is in a large range, the whole circuit works at a very low frequency to save power and is quiet; when the error is large, the Fsel is rapidly increased, the circuit operating frequency rises rapidly, and the circuit adjustment rate The increase is fast, and the power consumed by the circuit increases rapidly.

The method of calculating the frequency division multiple Fsel by the data processor can also be implemented by the following steps: the data processor adopts the sigma-delta algorithm according to the first-order Z-domain expression: Fsel(Z)=Err(Z)+(1-1/ Z)*E(Z), E(Z) is the quantization noise, and the value of the frequency division multiple Fsel is calculated. The output of Fsel(Z) can be output to at least two states, which simplifies the design of the divider. The advantage of the algorithm using sigma-delta is that it can simplify the design of the frequency divider. The disadvantage is that quantization noise is introduced, but the sigma-delta algorithm itself can push the noise to the high frequency end, so that the power is coupled into the system through the substrate coupling. Noise near the signal frequency point is negligible.

Claims

A digital output buffer, comprising: a timing generator (1), an integrator (2), a residual current detector (3), an energy storage device (4), an inductance L, a load capacitance CL, a first The switch tube SW1, the second switch tube SW2 and the third switch tube SW3, one end of the energy storage device (4) is grounded, and the other end of the energy storage device (4) is electrically connected to the first conductive end of the third switch tube SW3. The second conductive end of the third switch SW3 is electrically connected to one end of the inductor L. The other end of the inductor L is connected to the upper plate of the load capacitor CL, the first conductive end of the first switch SW1, and the first end. The first conductive end of the second switch SW2 is electrically connected, the lower end of the capacitor CL and the second conductive end of the second switch SW2 are grounded, and the second conductive end of the first switch SW1 is The power supply VDD is electrically connected, and the control end of the first switch tube SW1, the control end of the second switch tube SW2, and the control end of the third switch tube SW3 are electrically connected to the timing generator (1), respectively, and the residual current detector The two detecting ends of (3) are respectively electrically connected to the first conducting end and the second conducting end of the third switching tube SW3, and the output end of the residual current detector (3) is The input of the divider (2) is electrically connected, the output of the integrator (2) is electrically connected to the second input of the timing generator (1), and the first input of the timing generator (1) is The signal input of the digital output buffer.
A digital output buffer according to claim 1, further comprising an error detector (5), a data processor (6) and a frequency divider (7), said integrator (2) The output is also electrically connected to the input of the error detector (5), the output of which is electrically connected to the input of the data processor (6), the output of the data processor (6) The terminal is electrically connected to the second output of the frequency divider (7), and the first input of the frequency divider (7) is electrically connected to the first input of the timing generator (1), the frequency divider ( 2) output and error The clock signal input end of the detector (5), the clock signal input end of the integrator (2) and the clock signal input end of the residual current detector (3) are electrically connected.
A digital output buffer according to claim 1 or 2, characterized in that the energy store (4) is a capacitor or a voltage source.
A digital output buffer control method, characterized in that it comprises the following steps:

S1: the timing generator reads the input signal Din, when the input signal Din jumps from a low level to a high level, then step S2 is performed, when the input signal Din jumps from a high level to a low level, then step S4 is performed;

S2: the timing generator controls the third switch tube SW3 to be turned on for T time, and controls the first switch tube SW1 and the second switch tube SW2 to be turned off for T time;

S3: At the end of the T time, the timing generator controls the first switch SW1 to be turned on, and controls the second switch SW2 and the third switch SW3 to be turned off;

S4: The timing generator controls the third switch tube SW3 to be turned on for T time, and controls the first switch tube SW1 and the second switch tube SW2 to be turned off for T time;

S5: At the end of the T time, the timing controller controls the second switch tube SW2 to be turned on, and controls the first switch tube SW1 and the third switch tube SW3 to be turned off;

The timing generator takes the time value corresponding to the Dsgm value of the newly received integrator output as the value of the time T, and the integrator output Dsgm value includes the following steps: the integrator pre-sets an initial value to the Dsgm, the initial value corresponding to a time value That is, the time value is the initial value of the time T. When the timing generator controls the third switch tube SW3 to turn on the T time, that is, when the third switch tube SW3 is turned off, the residual current detector detects the residual current in the inductor L. , output the Dcmp value to the integrator, the Dcmp value reflects the direction of the residual current, or the Dcmp value reflects the residual current. Towards and size, the integrator integrates the initial value of Dsgm and all received Dcmp values to obtain the latest Dsgm value, and outputs the Dsgm value.
A digital output buffer control method according to claim 4, further comprising the steps of: the error detector receiving the Dsgm value of the integrator output, and calculating the error value Err of the received Dsgm value, The error detector inputs the error value Err to the data processor, and the data processor calculates the frequency division multiple Fsel of the frequency divider according to the error value Err, and sends the frequency division multiple Fsel to the frequency divider, and the frequency divider is divided according to the frequency division multiple. Fsel divides the input signal Din and outputs a clock signal CLK corresponding to the frequency to the error detector, the integrator, and the residual current detector.
A digital output buffer control method according to claim 5, wherein said error detector calculates a value of error value Err comprising the steps of: averaging the most recently received N Dsgm values by the error detector The average value Dref is obtained, and then the error value Err is calculated according to the formula Err=c*(Dsgm-Dref), and c is a constant.
A digital output buffer control method according to claim 5 or 6, wherein the method for calculating the frequency division multiple Fsel by the data processor comprises the following steps: the data processor according to the formula Fsel=Fsel0+a* |Err|, Fsel0 is a positive constant, a is a positive coefficient, and the value of the frequency division multiple Fsel is calculated.
A digital output buffer control method according to claim 5 or 6, wherein the method for calculating the frequency division multiple Fsel by the data processor comprises the following steps: the data processor according to the formula Fsel=Fsel0+b* e^|Err|, Fsel0 is a positive constant, b is a positive coefficient, and the value of the frequency division multiple Fsel is calculated.
A digital output buffer control method according to claim 5 or 6, wherein the method for calculating the frequency division multiple Fsel by the data processor comprises the following steps: The processor uses the sigma-delta algorithm to calculate the score according to the first-order Z-domain expression: Fsel(Z)=Err(Z)+(1-1/Z)*E(Z), E(Z) is the quantization noise. The value of the frequency multiple Fsel.