CN1638283A - Single crystal vibrator digital phase-locked loop device realizing E1T1 debouncing - Google Patents

Abstract

The present invention provides a single crystal oscillator digital phase-locked loop device that realizes E1T1 dejittering, including FIFO, read and write pointer comparison circuit, register 1, subtractor, adder, register 2, E1/T1 frequency division circuit; also includes E1/T1 T1 memory stores the reference value of E1/T1; E1/T1 selector selects the reference value of E1 or T1 and sends it to the subtractor. Since the present invention only needs to use one crystal oscillator, E1T1 adopts the same control circuit, which can not only debounce E1 but also T1, thereby reducing the capacity of the chip and reducing the cost.

Description

Single Crystal Oscillator Digital Phase-Locked Loop Device Realizing E1T1 Dejitter

technical field

The present invention relates to an optical synchronous digital transmission system (abbreviated as SDH/SONET), and specifically relates to a single-crystal oscillator digital phase-locked loop device for 2M/1.5M PDH interface to realize E1T1 dejittering.

Background technique

When VC4 receives it, it is decomposed into 63 TU12 and 84 TU11 signals. To get a pure 2M/1.5M signal, the overhead and stuffing bytes must be removed, and there may be pointer adjustments in the transmission TU12/TU11 , so the demapped 2M/1.5M signal has a gap, if it is directly output to the PDH end, it will cause a lot of jitter. The G.783 protocol has a jitter index limit for the 2M/1.5M PDH interface. The de-jittering method adopted in the mapping chip is a combination of de-leakage circuit and digital phase-locked loop (DPLL). When the transmitted signal contains two data streams, it is necessary to debounce the two data streams. Through searching, it is found that many patents use a set of debounce circuits for each of the two data streams, and use two crystal oscillators. For example, US Patent No. 5,289,507, as shown in Figure 3, uses a 44.736M crystal oscillator. For T1, 5 times of 28, 188 times of 29 frequency division, the times are evenly distributed in one frame, and increase or decrease according to the FIFO depth. US Patent 5297180 uses a 58.32M crystal oscillator as shown in Figure 4, and performs 28/29 frequency division for E1. The 28/29 frequency division is controlled by adding the difference between the 17-bit constant and the FIFO depth, and selecting according to the carry value. . The two patents use different crystal oscillators and different control circuits for E1/T1, so that the chip with more circuits will increase the capacity, and at the same time, because there are two crystal oscillators, the cost will be increased. The present invention is modified from the original US Patent No. 5,297,180, so that it can be applied to both E1 and T1.

Contents of the invention

The purpose of the present invention is to provide a circuit capable of de-jittering both E1 and T1 by using only one crystal oscillator, thereby reducing the chip capacity and cost.

In order to achieve the above object, the present invention proposes a single crystal oscillator digital phase-locked loop device that realizes E1T1 dejittering, including:

FIFO, which stores input data and is read out by the output clock;

Read and write pointer comparison circuit, the E1/T1 data stream is used as the write clock, the read clock is 58.32M crystal oscillator obtained through the E1T1 frequency division circuit, and the read and write pointers are subtracted to obtain the read and write rate difference;

Register 1 stores the value obtained by the read-write pointer comparison circuit and the remainder of the E1T1 frequency division circuit;

The subtractor selects the reference value of E1/T1 through the selector and subtracts the data value in register 1;

An adder, which adds and calculates the difference of the subtractor;

Register 2, which stores the sum data given by the adder;

E1/T1 frequency division circuit, frequency division of E1/T1 signal;

Also includes:

E1/T1 memory, storing E1/T1 reference value;

The E1/T1 selector selects the reference value of E1 or T1 and sends it to the subtractor.

Therefore, the remarkable effect of the present invention is that only one crystal oscillator is used, and the E1T1 uses the same control circuit, thereby reducing the capacity of the chip and reducing the cost at the same time.

Description of drawings

Fig. 1 the present invention realizes the circuit block diagram of the single crystal oscillator digital phase-locked loop device of E1T1 dejitter;

Fig. 2 E1T1 frequency division flow chart of the present invention;

The circuit block diagram of Fig. 3 US Patent No. 5,289,507;

Fig. 4 is a circuit block diagram of US Patent 5,297,180.

Detailed ways

E1T1 is a slow data stream. In order to ensure the uniformity of the output clock, a high-speed clock must be used for frequency division. The present invention uses a 58.32M crystal oscillator. However, there will always be a deviation between the input rate and the output rate. In order to ensure the correctness of the data flow, FIFO must be used to absorb the gap between the two sides. At the same time, the deviation between the input and output data streams can be known through the difference between the read and write pointers. And pass it to the frequency division circuit to adjust the ratio of frequency division. By giving the difference between the reference value of E1 and T1 under the 58.32M crystal oscillator and the input data of the 11BIT register, and adding the difference every E1/T1 cycle in a multi-frame time, the output clock is adjusted according to the carry value Frequency of. Each circuit is described in detail below.

As shown in Figure 1, the input LEAKDATA LEAKCLK is the jittered E1T1 data and clock signal, the output RCLK is the frequency-divided clock, and RDNRZ is read on the rising edge of RCLK. This phase-locked loop circuit is to track the input data stream and obtain the E1T1 data stream whose output jitter is within the specified range.

Circuit 1 in Fig. 1 includes FIFO, read and write pointers count, and read and write pointers subtract. FIFO depth can be set to 96BITS, and is set to 48BITS (0110, 0000) when resetting. Selecting 96BITS is to prevent FIFO from overflowing. The 64BITS in the original patent 5297180 will cause FIFO to overflow.

When the write clock is faster than the read clock, the FIFO depth is greater than 48BITS. When the write clock is slower than the read clock, the FIFO depth is less than 48BITS. This circuit obtains the difference between the input and output data stream rates through the difference between the read and write pointers, and uses the difference The value is sent to the 11BIT register. The write pointer increases with the change of the input data stream, because the output data stream is obtained by frequency division of a high-frequency clock. In order to ensure the correctness of the FIFO depth calculation, a high-speed clock is used to synchronize the input data.

The upper seven bits of 11BIT REGISTER store the difference between read and write pointers, and the lower four bits store the value calculated by the frequency division circuit when the multiframe arrives. The change frequency of the 11BIT register is a multiframe period, that is, the speed difference between the input and output data streams within a multiframe period is sampled.

18BITS subtractor, the minuend is a fixed value. E1 is 0111101_0110000_0000, and T1 is 11000110_011000_1100. This reference value is to obtain the standard E1, T1 signal, that is, the 58.32M crystal oscillator, respectively, the proportion value of 28/29, 37/38 frequency division and the FIFO depth is half full, and the remainder of the frequency division circuit is 0. Phase combination value.

For E1, to obtain a uniform E1 clock, 58.32M must be divided by 28/29, and 58.32/2.048=28.4765625. It must be divided by 29 for 47.65625%, and divided by 28 for 52.34375%. The calculation is as follows: 58.32/(28*0.5234375+29*0.4765625)=2.048. 0.4765625 converted into binary is 0111101, 0111101 is used as the benchmark parameter, 0110000 corresponds to the half-full state of the FIFO depth, that is, the reading and writing pointer rates are equal. When the read and write pointers are equal, the data input by 11BITS is 0110000_0000, and the difference of the corresponding 18BITS subtractor is 0111101_0000000_0000. At this time, dividing by 29 accounts for 47.65625%, and dividing by 28 accounts for 52.34375. When the write clock is faster than the read clock, the FIFO depth is greater than The difference between the 48BITS and 18BITS subtractors is smaller than the above difference, correspondingly, the reading clock is required to be accelerated, and the times of dividing by 28 are increased.

The circuit 2 in Fig. 1 completes the above work. When the write clock is slower than the read clock, the FIFO depth is less than 48BITS, and the difference of the 18BITS subtractor is greater than the above difference, correspondingly requiring the read clock to slow down, and the number of times divided by 29 increases. When the lowest four bits 0000 correspond to the arrival of the multiframe, the frequency division circuit just starts. These four bits serve as fine-tuning parameters.

For T1, to get a uniform T1 clock, 58.32M must be divided by 37/38. And 58.32/1.544 = 37.772020725388601036269430051813. It can be seen that there are more mantissa bits, but since the adder only has 18 bits at most (too many will increase the capacity). You can calculate the rate of the data stream obtained by frequency division after 18 bits. The 18-bit binary number is int(0.772020725388601036269430051813×2 ¹⁸ )=110001_01101000_1100. And this 18-bit binary number corresponds to 0.7720184326171875. Divided by 38 is 0.7720184326171875, divided by 37 is 0.2279815673828125. The rate after frequency division is 58.32/(38*0.7720184326171875+37*0.2279815673828125)=1.5440000937212044. The difference with 1.544 is relatively small. Therefore, the 18-bit BITS number in the case of T1 is 110001_01101000_1100+0110000_0000=h'3198c. Same as E1, when the read and write pointers are equal, the data input by 11BITS is 0110000_0000, and the difference of the corresponding 18BITS subtractor is 110001_01101000_1100. At this time, dividing by 38 is 0.7720184326171875, and dividing by 37 is 0.2279815673828125. When the write clock is faster than the read clock , the FIFO depth is greater than 48BITS, and the difference of the 18BITS subtractor is smaller than the above difference, correspondingly, the reading clock is required to be accelerated, and the number of times of dividing by 37 is increased. Circuit 2 in Figure 1 does this. When the write clock is slower than the read clock, the FIFO depth is less than 48BITS, and the difference of the 18BITS subtractor is greater than the above difference, correspondingly requiring the read clock to slow down, and the number of times divided by 38 increases.

The circuit 2 in Fig. 1 completes the proportional frequency division, which is composed of 18BITS adder and frequency division circuit. The 18BITS adder adds and calculates the difference of the input 18BITS subtractor according to the frequency of E1/T1, and the value of the sum is sent to the 18BIT register, and the carry value is sent to the frequency division circuit. When the carry value is 1, for E1, Divide by 29, and for T1, divide by 38. When the write clock is faster than the read clock, the FIFO depth increases, the value of the 11BITS register increases, the value of the 18BITS subtractor decreases, and the case where the addition calculation is 1 is reduced. For E1, the case of dividing by 28 is reduced and divided by 27. As the number of cases increases, the write clock rate of the corresponding output increases. Since E1T1 has the same function in the 18BITS adder, the circuit can be shared.

The frequency division circuit selectively divides the frequency according to the carry value sent by the 18BITS adder. E1 counts up to 29, T1 counts up to 38, and their counters can be shared. In order to ensure that the duty cycle of the output clock is 50%, it can be designed according to Figure 2. The initial value of E1 is set to 2, the initial value of T1 is set to 13, the counter is 6 bits, and the output clock of E1 is the output of the 5th bit of the counter. The output clock of T1 is the output of the 6th bit of the counter. For E1, the initial value is 000010, count to 16 (1_0000), the 5th bit jumps, the output read clock is high, when the count reaches 30 and the carry value is 1, the counter is initialized to 2, and the 5th bit jumps again change, the output read clock is low, thus outputting the E1 read clock with a duty cycle of 50%. For T1, the initial value is 001101, counting to 32 (100000), the 6th bit jumps, the output read clock is high, when the count reaches 50 and the carry value is 1, the counter is initialized to 13, and the 6th bit jumps again change, the output read clock is low, thus outputting the T1 read clock with a duty cycle of 50%.

Can find out from above, except adding E1/T1 memory, E1/T1 selector among the present invention, all the other circuits can be shared, select E1, T1 reference value according to E1T1 selection signal, greatly reduced the capacity of chip.

Claims (9)

1. realize that E1T1 removes the single crystal oscillator digital phase-locked loop device of shaking, and comprising for one kind:

FIFO, storage input data are output clock and read;

Read-write pointer comparison circuit, the E1/T1 data flow is as writing clock, and reading clock is that the 58.32M crystal oscillator draws by the E1T1 frequency dividing circuit, and the read-write pointer subtracts each other and obtains reading and writing speed difference;

Register 1, resulting value of storage read-write pointer comparison circuit and E1T1 frequency dividing circuit remainder;

Subtracter is selected the E1/T1 fiducial value by selector, deducts the data value in the register 1;

Adder is carried out additional calculation to the difference of subtracter;

Register 2, the storage adder provides and data;

The E1/T1 frequency dividing circuit carries out frequency division to the E1/T1 signal;

It is characterized in that also comprising:

The E1/T1 memory, storage E1/T1 fiducial value;

The E1/T1 selector selects the fiducial value of E1 or T1 to flow to subtracter.

2. the E1T1 that realizes according to claim 1 removes the single crystal oscillator digital phase-locked loop device of shaking, and it is characterized in that described register 1 is the 11BIT register.

3. the E1T1 that realizes according to claim 2 removes the single crystal oscillator digital phase-locked loop device of shaking, and it is characterized in that described 11BIT register, high seven storage read-write pointer differences, the value that frequency dividing circuit was calculated when low four storage multi-frames arrived.

4. the E1T1 that realizes according to claim 1 removes the single crystal oscillator digital phase-locked loop device of shaking, and it is characterized in that described subtracter is the 18BIT subtracter.

5. the E1T1 that realizes according to claim 1 removes the single crystal oscillator digital phase-locked loop device of shaking, and it is characterized in that described adder is the 18BIT adder.

6. the E1T1 that realizes according to claim 1 removes the single crystal oscillator digital phase-locked loop device of shaking, and it is characterized in that described register 2 is the 18BIT register.

7. the E1T1 that realizes according to claim 1 removes the single crystal oscillator digital phase-locked loop device of shaking, and it is characterized in that the described FIFO degree of depth is set to 96BITS, is set to 48BITS when resetting.

8. the E1T1 that realizes according to claim 1 removes the single crystal oscillator digital phase-locked loop device of shaking, and it is characterized in that described E1 fiducial value is 0111101_0110000_0000, and the T1 fiducial value is 11000110_011000_1100.

9. the E1T1 that realizes according to claim 1 removes the single crystal oscillator digital phase-locked loop device of shaking, and it is characterized in that: the external crystal-controlled oscillation of described E1/T1 frequency dividing circuit is 58.32M, and E1 is carried out 28/29 frequency division, and T1 is carried out 37/38 frequency division.

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