CN116827870A - Clock transparent transmission device, method and optical transmission network equipment - Google Patents

Abstract

The disclosure provides a clock transparent transmission device, a clock transparent transmission method and optical transmission network equipment, and relates to the technical field of optical networks. A clock transparent device of the present disclosure, comprising: an ingress rate statistics module configured to count ingress rates of data streams from the traffic source based on the local clock and update the ingress rates at a predetermined first frequency; the buffer module is configured to buffer data of the data stream and determine the occupied buffer space amount; the clock determining module is configured to multiply frequency by taking the local crystal as a reference clock to obtain a frequency-multiplied clock; the output rate control module is configured to read the data buffered by the buffer memory module, copy the buffered data bit by bit based on the frequency multiplication clock and output, wherein the number of times of copying is dynamically adjusted according to the input rate and the occupied buffer memory space amount rate.

Description

Clock transparent transmission device, method and optical transmission network equipment

Technical Field

The disclosure relates to the technical field of optical networks, in particular to a clock transparent transmission device, a clock transparent transmission method and optical transmission network equipment.

Background

In the field of optical fiber communication, an original SDH system is used as a main body and gradually evolved to an OTN technical system, and an OTN optical transport network has the capability of bearing multiple services such as Ethernet, SDH, E1 and the like.

Because the optical interface in the SDH communication system is required to have a clock frequency transparent transmission function, in order to meet the function of clock frequency transparent transmission on the SDH optical interface, the current mainstream OTN equipment manufacturers use a special clock chip to provide a reference clock for SERDES of the SDH optical interface, and then provide the clock transparent transmission function of the SDH interface. Because the source and the destination of each SDH optical interface service carried are different, each SDH optical interface carried needs a special clock chip to track the clock frequency of the service source. When the number of the carried SDH optical interfaces is large, the number of special clock chips needed to be used in the hardware system is large, so that the cost of the OTN equipment of the access layer is obviously increased.

Disclosure of Invention

An object of the present disclosure is to provide a method for implementing a clock frequency transparent transmission function of an optical interface, reducing the dependency on a dedicated clock chip, and reducing the cost of OTN equipment.

According to an aspect of some embodiments of the present disclosure, there is provided a clock transparent device, including: an ingress rate statistics module configured to count ingress rates of data streams from the traffic source based on the local clock and update the ingress rates at a predetermined first frequency; the buffer module is configured to buffer data of the data stream and determine the occupied buffer space amount; the clock determining module is configured to multiply frequency by taking the local crystal as a reference clock to obtain a frequency-multiplied clock; the output rate control module is configured to read the data buffered by the buffer memory module, copy the buffered data bit by bit based on the frequency multiplication clock and output, wherein the number of times of copying is dynamically adjusted according to the input rate and the occupied buffer memory space amount rate.

In some embodiments, the exit rate control module is configured to: determining the value of the token bucket according to the read data quantity, the occupied cache space quantity in the cache module and the entry rate acquired by the entry rate statistics module; determining the number of replications according to the value of the token bucket, wherein: in the case that the value of the token bucket is smaller than a predetermined low threshold, the number of copies is a first number of copies; the number of copies is a second copy number in case the value of the token bucket is greater than a predetermined high threshold; the number of copies is the initial number of copies when the value of the token bucket is less than or equal to a predetermined high threshold value and greater than or equal to a predetermined low threshold value; the first number of copies > the initial number of copies > the second number of copies.

In some embodiments, the first number of copies is 1 greater than the initial number of copies and the second number of copies is 1 less than the initial number of copies.

In some embodiments, the exit rate control module is configured to: initializing a token bucket to a predetermined initial value; increasing the entry rate counted by the entry rate counting module in the token bucket according to a preset second frequency; each time bit data is read from the cache module, the numerical value of the token bucket is reduced by less preset deduction values; and if the occupied buffer space amount is larger than a preset first threshold value or the occupied buffer space amount is smaller than a preset second threshold value, setting the token bucket as a preset initial value.

In some embodiments, the exit rate control module is further configured to: if the occupied buffer space amount is larger than a preset first threshold value, continuously reading the buffer data until the occupied buffer space amount is a preset standard value; and if the occupied amount of the buffer space is smaller than the preset second threshold value, stopping reading the buffer data until the occupied amount of the buffer space is a preset standard value.

In some embodiments, the apparatus conforms to at least one of: the clock determination module is configured to operate in STM-64 mode; the data bus bit width of the clock determining module and the outlet rate control module is 32 bits; the entry rate statistics module is configured to count the total amount of effective data sent to the write interface of the cache module in a predetermined time, continuously count the total amount of effective data for a predetermined number of times, and then obtain an average value to determine an entry rate.

In some embodiments, the clock transparent device operates in STM-1 mode, the buffer depth of the buffer module is 64, the bit width is 1 bit, the initial copy number is 63, the data amount of one bit read from the buffer module at a time is 1 bit, and the predetermined deduction value is 1.

In some embodiments, the clock transparent device operates in STM-4 mode, the buffer depth of the buffer module is 64, the bit width is 4 bits, the initial copy number is 15, the data amount of one bit read from the buffer module is 4 bits each time, and the predetermined deduction value is 4.

In some embodiments, the apparatus further comprises: and the mode adjustment module is configured to switch the working modes of the clock transparent transmission device, wherein the working modes comprise STM-1 and STM-4.

In some embodiments, the clock determination module is a Serdes TX module comprising an input interface, an output interface, a reference clock receiving interface, and a multiplied clock output interface, wherein: the reference clock receiving is connected with the crystal oscillator and is configured to acquire a reference clock; the frequency multiplication clock output interface is connected with the exit rate control module and the buffer module and is configured to output a frequency multiplication clock; the input interface is connected with the output rate control module and is configured to acquire the copied data stream output by the output rate control module; the output interface is configured to output the data stream according to an operating mode of the clock-transparent device in accordance with the data stream from the input interface.

In some embodiments, the buffer module is a FIFO module, including a write-side clock interface, a read-side clock interface, a buffer input interface, a buffer output interface, and an occupied buffer space amount output interface, where: the write side clock interface is connected with the clock output interface of the OTN device and is configured to write the data stream into the buffer memory based on the clock output by the OTN device; the read side clock interface is connected with the frequency multiplication clock output interface of the clock determining module and is configured to output cached data based on the frequency multiplication clock output by the clock determining module; the cache input interface is configured to receive an input data stream; the cache output interface is configured to output the cached data to the egress rate control module; and the occupied amount of buffer space output interface is configured to output the occupied amount of buffer space to the egress rate control module.

In some embodiments, the exit rate control module includes: the device comprises a frequency multiplication clock input interface, an occupied buffer space input interface, an entry rate input interface, a buffer reading interface and a data output interface, wherein: the frequency multiplication clock input interface is connected with the frequency multiplication clock output interface of the clock determination module and is configured to receive the frequency multiplication clock; the occupied cache space input interface is connected with the occupied cache space output interface of the cache module and is configured to acquire the occupied cache space amount; the ingress rate input interface is configured to interface with the ingress rate statistics module and is configured to receive an ingress rate; the cache reading interface is configured to be connected with a cache output interface of the cache module and configured to read data cached in the cache module; the data output interface is connected with the input interface of the clock determining module and is configured to output the data after the bitwise copying to the clock determining module.

According to an aspect of some embodiments of the present disclosure, an optical transport network device is provided, including any one of the clock transparent transmission apparatuses above.

According to an aspect of some embodiments of the present disclosure, a clock transparent method is provided, including: counting an ingress rate of a data stream from a traffic source based on a local clock and updating the ingress rate at a predetermined first frequency; caching data of the data stream and determining an amount of occupied cache space; taking the local crystal as a reference clock to carry out frequency multiplication to obtain a frequency multiplication clock; and reading the data cached by the cache module, copying the cached data bit by bit based on the frequency multiplication clock, and outputting, wherein the copying times are dynamically adjusted according to the entry rate and the occupied cache space amount rate.

In some embodiments, reading the data buffered by the buffer module and copying the buffered data bit by bit based on the multiplied clock and outputting the buffered data includes: determining the value of the token bucket according to the read data quantity, the occupied cache space quantity in the cache module and the entry rate acquired by the entry rate statistics module; determining the number of replications according to the value of the token bucket, wherein: in the case that the value of the token bucket is smaller than a predetermined low threshold, the number of copies is a first number of copies; the number of copies is a second copy number in case the value of the token bucket is greater than a predetermined high threshold; the number of copies is the initial number of copies when the value of the token bucket is less than or equal to a predetermined high threshold value and greater than or equal to a predetermined low threshold value; the first replication times > the initial replication times > the second replication times; and according to the copying times, the buffered data is copied bit by bit based on the frequency multiplication clock and then output.

In some embodiments, determining the value of the token bucket based on the amount of data read, the amount of buffer space occupied in the buffer module, and the entry rate obtained by the entry rate statistics module comprises: initializing a token bucket to a predetermined initial value; increasing the entry rate counted by the entry rate counting module in the token bucket according to a preset second frequency; each time bit data is read from the cache module, the numerical value of the token bucket is reduced by a preset deduction value; and if the occupied buffer space amount is larger than a preset first threshold value or the occupied buffer space amount is smaller than a preset second threshold value, setting the token bucket as a preset initial value.

In some embodiments, reading the data buffered by the buffer module, and copying the buffered data bit by bit based on the multiplied clock, and outputting the buffered data further comprises: if the occupied buffer space amount is larger than a preset first threshold value, continuously reading the buffer data until the occupied buffer space amount is a preset standard value; and if the occupied amount of the buffer space is smaller than the preset second threshold value, stopping reading the buffer data until the occupied amount of the buffer space is a preset standard value.

In some embodiments, the method further comprises: the current operating mode is switched, the operating modes including STM-1 and STM-4.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate and explain the present disclosure, and together with the description serve to explain the present disclosure. In the drawings:

fig. 1 is a schematic diagram of some embodiments of a clock transparent device of the present disclosure.

Fig. 2 is a schematic diagram of further embodiments of a clock transparent device of the present disclosure.

Fig. 3A-C are schematic diagrams of some embodiments of a buffer module in a clock transparent device of the present disclosure.

Fig. 4A-B are schematic diagrams of some embodiments of an exit rate control module in a clock pass-through device of the present disclosure.

Fig. 5 is a schematic diagram of some embodiments of a clock determination module in a clock pass-through device of the present disclosure.

FIG. 6 is a schematic diagram of some embodiments of traffic egress rate adjustment in STM-1 mode for a clock transparent device of the present disclosure.

Fig. 7 is a schematic diagram of some embodiments of an optical transport network device of the present disclosure.

Fig. 8 is a schematic diagram of some embodiments of downstream data transmission over an optical transport network of the present disclosure.

Fig. 9 is a flow chart of some embodiments of a clock pass-through method of the present disclosure.

Detailed Description

The technical scheme of the present disclosure is described in further detail below through the accompanying drawings and examples.

A schematic diagram of some embodiments of a clock transparent device 10 of the present disclosure is shown in fig. 1.

The ingress rate statistics module 101 is capable of counting ingress rates of data streams from traffic sources based on a local clock and updating the ingress rates at a predetermined first frequency. In some embodiments, the ingress rate statistics module 101 counts the total amount of valid data sent to the write interface of the cache module for a predetermined time, and obtains an average value after continuously counting a predetermined number of times, so as to determine the ingress rate. In some embodiments, the ingress rate statistics module 101 counts the ingress rate of the data stream from the service source in the current period as a real-time ingress rate in a predetermined period, and further averages the ingress rates obtained in a continuous predetermined number of periods to obtain the ingress rate, so as to avoid that the subsequent processing is affected by accidental changes of the ingress rate, and improve the running stability of the clock transparent transmission device. In some embodiments, the predetermined period may be 100ms and the consecutive predetermined number may be 16, i.e., 1600ms, updating the entry rate once.

The caching module 102 is capable of caching data of a data stream and determining an amount of cache space that is occupied. In some embodiments, the cache module 102 is a FIFO (First Input First Output, first-in first-out) memory. In some embodiments, when the clock transparent device is operating in STM-1 mode, the bit width of the FIFO memory is 1 bit; when the clock transparent device is operating in STM-4 mode, the bit width of the FIFO memory is 4 bits. In some embodiments, the cache module 102 is capable of outputting the amount of cache space that itself has occupied.

The clock determining module 103 can multiply the frequency by using the local crystal as a reference clock to obtain a multiplied frequency clock. In some embodiments, the clock determination module 103 may be a Serdes TX module, implemented by an FPGA design tool. In some embodiments, the operating rate of clock determination module 103 may be the rate corresponding to STM-64 mode, 9953.28Mbps. In some embodiments, the bit width of the data bus to which the clock determination module 103 is connected to the egress rate control module 104 may be 32 bits, and the clock frequency sent by the clock determination module 103 is 9953.28/32= 311.04MHz. In some embodiments, the clock determination module 103 multiplies the frequency by a phase-locked loop inside the clock determination module 103 with the local crystal as a reference clock, and uses the multiplied frequency as a processing clock of the egress rate control module 104 and a read side clock of the buffer module 102.

The output rate control module 104 can read the data buffered by the buffer module, copy the buffered data bit by bit based on the frequency multiplication clock, and output the buffered data, wherein the number of times of copying is dynamically adjusted according to the input rate and the occupied buffer space amount rate.

The device can copy the entry data stream bit by bit based on the frequency multiplication clock and then output the data stream, and the output rate can be finely adjusted along with the input rate through the change of the copy times, so that the dependence on a special clock chip is reduced, and the cost of OTN equipment is reduced.

In some embodiments, the exit rate control module 104 can determine the number of replications based on the mechanism of the token bucket. In some embodiments, the value of the token bucket may be determined according to the read data amount, the occupied buffer space in the buffer module, and the entry rate acquired by the entry rate statistics module, and further the number of copies may be determined according to the value of the token bucket, where: in the case that the value of the token bucket is smaller than a predetermined low threshold, the number of copies is a first number of copies; the number of copies is a second copy number in case the value of the token bucket is greater than a predetermined high threshold; the number of copies is the initial number of copies when the value of the token bucket is less than or equal to a predetermined high threshold value and greater than or equal to a predetermined low threshold value; the first number of copies > the initial number of copies > the second number of copies.

By the method, the number of the token bucket can be adjusted according to the read data quantity, the entry rate and the occupied buffer space based on the initial copy number, and then the copy number can be adjusted according to the number of the token bucket, so that the output rate of the data stream can be adjusted. In some embodiments, the first copy number is 1 greater than the initial copy number and the second copy number is 1 less than the initial copy number, so that the rate is finely adjusted and the accuracy of the adjustment is improved.

In some embodiments, when the clock transparent device is operated in STM-1 mode, the initial copy number is 63 (i.e. 64 times per 1 bit data transmission), then the first copy number is 64 (i.e. 65 times per 1 bit data transmission), and the second copy number is 62 (i.e. 63 times per 1 bit data transmission), so as to achieve sixty-four precision adjustment; when the clock transparent transmission device works in STM-1 mode, the initial copying times are 15 (namely 16 times of data transmission of every 1 bit), the first copying times are 16 (namely 17 times of data transmission of every 1 bit), and the second copying times are 14 (namely 15 times of data transmission of every 1 bit), so that adjustment of one sixteenth precision is realized. The clock transparent transmission device can adjust the output rate with the precision of sixty-four or sixteenth in the corresponding working mode, thereby realizing fine adjustment of the data transmission speed and reducing the data jitter while realizing clock transparent transmission.

In some embodiments, the adjustment operation of the exit rate control module to the token bucket may include initializing the token bucket to a predetermined initial value, thereby providing a reference point for control of the token bucket to facilitate subsequent determination of the change in the entry rate based on the absolute value of the token bucket.

In some embodiments, the adjustment operation of the exit rate control module to the token bucket may include: and increasing the entry rate counted by the entry rate counting module in the token bucket according to the preset second frequency, so that the entry rate can be intuitively reflected in the token bucket, and injection and deduction balance during deduction of the token are facilitated.

In some embodiments, the adjustment operation of the output rate control module to the token bucket may further include, for each time the bit data is read from the buffer module, reducing the value of the token bucket by a predetermined deduction value, so that the read and output data is intuitively reflected in the token bucket, and when the value of the token bucket is reduced to be lower than a predetermined low threshold value, reducing the sending speed of the output data, and by increasing the copy number, reducing the output number of the information quantity. Such a device can increase sensitivity to inlet rate variations and improve the timeliness of outlet rate adjustments. In addition, the token injection rule is to inject the bit number actually input by the SDH data stream once every certain period; the token deduction rule deducts the corresponding token every time 1 bit (or 4 bits) is read out from the FIFO, so that the balance between the injection and deduction of the token can be realized.

In some embodiments, the adjustment of the token bucket by the exit rate control module may further include setting the token bucket to a predetermined initial value if the amount of occupied buffer space is greater than a predetermined first threshold or the amount of occupied buffer space is less than a predetermined second threshold. In some embodiments, if the amount of occupied buffer space is greater than a predetermined first threshold, the egress rate control module continues to read the buffer data until the amount of occupied buffer space is a predetermined standard value; and if the occupied buffer space amount is smaller than the preset second threshold value, the exit rate control module stops reading the buffer data until the occupied buffer space amount is a preset standard value. The device can determine the size of the outlet rate relative to the inlet rate according to the change condition of the occupied buffer space, and effectively regulate the residual space of the buffer module by stopping the operations of reading and continuously reading the buffer data, so that the balance of the data quantity between the input and the output is ensured, and the running stability of the device is improved.

In some embodiments, the clock transparent device further comprises a mode adjustment module capable of switching an operating mode of the clock transparent device, the operating mode comprising STM-1 and STM-4. The device can improve compatibility, improves adaptability of the clock transparent transmission device to different OTN devices or application scenes, and is favorable for popularization and application.

A schematic diagram of further embodiments of the clock transparent device of the present disclosure is shown in fig. 2.

The service of STM-1 or STM-4 optical interface of source end enters OTN network to carry through AMP, BMP, GMP, and after reaching destination end to demap through corresponding mapping mode, the service flow enters clock transparent transmission processing device as shown in figure 2 to process. In the clock transparent processing apparatus, the ingress rate statistics module 201 performs rate statistics on the incoming STM-1/STM-4 traffic data stream. The traffic data stream is input to a buffer module, shown in fig. 2 as FIFO memory 202. The clock determination module is implemented by Serdes TX 203 on the FPGA chip. The Serdex TX 203 obtains a frequency-multiplied clock CLK311M04 by frequency-multiplication processing based on the reference clock Refclk generated by the crystal oscillator. The multiplied clock CLK311M04 is sent to the FIFO memory 202 and the egress rate control module 204 as the output side clock of the FIFO memory; the egress rate control module 204 reads the data buffered in the FIFO memory 202, copies the data based on the multiplied clock, and sends the data to the Serdes TX 203, which is sent through the Serdes TX high-speed interface.

The clock transparent transmission device in the embodiment allows the OTN equipment to realize the clock frequency transparent transmission function of a plurality of STM-1 and STM-4 optical interfaces under the condition that a special clock chip is not used, and ensures the index requirement of the SDH interface on clock frequency offset. When the device is assembled in the OTN access layer equipment which is very sensitive to the cost, especially when the number of STM-1 and STM-4 optical interfaces which need to be borne is 4 or 8, the number of saved special clock chips is 4 or 8, so that the product cost and the power consumption can be obviously reduced, and the competitiveness of the OTN access layer equipment is improved.

Schematic diagrams of some embodiments of a buffer module in a clock transparent device of the present disclosure are shown in fig. 3A-C.

In some embodiments, as shown in FIG. 3A, the cache module 320 includes a write side clock interface 321, a read side clock interface 323, a cache input interface 322, a cache output interface 324, and an occupied cache space amount output interface 325.

The write-side clock interface 321 is connected to a clock output interface of the OTN device, and is capable of writing the data stream into the buffer memory based on the clock output by the OTN device.

The read-side clock interface 323 is connected to the multiplied clock output interface of the clock determination module, and is capable of outputting buffered data based on the multiplied clock output by the clock determination module.

The cache input interface 322 is capable of receiving an incoming data stream.

The cache output interface 324 is coupled to the egress rate control module and is capable of outputting cached data to the egress rate control module, and in some embodiments, the output clock matches the multiplied clock input by the read side clock interface 323. In some embodiments, the buffer output interface 324 is 32 bits wide.

The occupied buffer space amount output interface 325 can output the occupied buffer space amount to the egress rate control module.

In the clock transparent transmission device in the above embodiment, the buffer module can buffer the input data stream and acquire the read-write side clock through different interfaces, so as to solve the problem of inconsistent read-write side clocks; the buffer memory module outputs the real-time occupied buffer memory space amount, so that the output rate control module refers to the information to control the copying times, and the purpose that the output rate is dynamically adjusted along with the service source is achieved.

In some embodiments, the buffer module may be a FIFO memory.

In some embodiments, in STM-1 mode, the FIFO memory is as shown in FIG. 3B, and after the traffic of the STM-1 optical interface of the source is demapped by AMP, BMP or GMP, the data is sent to the cache input interface DIN [0] of the FIFO memory. In some embodiments, the depth of the FIFO in STM-1 mode is 64, the bit width is 1 bit, and the data stream from DIN [0] is written sequentially into the FIFO memory. In some embodiments, the FIFO memory further comprises an input control interface WEN for controlling the on and off of the buffer input interface. In some embodiments, the write-side clock interface is connected to a demapping module of the OTN device, and obtains, as the write-side clock, the clock clk_otn sent from the OTN by the demapping module.

The read-side clock interface acquires the multiplied clock CLK311M04 output by the clock determination module as a read-side clock. The FIFO memory outputs the buffered data through the buffer output interface DOUT [0]. In some embodiments, the FIFO memory further comprises an output control interface REN for controlling the on and off of the buffer output interface. The output USED [5:0] on the read side of the FIFO represents the amount of memory space USED in the FIFO and is sent to the egress rate control module.

In some embodiments, in STM-4 mode, the FIFO memory is as shown in FIG. 3C, and after the traffic of the STM-4 optical interface of the source is demapped by AMP, BMP or GMP, the data is sent to the cache input interface DIN [3:0] of the FIFO memory. In some embodiments, the depth of the FIFO in STM-4 mode is 64, the bit width is 4 bits, from DIN [3:0] are written into the FIFO memory sequentially. In some embodiments, the FIFO memory further comprises an input control interface WEN for controlling the on and off of the buffer input interface. In some embodiments, the write-side clock interface is connected to a demapping module of the OTN device, and obtains, as the write-side clock, the clock clk_otn sent from the OTN by the demapping module.

The read-side clock interface acquires the multiplied clock CLK311M04 output by the clock determination module as a read-side clock. The FIFO memory outputs the buffered data through the buffer output interface DOUT [3:0]. In some embodiments, the FIFO memory further comprises an output control interface REN for controlling the on and off of the buffer output interface. The output USED [5:0] on the read side of the FIFO represents the amount of memory space USED in the FIFO and is sent to the egress rate control module.

In the clock transparent transmission device in the embodiment, the buffer module can be suitable for STM-1 and STM-4 modes, so that the application range is expanded, and popularization and application are facilitated.

A schematic diagram of some embodiments of an exit rate control module in a clock pass-through device of the present disclosure is shown in fig. 4A-B.

In some embodiments, the exit rate control module 440 includes: a multiplied clock input interface 441, an occupied buffer space input interface 442, an ingress rate input interface 443, a buffer read interface 444, and a data output interface 445.

The multiplied clock input interface 441 is connected to the multiplied clock output interface of the clock determination module, and is capable of receiving the multiplied clock. The occupied buffer space input interface 442 is coupled to the occupied buffer space output interface of the buffer module and is configured to obtain the amount of occupied buffer space. The ingress rate input interface 443 is coupled to the ingress rate statistics module and is capable of receiving an ingress rate. The cache read interface 444 is connected to the cache output interface of the cache module, and is capable of reading data cached in the cache module. The data output interface 445 is connected to the input interface of the clock determination module and is capable of outputting the bitwise copied data to the clock determination module.

In some embodiments, the egress rate control module designs a Token bucket [31:0], filters out the high-frequency jitter of the actual transmission rate F [23:0]/F [25:0] of the service source counted by the ingress rate statistics module, and controls the transmission rate of the transmission data stream by combining the use number USED [5:0] of the buffer space sent by the FIFO memory. As shown in fig. 4B (fig. 4B includes a clock determination module Serdes TX module in addition to the egress rate control module), a 311.04MHz clock sent by the Serdes TX module is used as a processing clock of the egress rate control module and a read side clock of the FIFO. The Serdes TX module is at STM-64 rate setting with a DATA interface DATA [31:0] bit width of 32 bits.

Generally, when frequency trimming is not required, since the Serdes TX module operates at 9953.28Mbps (STM-64) rate, when the DATA stream to be transmitted is STM-1, each bit of the STM-1 DATA needs to be copied into 64 copies to be sent, that is, 1 bit of DATA read out from the FIFO is expanded into the same 64 bits and then sent out on the DATA [31:0] interface through 2 CLK311M04 clock cycles; when the transmitted DATA stream is STM-4, each bit of the STM-4 DATA needs to be duplicated to 16 parts for transmission, namely, 2 bits of DATA in 4 bits read out from the FIFO are all extended to 16 parts, and then 32 bits of DATA are formed and transmitted through the DATA [31:0] interface.

According to the clock transparent transmission device in the embodiment, the STM-1 or STM-4 data stream to be transmitted can be operated at the STM-64 rate in the Serdes TX module, and the data transmission multiple of the read side of the FIFO is finely adjusted, so that the transmitted data of the STM-1 or STM-4 is slowly changed, the purpose of slowly changing the transmitted data rate is achieved, the transmitted data jitter is ensured to be smaller, the frequency is ensured to dynamically adjust along with the service source, the purpose of frequency transparent transmission is achieved, and meanwhile, the use of a special clock chip is saved.

A schematic diagram of some embodiments of a clock determination module in a clock transparent device of the present disclosure is shown in fig. 5.

In some embodiments, clock determination module 530 includes an input interface 531, an output interface 533, a reference clock receiving interface 532, and a multiplied clock output interface 534.

The reference clock receiving interface 532 is connected to a crystal oscillator, and can acquire a reference clock. The multiplied clock output interface 534 is connected to the output rate control module and the buffer module, and can be used for outputting a multiplied clock. The input interface 531 is connected to the output rate control module, and can obtain the copied data stream output by the output rate control module. The output interface 532 is capable of outputting a data stream according to an operation mode of the clock-transparent device based on the data stream from the input interface.

In some embodiments, the clock determination module 530 is generated by the FPGA design tool, the working rate is set at 9953.28Mbps (STM-64), the DATA bus DATA [31:0] bit width connected to the egress rate control module is 32 bits, and therefore the clock frequency sent by the Serdes TX module is 9953.28/32= 311.04MHz, the clock is obtained by multiplying the frequency of the phase-locked loop inside the Serdes module with the local crystal as the reference clock, and the clock is named CLK311M04, and is used as the processing clock of the egress rate control module and the read side clock of the FIFO.

A schematic diagram of some embodiments of traffic egress rate adjustment in STM-1 mode for a clock transparent device of the present disclosure is shown in fig. 6.

The sequence read from the FIFO is: 0 1 … 1, the DATA [31:0] interface signals of the Serdes TX module are:

32’b0000-0000-0000-0000-0000-0000-0000-0000

32’b0000-0000-0000-0000-0000-0000-0000-0000

32’b1111-1111-1111-1111-1111-1111-1111-1111

32’b1111-1111-1111-1111-1111-1111-1111-1111

…

32’b1111-1111-1111-1111-1111-1111-1111-1111

32’b1111-1111-1111-1111-1111-1111-1111-1111

when data needs to be sent faster, it is assumed that the sequence read out from the FIFO is: 0 1 …, at this time, on the DATA [31:0] interface of the Serdes TX module, the number of copies of 0 read out by the FIFO is reduced to 63, and the 1-bit DATA missing on the DATA [31:0] bus is padded with the 64 1's copied later. The signals are as follows:

32’b0000-0000-0000-0000-0000-0000-0000-0000

32’b0000-0000-0000-0000-0000-0000-0000-0001

32’b1111-1111-1111-1111-1111-1111-1111-1111

32’b1111-1111-1111-1111-1111-1111-1111-111X

when data needs to be sent slowly, it is assumed that the sequence read from the FIFO is: 0 1 …, the DATA [31:0] interface signals of the Serdes TX module are sequentially as follows:

32’b0000-0000-0000-0000-0000-0000-0000-0000

32’b0000-0000-0000-0000-0000-0000-0000-0000

32’b0111-1111-1111-1111-1111-1111-1111-1111

32’b1111-1111-1111-1111-1111-1111-1111-1111

32’b1xxx-…

under the design method of the data rate adjustment, the control precision of the rate adjustment is +/-1/64 which is greater than the frequency deviation of the SDH optical interface clock by +/-4.6 PPM, and the requirements of tracking the service clock of the source end and being better than +/-4.6 PPM are achieved by intermittently performing the rate adjustment.

A schematic diagram of some embodiments of an optical transport network device 70 of the present disclosure. The optical transport network device 70 includes a clock transparent device 700, and the clock transparent device 700 may be any of those mentioned above.

The optical transport network device can copy the entry data stream bit by bit based on the frequency multiplication clock and then output the data stream, and the output rate can be finely adjusted along with the input rate through the change of the copy times, so that the dependence on a special clock chip is reduced, and the cost of the OTN device is reduced. In addition, the device saves the area and the power consumption of a PCB, reduces the volume of OTN box-type equipment, and is more energy-saving and environment-friendly.

A schematic diagram of some embodiments of the uplink and downlink data transmission of the optical transport network SDH service system of the present disclosure is shown in fig. 8. The service of STM-1 or STM-4 optical interface of source end enters OTN network through various mapping modes such as AMP, BMP, GMP to carry and transport, after reaching host end and demapping through corresponding mapping mode, the service enters clock transparent transmission processing device of the disclosure to process, and finally is sent out through Serdes TX of high-speed interface of FPGA chip, thus realizing clock frequency transparent transmission function of optical interfaces of multiple STM-1 and STM-4 rates without using special clock chip, and ensuring index requirement of SDH interface to clock frequency offset.

A flowchart of some embodiments of the clock pass-through method of the present disclosure is shown in fig. 9.

In step 901, the ingress rate of a data stream from a traffic source is counted based on a local clock and updated at a predetermined first frequency. In some embodiments, traffic interface rate F is counted. Since the SDH standard specifies a STM-1 rate of 155.52Mbps, the value of F is expected to be approximately 155.52x105bps for STM-1, which translates to 16-ary number ED4E00, which is represented by 24 bits, namely F [23:0]; STM-4 is 4 times that of STM-1 and is represented by 26 bits, F [25:0].

In step 902, the local crystal is multiplied by a reference clock to obtain a multiplied clock.

In some embodiments, steps 901 and 902 may be performed in parallel without precedence.

In step 903, the data of the data stream is buffered and the amount of occupied buffer space is determined.

In step 904, the data buffered by the buffer module is read, and the buffered data is output after being copied bit by bit based on the frequency multiplication clock, wherein the number of times of copying is dynamically adjusted according to the entry rate and the occupied buffer space amount rate.

In some embodiments, taking STM-1 mode as an example, when no rate adjustment is required, 1 bit of DATA is read from DOUT [0] every 2 CLK311M04 clock cycles, 32 copies of each clock cycle are sent to interface signal DATA [31:0] of the Serdes TX module, and 64 copies of the copied transmissions are completed for 2 clock cycles.

By the method, the input data stream can be output after being copied bit by bit based on the frequency multiplication clock, the output rate can be finely adjusted along with the input rate through the change of the copying times, the dependence on a special clock chip is reduced, and the cost of the OTN equipment is reduced.

In some embodiments, the current service mode may also be set first, and specific device parameters may be as shown in table 1.

TABLE 1STM-1/4 Pattern setting parameter definition

By the method, the method can be applied to STM-1/4 mode, and the application range is enlarged.

In some embodiments, in step 904 described above, the high frequency jitter of F [23:0]/F [25:0] introduced by the larger jitter in OTN demapping can be filtered out by using a token bucket control mechanism.

In some embodiments, the token bucket operates under two conditions, namely, the USED [5:0] sent by the FIFO module and the entry rate indicator F [23:0]/F [25:0] sent by the entry rate statistics module, as follows:

A. initializing: token=32' h8000-0000;

B. when (USED [5:0] > = 8) & & (USED [5:0] < = 56), every 100ms token=token+f [23:0] or F [25:0];

when (USED [5:0] > 56): setting token=32' h8000-0000, continuing to read FIFO until FIFO returns to USED [5:0] =32;

When (USED [5:0] < 8): setting token=32' h8000-0000, stopping reading FIFO until FIFO returns to USED [5:0] =32;

C. each time 1 bit of data is read from the FIFO in STM-1 mode, token=token-1; every time 4 bits of data are read from the FIFO in STM-4 mode, token=token-4;

D. token no longer increases when Token > = 32' hE 000-0000; token no longer decreases when Token < = 32' h 2000-0000;

from the above rules, it is known that: the token injection rule is to inject the bit number actually input by the SDH data stream once every 100 ms; the token deduction rule is to deduct the corresponding token every 1 bit (or 4 bits) read from the FIFO. The injection of tokens is balanced against deduction.

In some embodiments, dynamic adjustment of the transmitted data rate is required in order for the frequency information carried by the transmitted data to track the STM-1 or STM-4 data stream rate at the source. The rules for rate adjustment are shown in table 2.

Table 2 rules for token bucket based rate adjustment

Based on the method in the embodiment, the problem that the OTN access layer equipment bears multiple paths of SDH optical interfaces and provides clock frequency transparent transmission can be solved under the condition that a special clock chip is not used, and the equipment cost is reduced; the frequency tracking is converted into the adjustment of the transmission speed of the data stream by adjusting the transmission number of the data stream (only 1/64 or 1/16 is adjusted each time) under the STM-64 mode by setting a frequency multiplication clock, so that the frequency of a tracking data source is realized; by means of Token bucket, balance of data quantity between input and output is guaranteed.

The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Thus far, the present disclosure has been described in detail. In order to avoid obscuring the concepts of the present disclosure, some details known in the art are not described. How to implement the solutions disclosed herein will be fully apparent to those skilled in the art from the above description.

The methods and apparatus of the present disclosure may be implemented in a number of ways. For example, the methods and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, firmware. The above-described sequence of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the sequence specifically described above unless specifically stated otherwise. Furthermore, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the drawings are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the disclosure described herein may be capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Finally, it should be noted that: the above embodiments are merely for illustrating the technical solution of the present disclosure and are not limiting thereof; although the present disclosure has been described in detail with reference to preferred embodiments, those of ordinary skill in the art will appreciate that: modifications may be made to the specific embodiments of the disclosure or equivalents may be substituted for part of the technical features; without departing from the spirit of the technical solutions of the present disclosure, it should be covered in the scope of the technical solutions claimed in the present disclosure.

Claims (18)

1. A clock transparent device comprising:

an ingress rate statistics module configured to count ingress rates of data streams from a traffic source based on a local clock and update the ingress rates at a predetermined first frequency;

the buffer module is configured to buffer the data of the data stream and determine the occupied buffer space amount;

the clock determining module is configured to multiply frequency by taking the local crystal as a reference clock to obtain a frequency-multiplied clock;

and the outlet rate control module is configured to read the data buffered by the buffer memory module, copy the buffered data bit by bit based on the frequency multiplication clock and output the data, wherein the number of times of copying is dynamically adjusted according to the inlet rate and the occupied buffer memory space amount rate.

2. The apparatus of claim 1, wherein,

the exit rate control module is configured to:

determining the value of a token bucket according to the read data quantity, the occupied cache space quantity in the cache module and the entry rate acquired by the entry rate statistics module;

determining the number of replications according to the value of the token bucket, wherein:

the number of copies is a first copy number if the value of the token bucket is less than a predetermined low threshold;

The number of copies is a second number of copies in the case where the value of the token bucket is greater than a predetermined high threshold;

the number of copies is an initial number of copies in a case where the value of the token bucket is equal to or less than the predetermined high threshold and equal to or greater than the predetermined low threshold;

the first number of copies > the initial number of copies > the second number of copies.

3. The apparatus of claim 2, wherein the first number of replications is 1 greater than the initial number of replications and the second number of replications is 1 less than the initial number of replications.

4. The apparatus of claim 2, wherein the exit rate control module is configured to:

initializing the token bucket to a predetermined initial value;

increasing the entry rate counted by the entry rate counting module in the token bucket according to a preset second frequency;

each time bit data is read from the cache module, the value of the token bucket is reduced by a preset deduction value;

and if the occupied buffer space amount is larger than a preset first threshold value or the occupied buffer space amount is smaller than a preset second threshold value, setting the token bucket as the preset initial value.

5. The apparatus of claim 2, wherein the exit rate control module is further configured to:

if the occupied buffer space amount is larger than a preset first threshold value, continuously reading the buffer data until the occupied buffer space amount is a preset standard value;

and if the occupied buffer space amount is smaller than a preset second threshold value, stopping reading the buffer data until the occupied buffer space amount is a preset standard value.

6. The apparatus of any one of claims 1-5, wherein the apparatus is compliant with at least one of:

the clock determination module is configured to operate in STM-64 mode;

the data bus bit width of the clock determining module and the outlet rate control module is 32 bits; or (b)

The entry rate statistics module is configured to count the total amount of effective data sent to the write interface of the cache module in a predetermined time, continuously count the total amount of effective data for a predetermined number of times, and then obtain an average value to determine the entry rate.

7. The apparatus of claim 4, wherein the clock transparent means operates in STM-1 mode,

the buffer depth of the buffer module is 64, the bit width is 1 bit, the initial copy number is 63, the data quantity of one bit read from the buffer module each time is 1 bit, and the preset deduction value is 1.

8. The apparatus of claim 4, wherein the clock transparent means operates in STM-4 mode,

the buffer depth of the buffer module is 64, the bit width is 4 bits, the initial copy number is 15, the data quantity of one bit read from the buffer module each time is 4 bits, and the preset deduction value is 4.

9. The apparatus of claim 1, further comprising:

and the mode adjustment module is configured to switch the working modes of the clock transparent transmission device, wherein the working modes comprise STM-1 and STM-4.

10. The apparatus of claim 1, wherein the clock determination module is a Serdes TX module comprising an input interface, an output interface, a reference clock receiving interface, and a multiplied clock output interface, wherein:

the reference clock receiving interface is connected with the crystal oscillator and is configured to acquire a reference clock;

the frequency multiplication clock output interface is connected with the output rate control module and the buffer module and is configured to output a frequency multiplication clock;

the input interface is connected with the outlet rate control module and is configured to acquire the copied data stream output by the outlet rate control module;

the output interface is configured to output a data stream according to an operation mode of the clock transparent device according to the data stream from the input interface.

11. The apparatus of claim 10, wherein,

the buffer memory module is a FIFO module and comprises a write side clock interface, a read side clock interface, a buffer memory input interface, a buffer memory output interface and an occupied buffer memory space amount output interface, wherein:

the write-side clock interface is connected with a clock output interface of the OTN device and is configured to write a data stream into a cache based on a clock output by the OTN device;

the read side clock interface is connected with the frequency multiplication clock output interface of the clock determining module and is configured to output buffered data based on the frequency multiplication clock output by the clock determining module;

the cache input interface is configured to receive an input data stream;

the cache output interface is configured to output cached data to the egress rate control module; and

the occupied amount of buffer space output interface is configured to output the occupied amount of buffer space to the egress rate control module.

12. The apparatus of claim 10, wherein the exit rate control module comprises: the device comprises a frequency multiplication clock input interface, an occupied buffer space input interface, an entry rate input interface, a buffer reading interface and a data output interface, wherein:

The frequency multiplication clock input interface is connected with the frequency multiplication clock output interface of the clock determination module and is configured to receive a frequency multiplication clock;

the occupied cache space input interface is connected with an occupied cache space output interface of the cache module and is configured to acquire the occupied cache space amount;

the ingress rate input interface is coupled to the ingress rate statistics module and configured to receive the ingress rate;

the cache reading interface is connected with the cache output interface of the cache module and is configured to read data cached in the cache module;

the data output interface is connected with the input interface of the clock determining module and is configured to output the data after the bitwise copying to the clock determining module.

13. An optical transport network device comprising a clock transmission apparatus as claimed in any one of claims 1 to 13.

14. A clock transparent method comprising:

taking the local crystal as a reference clock to carry out frequency multiplication to obtain a frequency multiplication clock;

counting an ingress rate of a data stream from a traffic source based on a local clock and updating the ingress rate at a predetermined first frequency;

caching data of the data stream and determining the occupied cache space amount; and

And reading the data cached by the caching module, and copying the cached data bit by bit based on the frequency multiplication clock and outputting the data, wherein the copying times are dynamically adjusted according to the entry rate and the occupied caching space quantity rate.

15. The method of claim 14, wherein the reading the data buffered by the buffer module and copying the buffered data bit by bit based on the multiplied clock and outputting comprises:

determining the value of a token bucket according to the read data quantity, the occupied cache space quantity in the cache module and the entry rate acquired by the entry rate statistics module;

determining the number of replications according to the value of the token bucket, wherein:

the number of copies is a first copy number if the value of the token bucket is less than a predetermined low threshold;

the number of copies is a second number of copies in the case where the value of the token bucket is greater than a predetermined high threshold;

the number of copies is an initial number of copies in a case where the value of the token bucket is equal to or less than the predetermined high threshold and equal to or greater than the predetermined low threshold;

the first replication times > initial replication times > second replication times;

And according to the copying times, copying the cached data bit by bit based on the frequency doubling clock and outputting the data.

16. The method of claim 15, wherein the determining the value of the token bucket based on the amount of data read, the amount of buffer space occupied in the buffer module, and the ingress rate obtained by the ingress rate statistics module comprises:

initializing the token bucket to a predetermined initial value;

increasing the entry rate counted by the entry rate counting module in the token bucket according to a preset second frequency;

each time bit data is read from the cache module, the value of the token bucket is reduced by a preset deduction value;

and if the occupied buffer space amount is larger than a preset first threshold value or the occupied buffer space amount is smaller than a preset second threshold value, setting the token bucket as the preset initial value.

17. The method of claim 15, wherein the reading the data buffered by the buffer module and copying the buffered data bit by bit based on the multiplied clock and outputting further comprises:

if the occupied buffer space amount is larger than a preset first threshold value, continuously reading the buffer data until the occupied buffer space amount is a preset standard value;

And if the occupied buffer space amount is smaller than a preset second threshold value, stopping reading the buffer data until the occupied buffer space amount is a preset standard value.

18. The method of any of claims 14-17, further comprising:

and switching the current working modes, wherein the working modes comprise STM-1 and STM-4.