CN1624933A - Thin film transistor and its manufacturing method - Google Patents

Abstract

The invention mainly provides a thin film transistor which comprises an inner island-shaped structure formed by a semiconductor layer, a lower heavily doped semiconductor layer and an upper heavily doped semiconductor layer. The lower heavily doped semiconductor layer is arranged on the upper surfaces of two opposite sides of the outside of the channel region of the semiconductor layer, and the upper heavily doped semiconductor layer is arranged on the lower heavily doped semiconductor layer and covers two side walls of the lower heavily doped semiconductor layer opposite to the outside of the channel region and two side walls of the two opposite sides of the semiconductor layer, so that the source electrode and the drain electrode are not directly connected with the semiconductor layer.

Description

Thin film transistor and its manufacturing method

technical field

The invention relates to a thin film transistor and its manufacturing method, in particular to an amorphous silicon thin film transistor capable of avoiding source/drain leakage current and its manufacturing method.

Background technique

With the rapid development of liquid crystal display technology, liquid crystal display panels have been widely used in display devices of various electronic products and flat and thin TV products. Since a liquid crystal display panel needs to use a backlight module as a light source, it must be fabricated using a light-transmitting substrate, among which a glass substrate is the most common. However, since glass cannot withstand high temperatures, liquid crystal display panels using glass substrates often use an amorphous silicon layer with a relatively low process temperature as the semiconductor layer material of the thin film transistor.

Please refer to FIG. 1 , which is a schematic diagram of a conventional amorphous silicon thin film transistor 10 . As shown in FIG. 1 , an amorphous silicon thin film transistor 10 includes a substrate 12, a gate electrode 14 disposed on the surface of the substrate 12, a gate insulating layer 16 disposed on the substrate 12 and covering the gate electrode 14, An amorphous silicon layer 18 is located on the surface of the gate insulating layer 16, a heavily doped amorphous silicon layer 20 is located on two opposite sides of the upper surface of the amorphous silicon layer 18, and a source electrode 22 and a drain electrode 24 are respectively located on the heavily doped amorphous silicon layer 20 . The gate electrode 14 , the source electrode 22 and the drain electrode 24 are made of metal material, and the amorphous silicon layer 18 includes a channel region 26 . The amorphous silicon layer 18 and the heavily doped amorphous silicon layer 20 are generally referred to as an island structure, and the heavily doped amorphous silicon layer 20 is arranged on the upper surface of the channel region 26 of the amorphous silicon layer 18 on two opposite sides. The function is to improve the ohmic contact between the source electrode 22 and the drain electrode 24 and the amorphous silicon layer 18 . In addition, the island structure of the existing amorphous silicon thin film transistor 10 is an island-in structure, that is, the size of the amorphous silicon layer 18 is smaller than the size of the gate electrode 14, thereby avoiding the During actual operation, the transistor 10 is illuminated by the backlight source of the liquid crystal display (not shown) under the substrate 12 to generate light leakage current, thereby affecting the switching characteristics.

As shown in FIG. 1 , the source electrode 22 and the drain electrode 24 of the existing amorphous silicon thin film transistor 10 are in direct contact with the sidewall portion of the amorphous silicon layer 18, and since the source electrode 22 and the drain electrode 24 are It is made of metal material, so the junction 28 with the amorphous silicon layer 18 will produce a Schottky contact (schottky contact). In this case, when a negative bias voltage is applied to the gate electrode 12, the holes will accumulate toward the gate electrode 12, and if the drain electrode 24 has a positive bias voltage, the accumulated holes will be released from the drain electrode 24. The pole electrode 24 flows into the amorphous silicon layer 18 through the junction 28 and flows out from the source electrode 22 to form a leakage current. Since the drain electrode 24 is electrically connected to the pixel electrode, the leakage current will cause the charge stored in the pixel to be lost, resulting in a change in the grayscale value of the pixel.

In view of this, based on this shortcoming and years of related experience in thin film transistor manufacturing, the applicant carefully observes and researches, and proposes an improved invention, which can effectively suppress the generation of leakage current and ensure the switching characteristics of thin film transistors.

Contents of the invention

Therefore, the main purpose of the present invention is to provide a thin film transistor and its manufacturing method, so as to avoid the insurmountable problems in the prior art.

According to a preferred embodiment of the present invention, a thin film transistor and its manufacturing method are disclosed. The thin film transistor includes a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate electrode, an inner island structure disposed on the gate insulating layer, and a source The electrode and a drain electrode are respectively arranged on two opposite sides above the inner island structure. The inner island structure includes a semiconductor layer, a lower heavily doped semiconductor layer and an upper heavily doped semiconductor layer from bottom to top, and the materials of the semiconductor layer, the lower heavily doped semiconductor layer and the upper heavily doped semiconductor layer can be amorphous Silicon, wherein the semiconductor layer includes a channel region, the lower heavily doped semiconductor layer is arranged on the upper surface of the opposite sides of the channel region of the semiconductor layer, and the upper heavily doped semiconductor layer is arranged on the lower heavily doped semiconductor layer above, and the upper heavily doped semiconductor layer covers the side walls of the lower heavily doped semiconductor layer opposite to the channel region and the side walls of the opposite sides of the semiconductor layer. The source electrode and the drain electrode are respectively located on the upper heavily doped semiconductor layer on opposite sides of the channel region, and the source electrode and the drain electrode are not directly connected to the semiconductor layer. In addition, the method for manufacturing a thin film transistor of the present invention is to firstly provide a substrate, then form a gate electrode on the surface of the substrate, and sequentially form a gate insulating layer and a semiconductor layer on the surface of the substrate and the gate electrode. with a heavily doped semiconductor layer. Then perform a photolithography and photolithography process to remove part of the lower heavily doped semiconductor layer and semiconductor layer to form an inner island structure (island) on the gate insulating layer, and the inner island structure includes a channel region. Then, an upper heavily doped semiconductor layer and a conductive layer are sequentially formed on the inner island structure and the gate insulating layer, and another photolithography and photolithography process is performed to remove part of the conductive layer for the upper heavily doped semiconductor layer A source electrode and a drain electrode that are not connected are formed on two opposite sides outside the channel region of the inner island structure. Finally, the upper heavily doped semiconductor layer and the lower heavily doped semiconductor layer not covered by the source electrode and the drain electrode are removed, and the upper heavily doped semiconductor layer covers the lower heavily doped semiconductor layer relative to the inner island structure. The two opposite sides outside the channel region and the two opposite sides outside the channel region of the inner island structure, wherein the material of the semiconductor layer, the lower heavily doped semiconductor layer and the upper heavily doped semiconductor layer can be amorphous silicon.

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, preferred embodiments are exemplified below and described in detail in conjunction with the accompanying drawings. However, the following preferred embodiments and drawings are for reference and illustration only, and are not intended to limit the present invention.

Description of drawings

FIG. 1 is a schematic diagram of an existing amorphous silicon thin film transistor;

Fig. 2 is the schematic diagram of the amorphous silicon thin film transistor of the first preferred embodiment of the present invention;

3 to 6 are schematic diagrams of a method for manufacturing the amorphous silicon thin film transistor according to the first preferred embodiment of the present invention shown in FIG. 2;

7 is a schematic diagram of an amorphous silicon thin film transistor according to a second preferred embodiment of the present invention;

8 to 12 are schematic diagrams of a method for manufacturing the amorphous silicon thin film transistor according to the second preferred embodiment of the present invention shown in FIG. 7;

13 is a schematic diagram of an amorphous silicon thin film transistor according to a third preferred embodiment of the present invention;

14 to 17 are schematic diagrams of a method for manufacturing the amorphous silicon thin film transistor according to the third preferred embodiment of the present invention shown in FIG. 13 .

Detailed ways

Please refer to FIG. 2 , which is a schematic diagram of an amorphous silicon thin film transistor 30 according to a first preferred embodiment of the present invention. As shown in FIG. 2, the amorphous silicon thin film transistor 30 includes a substrate 32, a gate electrode 34 disposed on the substrate 32, a gate insulating layer 36 disposed on the substrate 32 and covering the gate electrode 34, An amorphous silicon layer 38 is located on the surface of the gate insulating layer 36, a heavily doped amorphous silicon layer 40 is located on two opposite sides of the upper surface of the amorphous silicon layer 38 and covers two opposite side walls of the amorphous silicon layer 38 , and a source electrode 42 and a drain electrode 44 are respectively located on the heavily doped amorphous silicon layer 40 . The substrate 32 is a glass substrate, but not limited thereto. The gate electrode 34 , the source electrode 42 and the drain electrode 44 are made of metal material, such as aluminum. In addition, the materials of the amorphous silicon layer 38 and the heavily doped amorphous silicon layer 40 can also be other commonly used semiconductor materials, and this embodiment takes amorphous silicon as an example. The amorphous silicon layer 38 includes a channel region 46 , and the amorphous silicon layer 38 and the heavily doped amorphous silicon layer 40 are generally called island structures. In addition, since the size of the amorphous silicon layer 38 of the amorphous silicon thin film transistor 30 in this embodiment is smaller than the size of the gate electrode 34 , it is an island-in structure. The advantage of the inner island structure is that it can prevent the amorphous silicon thin film transistor 30 from being illuminated by the backlight of the liquid crystal display (not shown) under the substrate 32 to generate light leakage current during actual operation, thereby affecting the switching characteristics. The function of the heavily doped amorphous silicon layer 40 is to improve the ohmic contact between the source electrode 42 and the drain electrode 44 and the amorphous silicon layer 38, wherein it is noteworthy that the heavily doped amorphous silicon thin film transistor 30 of the present invention The hetero-amorphous silicon layer 40 covers both sides of the upper surface outside the channel region 46 of the amorphous silicon layer 38, and simultaneously extends outward to cover two opposite sidewalls of the amorphous silicon layer 38, thereby making the source The electrode 42 and the drain electrode 44 are not in direct contact with the amorphous silicon layer 38 to form a Schottky contact. In this way, when the gate electrode 34 receives a negative bias voltage and the drain electrode 44 receives a positive bias voltage, the amorphous silicon thin film transistor 30 of the present invention will not generate a gap between the drain electrode 44 and the source electrode 42. leakage current.

Please refer to Fig. 3 to Fig. 6, Fig. 3 to Fig. 6 are schematic diagrams of the method for manufacturing the amorphous silicon thin film transistor 30 of the first preferred embodiment of the present invention shown in Fig. Same reference numerals as in Fig. 2. As shown in Figure 3, at first provide a substrate 32, and form a gate electrode 34 on the surface of the substrate 32, wherein the substrate 32 is a glass substrate, but not limited thereto but can be a quartz substrate or other Fabricate the substrate of the thin film transistor. The gate electrode 34 is made of a material with good conductivity, such as metal or polysilicon, and is formed on the substrate 32 by photolithography and etching.

As shown in FIG. 4, a gate insulating layer 36 and an amorphous silicon layer 38 are sequentially formed on the substrate 32 and the surface of the gate electrode 34, wherein the gate insulating layer 36 is made of silicon nitride, silicon oxide or The silicon oxynitride material is used to isolate the gate electrode 34 from the amorphous silicon layer 38 . As shown in FIG. 5, a photolithography and etching process is performed to remove part of the amorphous silicon layer 38 and retain the amorphous silicon layer 38 above the gate electrode 34, and the size of the amorphous silicon layer 38 is slightly smaller than the gate electrode. 34 to form an inner island structure. Subsequently, a heavily doped amorphous silicon layer 40 and a metal layer 41 are sequentially formed on the amorphous silicon layer 38 .

As shown in FIG. 6, another photolithography and etching process is then carried out to form a gap 43 in the metal layer 41, thereby forming a source electrode 42 and a top electrode 42 respectively on the two opposite sides of the amorphous silicon layer 38. drain electrode 44, and remove the heavily doped amorphous silicon layer 40 that is not covered by the source electrode 42 and the drain electrode 44 at the same time, and complete the fabrication of the amorphous silicon thin film transistor 30, wherein the amorphous silicon layer corresponding to the gap 43 38 is the channel region 46 . In addition, the step of removing the heavily doped amorphous silicon layer 40 can be etched by using the mask layer (not shown) for forming the source electrode 42 and the drain electrode 44, or after the source electrode 42 and the drain electrode 44 are formed The mask layer (not shown) is removed, and the source electrode 42 and the drain electrode 44 are directly used as masks for etching.

Please refer to FIG. 7 , which is a schematic diagram of an amorphous silicon thin film transistor 50 according to a second preferred embodiment of the present invention. As shown in FIG. 7, the amorphous silicon TFT 50 includes a substrate 52, a gate electrode 54 disposed on the substrate 52, a gate insulating layer 56 disposed on the substrate 52 and covering the gate electrode 54, An amorphous silicon layer 58 is located on the surface of the gate insulating layer 56 and corresponds to the gate electrode 54. An etch stop pattern 60 covers the surface of the channel region 62 of the amorphous silicon layer 58. A heavily doped amorphous silicon layer 64 is located on the surface of the channel region 62 of the amorphous silicon layer 58. Two opposite sides on the surface of the amorphous silicon layer 58 other than the channel region 62 and cover the etching stop pattern 60 and two opposite sidewalls of the amorphous silicon layer 58, and a source electrode 66 and a drain electrode 68 respectively Located on the surface of the heavily doped amorphous silicon layer 64 . The substrate 52 is a glass substrate, but not limited thereto. The gate electrode 54 , the source electrode 66 and the drain electrode 68 are made of metal material, such as aluminum. The material of the amorphous silicon layer 58 can also be other commonly used semiconductor materials, and this embodiment takes amorphous silicon as an example. In addition, the amorphous silicon layer 58 and the heavily doped amorphous silicon layer 64 of the amorphous silicon thin film transistor 50 of the present invention form an island-in structure. The function of the etching stop pattern 60 is to avoid damage to the amorphous silicon layer 58 when patterning the heavily doped amorphous silicon layer 64, and the function of the heavily doped amorphous silicon layer 64 is to improve the source electrode 66 and the drain electrode. The electrode 68 is in ohmic contact with the amorphous silicon layer 58 , and the heavily doped amorphous silicon layer 64 can partially cover the surface of the etch stop pattern 60 . It is worth noting that the heavily doped amorphous silicon layer 64 of the amorphous silicon thin film transistor 50 of the present invention covers both sides of the upper surface of the amorphous silicon layer 58 except for the channel region 62 , and simultaneously extends outward to cover Two opposite sidewalls of the amorphous silicon layer 58 are covered, so that the source electrode 66 and the drain electrode 68 do not directly contact the amorphous silicon layer 58 to form a Schottky contact. In this way, when the gate electrode 54 receives a negative bias voltage and the drain electrode 68 receives a positive bias voltage, the amorphous silicon thin film transistor 50 of the present invention will not generate a gap between the drain electrode 68 and the source electrode 66. leakage current.

Please refer to Figure 8 to Figure 12. 8 to 12 are schematic diagrams of a method for manufacturing the amorphous silicon thin film transistor 50 according to the second preferred embodiment of the present invention shown in FIG. As shown in Figure 8, at first provide a substrate 52, and form a gate electrode 54 on the surface of the substrate 52, wherein the substrate 52 is a glass substrate, but not limited thereto but can be a quartz substrate or other Fabricate the substrate of the thin film transistor. The gate electrode 54 is made of a material with good conductivity, such as metal or polysilicon, and is formed on the substrate 52 by photolithography and etching.

As shown in FIG. 9, a gate insulating layer 56 and an amorphous silicon layer 58 are sequentially formed on the surface of the substrate 52 and the gate electrode 54, wherein the gate insulating layer 56 is made of silicon nitride, silicon oxide or The silicon oxynitride material is used to isolate the gate electrode 54 from the amorphous silicon layer 58 . As shown in FIG. 10 , a photolithography and etching process is performed to remove part of the amorphous silicon layer 58 and retain the amorphous silicon layer 58 above the gate electrode 54, and the size of the amorphous silicon layer 58 is slightly smaller than the gate electrode. 54 to form an inner island structure. An etch stop pattern 60 is then formed on the amorphous silicon layer 58 to prevent the amorphous silicon layer 58 from being damaged during subsequent patterning of the heavily doped amorphous silicon layer 64 . As shown in FIG. 11 , a heavily doped amorphous silicon layer 64 and a metal layer 65 are sequentially formed on the surfaces of the gate insulating layer 56 , the amorphous silicon layer 58 and the etching stop pattern 60 .

As shown in FIG. 12 , another photolithography and etching process is then carried out to form a gap 67 in the metal layer 65, thereby forming a source electrode 66 and a source electrode 66 respectively on the two opposite sides of the amorphous silicon layer 58. drain electrode 68, and remove the heavily doped amorphous silicon layer 64 that is not covered by the source electrode 66 and the drain electrode 68 at the same time to complete the fabrication of the amorphous silicon thin film transistor 50, wherein the amorphous silicon layer corresponding to the gap 67 58 is the channel region 62 . In addition, the step of removing the heavily doped amorphous silicon layer 64 can be etched using the mask layer (not shown) forming the source electrode 66 and the drain electrode 68, or after the source electrode 66 and the drain electrode 68 are formed The mask layer (not shown) is removed, and etching is performed directly using the source electrode 66 and the drain electrode 68 as a mask.

Please refer to FIG. 13 , which is a schematic diagram of an amorphous silicon thin film transistor 70 according to a third preferred embodiment of the present invention. As shown in FIG. 13 , the amorphous silicon TFT 70 includes a substrate 72, a gate electrode 74 disposed on the surface of the substrate 72, a gate insulating layer 76 disposed on the substrate 72 and covering the gate electrode 74. 1. An amorphous silicon layer 78 is disposed on the gate insulating layer 76 relative to the gate electrode 74, and a heavily doped amorphous silicon layer 80 is located on two opposite sides of the surface of the amorphous silicon layer 78 other than the channel region 82 1. An upper heavily doped amorphous silicon layer 84 is arranged on the upper surface of the lower heavily doped amorphous silicon layer 80, and extends outwards at the same time to cover the side walls of the lower heavily doped amorphous silicon layer 80 and the amorphous silicon The sidewalls of layer 78 , and a source electrode 86 and a drain electrode 88 are respectively located on the surface of the upper heavily doped amorphous silicon layer 84 . The substrate 72 is a glass substrate, but not limited thereto. The gate electrode 74 , the source electrode 86 and the drain electrode 88 are made of metal material, such as aluminum. In addition, the amorphous silicon layer 78 , the lower heavily doped amorphous silicon layer 80 and the upper heavily doped amorphous silicon layer 84 form an island-in structure. The role of the lower heavily doped amorphous silicon layer 80 and the upper heavily doped amorphous silicon layer 84 is to improve the ohmic contact between the source electrode 86 and the drain electrode 88 and the amorphous silicon layer 78, and in this embodiment The amorphous silicon thin film transistor 70 has the effect of the double doped amorphous silicon layer, because the lower heavily doped amorphous silicon layer 80 is directly defined by the photoresist pattern during fabrication, so its surface condition will be affected by particles. The upper heavily doped amorphous silicon layer 84 is defined by the source electrode 86 and the drain electrode 88 , so its surface condition is better. In this case, the upper heavily doped amorphous silicon layer 84 extending to the sidewalls of the lower heavily doped amorphous silicon layer 80 and the sidewalls of the amorphous silicon layer 78 can make the source electrode 86 and the drain electrode 88 not aligned. Direct contact with the amorphous silicon layer 78 creates a Schottky contact. In this way, when the gate electrode 74 receives a negative bias voltage and the drain electrode 88 receives a positive bias voltage, the amorphous silicon thin film transistor 70 of the present invention will not generate a gap between the drain electrode 88 and the source electrode 86. leakage current.

Please refer to Figure 14 to Figure 17. 14 to 17 are schematic diagrams of a method for manufacturing the amorphous silicon thin film transistor 70 according to the third preferred embodiment of the present invention shown in FIG. As shown in Figure 14, at first provide a substrate 72, and form a grid electrode 74 on the surface of the substrate 72, wherein the substrate 72 is a glass substrate, but not limited thereto but can be a quartz substrate or other for Fabricate the substrate of the thin film transistor. The gate electrode 74 is made of a material with good conductivity, such as metal or polysilicon, and is formed on the substrate 72 by photolithography and etching.

As shown in FIG. 15 , a gate insulating layer 76 , an amorphous silicon layer 78 and a heavily doped amorphous silicon layer 80 are sequentially formed on the surfaces of the substrate 72 and the gate electrode 74 , wherein the gate insulating layer 76 is made of silicon nitride, silicon oxide or silicon oxynitride, and is used to isolate the gate electrode 74 from the subsequent amorphous silicon layer 78 used as a channel. As shown in FIG. 16 , a photolithography and etching process is performed to remove part of the lower heavily doped amorphous silicon layer 80 and the amorphous silicon layer 78 while retaining the amorphous silicon layer 78 and the lower heavily doped amorphous silicon layer located above the gate electrode 74. The amorphous silicon layer 80 , and the size of the amorphous silicon layer 78 is slightly smaller than the size of the gate electrode 74 to form an inner island structure. As shown in FIG. 16 , an upper heavily doped amorphous silicon layer 84 and a metal layer 85 are sequentially formed on the surfaces of the gate insulating layer 76 and the lower heavily doped amorphous silicon layer 80 .

As shown in FIG. 17 , another photolithography and etching process is then carried out to form a gap 87 in the metal layer 85, thereby forming a source electrode 86 and a source electrode 86 respectively on the two opposite sides of the amorphous silicon layer 78. drain electrode 88, and simultaneously remove the upper heavily doped amorphous silicon layer 84 and the lower heavily doped amorphous silicon layer 80 not covered by the source electrode 86 and the drain electrode 88, and complete the fabrication of the amorphous silicon thin film transistor 70 , wherein the amorphous silicon layer 78 corresponding to the gap 87 is the channel region 82 . In addition, the step of removing the upper heavily doped amorphous silicon layer 84 and the lower heavily doped amorphous silicon layer 80 can be etched by using the mask layer (not shown) for forming the source electrode 86 and the drain electrode 88, or wait until After the source electrode 86 and the drain electrode 88 are formed, the mask layer (not shown) is removed, and the source electrode 86 and the drain electrode 88 are directly used as masks for etching.

The above-mentioned embodiments of the present invention all use amorphous silicon thin film transistors and their manufacturing methods to illustrate the features of the present invention, mainly based on the fact that amorphous silicon thin film transistors are easily separated by metal electrodes (source electrodes and drain electrodes) and amorphous silicon layers. (semiconductor layer) contact to generate leakage current, but the application of the present invention is not limited to this. If the junction between the semiconductor layer and the metal electrode of other materials causes leakage current due to Schottky contact, the structure of the thin film transistor of the present invention can be applied to reduce the leakage current.

Compared with the prior art, the amorphous silicon layer used as the channel of the amorphous silicon thin film transistor of the present invention is covered by a heavily doped amorphous silicon layer, so the amorphous silicon layer is not connected to the source electrode and the drain electrode. The electrodes are in direct contact, thus effectively avoiding the shortcoming of leakage current between the source electrode and the drain electrode of the conventional amorphous silicon thin film transistor.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (8)

1. A thin film transistor, comprising: a substrate; A gate electrode is formed on the substrate; a gate insulating layer formed on the substrate and covering the gate electrode; An island structure is disposed on the gate insulating layer, the island structure includes: a semiconductor layer formed on the gate insulating layer opposite to the gate electrode, the semiconductor layer including a channel region; and an upper heavily doped semiconductor layer, formed on the semiconductor layer and covering sidewalls on opposite sides of the semiconductor layer outside the channel region; as well as A source electrode and a drain electrode are respectively formed above the upper heavily doped semiconductor layer opposite to two sides of the channel region. 2. The TFT as claimed in claim 1, wherein a size of the semiconductor layer is smaller than a size of the gate electrode. 3. The thin film transistor as claimed in claim 1, wherein the semiconductor layer comprises an amorphous silicon layer. 4. The thin film transistor as claimed in claim 1, wherein the upper heavily doped semiconductor layer is a heavily doped amorphous silicon layer. 5. The TFT as claimed in claim 1, wherein the island structure further comprises an etch stop pattern formed between the semiconductor layer and the upper heavily doped semiconductor layer. 6. The TFT as claimed in claim 5, wherein the upper heavily doped semiconductor layer covers two opposite sidewalls of the etch stop pattern. 7. The thin film transistor according to claim 1, wherein the island structure further comprises a lower heavily doped semiconductor layer formed between the semiconductor layer and the upper heavily doped semiconductor layer and opposite to the channel region. side. 8. The thin film transistor according to claim 7, wherein the upper heavily doped semiconductor layer covers the lower heavily doped semiconductor layer with respect to the two side walls outside the channel region and the side walls on the opposite sides of the semiconductor layer .

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