CN101728436A - Element of thin film transistor and manufacturing method thereof - Google Patents

Abstract

The invention provides a thin film transistor element and a manufacturing method thereof. The thin film transistor device includes a crystalline semiconductor layer and a patterned heavily doped semiconductor layer. The patterned heavily doped semiconductor layer is formed by a deposition process, and the heavily doped semiconductor layer includes a first heavily doped semiconductor layer and a second heavily doped semiconductor layer, wherein the first heavily doped semiconductor layer covers the crystalline semiconductor The first side surface of the layer and part of the upper surface connected to the first side surface, the second heavily doped semiconductor layer covers the second side surface of the crystalline semiconductor layer and part of the upper surface connected to the second side surface.

Description

Thin film transistor element and manufacturing method thereof

technical field

The present invention relates to a thin film transistor element and a manufacturing method thereof, in particular to a thin film transistor element, which has a patterned heavily doped semiconductor layer covering the side surface and part of the upper surface of a crystalline semiconductor layer, and manufacturing the above thin film transistor element Methods.

Background technique

Amorphous silicon (amorphous silicon) thin films have been widely used in flat panel display devices as semiconductor layers of thin film transistor elements (thin film transistor elements using amorphous silicon as semiconductor layers are generally called amorphous silicon thin film transistor elements). However, too low electron mobility, low driving current and poor device reliability limit the application of amorphous silicon thin film transistor devices. For example, the amorphous silicon thin film will produce a light fading effect (Staebler-Wronski effect) under the irradiation of light, so that the stability of the device is not good enough to meet the specification requirements of high-end liquid crystal display devices. Furthermore, when applied to an organic electroluminescent display device, the amorphous silicon thin film transistor element will deteriorate after a long period of use, which will reduce the current passing through the organic light emitting layer, thereby affecting the brightness of light emission. Using polysilicon film as the semiconductor layer not only has higher electron mobility, but also can improve the degradation of transistors.

The heavily doped drain/source layer (also known as the ohmic contact layer) of the polysilicon thin film transistor on the known display panel is mainly produced by the ion implantation process, but limited by the size of the ion implantation machine, it can only be developed to a small size Substrates (substrates before the 4.5th generation or 4th generation), currently there is no ion implantation machine for large-scale substrates, and the ion implantation process is not compatible with the process of standard amorphous silicon thin film transistor components, making polysilicon thin film transistors The process of components is limited.

Contents of the invention

One of the objectives of the present invention is to provide a thin film transistor element and a manufacturing method thereof, so as to solve the problems faced by the conventional technologies.

A preferred embodiment of the present invention provides a thin film transistor device, including a substrate, a crystalline semiconductor layer, a patterned heavily doped semiconductor layer, a source and a drain, a gate insulating layer and a gate . The crystalline semiconductor layer is disposed on the substrate, wherein the crystalline semiconductor layer includes an upper surface, a first side surface and a second side surface. The patterned heavily doped semiconductor layer is disposed on the crystalline semiconductor layer and the substrate, the patterned heavily doped semiconductor layer includes a first heavily doped semiconductor layer and a second heavily doped semiconductor layer, wherein the first heavily doped semiconductor layer Covering the first side surface of the crystalline semiconductor layer and part of the upper surface connected to the first side surface, the second heavily doped semiconductor layer covering the second side surface of the crystalline semiconductor layer and part of the upper surface connected to the second side surface . The source and the drain are respectively disposed on the first heavily doped semiconductor layer and the second heavily doped semiconductor layer. The gate insulating layer is disposed on the source, the drain and the crystalline semiconductor layer. The gate is disposed on the gate insulating layer.

Another preferred embodiment of the present invention provides a method for manufacturing a thin film transistor device, including the following steps. First, a substrate is provided, and a crystalline semiconductor layer is formed on the substrate. Then a heavily doped semiconductor layer is deposited on the crystalline semiconductor layer and the substrate, and the heavily doped semiconductor layer is patterned to form a first heavily doped semiconductor layer and a second heavily doped semiconductor layer. Then a source and a drain are respectively formed on the first heavily doped semiconductor layer and the second heavily doped semiconductor layer.

Another preferred embodiment of the present invention provides a method for manufacturing a thin film transistor device, including the following steps. First, a substrate is provided, and a crystalline semiconductor layer is formed on the substrate. A heavily doped semiconductor layer is then deposited on the crystalline semiconductor layer and the substrate. Then a conductive layer is formed on the heavily doped semiconductor layer. The conductive layer is then patterned to form a source and a drain, and the heavily doped semiconductor layer is patterned to form a first heavily doped semiconductor layer and a second heavily doped semiconductor layer.

The first side surface and the second side surface of the crystalline semiconductor layer of the thin film transistor device of the present invention are respectively covered by the first heavily doped semiconductor layer and the second heavily doped semiconductor layer, and because the heavily doped semiconductor layer can block Hole conduction can avoid the problem of leakage current. In addition, the method for manufacturing a thin film transistor element of the present invention uses a deposition process to form a heavily doped semiconductor layer instead of an ion implantation process to form a heavily doped semiconductor layer, so the process will not be limited by the size of the substrate, and the deposition process Can be integrated in the standard process of amorphous silicon thin film transistor devices.

Description of drawings

1 to 4 illustrate a schematic diagram of a method for manufacturing a thin film transistor device according to a preferred embodiment of the present invention;

5 to 8 are schematic diagrams illustrating a method for manufacturing a thin film transistor device according to another preferred embodiment of the present invention.

Among them, reference signs

10 Substrate 12 Crystalline semiconductor layer

121 upper surface 122 first side surface

123 Second side surface 14 Heavily doped semiconductor layer

141 First heavily doped semiconductor layer 142 Second heavily doped semiconductor layer

16 Conductive layer 16S Source

16D Drain 18 Gate Insulator

20 Gate Gate 22 Thin Film Transistor Components

30 Substrate 32 Crystalline semiconductor layer

321 upper surface 322 first side surface

323 Second side surface 34 Heavily doped semiconductor layer

36 Conductive layer 36S Source

36D Drain 38 Gate Insulator

40 Gate Gate 42 Thin Film Transistor Components

Detailed ways

In order for those skilled in the art to have a better understanding of the present invention, preferred embodiments of the present invention are listed below, together with the accompanying drawings, to describe in detail the composition and desired effects of the present invention.

Please refer to Figure 1 to Figure 4. 1 to 4 are diagrams illustrating a method for manufacturing a thin film transistor device according to a preferred embodiment of the present invention. As shown in FIG. 1 , firstly, a substrate 10 is provided, wherein the substrate 10 can be a transparent substrate such as a glass substrate, but not limited thereto and can be other various types of substrates, such as a plastic substrate or a wafer. Then a crystalline semiconductor layer 12 is formed on the substrate 10 . Before forming the crystalline semiconductor layer 12 , a buffer layer (not shown) can be optionally formed on the substrate 10 . The crystalline semiconductor layer 12 of the present embodiment selects a polycrystalline silicon semiconductor layer (polycrystalline silicon semiconductor layer), but the material of the crystalline semiconductor layer 12 is not limited to silicon, but can be other semiconductor materials, and its crystal form is not limited to polycrystalline, and Other crystalline forms are possible, for example, microcrystalline. In this embodiment, the fabrication of the crystalline semiconductor layer 12 includes the following steps. Forming an amorphous semiconductor layer on the substrate 10, such as an amorphous silicon semiconductor layer (amorphous silicon semiconductor layer); performing a modification process to convert the amorphous semiconductor layer into a crystalline semiconductor layer 12 (here, a polysilicon semiconductor layer); And patterning the crystalline semiconductor layer 12, for example, using photolithography and etching techniques. In this embodiment, the modification process is a solid phase crystallization (SPC) process, which converts amorphous silicon into polysilicon at a high temperature of about 600° C. to 700° C. Because at this high temperature, the substrate 10 will inevitably shrink due to excessive temperature, so the thin film transistor element of this embodiment is a top gate type (top-gate type) thin film transistor element, that is, after the high temperature After the polysilicon semiconductor layer is formed by the solid-state crystallization process, the source/drain and the gate are fabricated sequentially, so there will be no problem of misalignment. It is worth noting that in this embodiment, the modification process is not limited to the solid-state crystallization process, but other various modification processes can be used, such as rapid thermal process (rapid thermal process, RTP), furnace heating process , excimer laser annealing (excimerlaser annealing, ELA) process, metal-induced crystallization (metal-induced crystallization, MIC) process, metal-induced lateral crystallization (metal-induced lateral crystallization, MILC) process, sequential lateral crystallization (sequential lateral solidification (SLS) process or continuous silicon crystallization (continuous grain silicon, CGS) and other modification processes. In addition, the method of this embodiment is not limited to forming the crystalline semiconductor layer 12 through a modification process, for example, the crystalline semiconductor layer 12 can also be directly formed on the substrate 10 and patterned. After patterning, the crystalline semiconductor layer 12 includes an upper surface 121 , a first side surface 122 and a second side surface 123 .

As shown in FIG. 2, a heavily doped semiconductor layer 14 (such as an N-type heavily doped semiconductor layer) is deposited on the crystalline semiconductor layer 12 and the substrate 10, and the heavily doped semiconductor layer 14 is patterned to form a first The heavily doped semiconductor layer 141 and a second heavily doped semiconductor layer 142, wherein the heavily doped semiconductor layer 14 can be formed using, for example, a chemical vapor deposition process, and the step of patterning the heavily doped semiconductor layer 14 can be used, such as photolithography and Etching technology and mask to achieve. The first heavily doped semiconductor layer 141 and the second heavily doped semiconductor layer 142 respectively correspond to two sides of the crystalline semiconductor layer 12, and the first heavily doped semiconductor layer 141 covers the first side surface 122 of the crystalline semiconductor layer 12 and The first side surface 122 is connected to a part of the upper surface 121 , and the second heavily doped semiconductor layer 142 covers the second side surface 123 of the crystalline semiconductor layer 12 and the part of the upper surface 121 connected to the second side surface 123 .

As shown in FIG. 3, a conductive layer 16, such as a metal layer, is then formed on the substrate 10, the crystalline semiconductor layer 12, and the heavily doped semiconductor layer 14, and the conductive layer is patterned using photolithography and etching techniques with a mask 16 to form a source 16S and a drain 16D. In this embodiment, the source electrode 16S is substantially located on the first heavily doped semiconductor layer 141 and is not in contact with the crystalline semiconductor layer 12. In addition, the source electrode 16S protrudes from the first heavily doped semiconductor layer 141 and partially covers the substrate 10. The drain 16D is substantially located on the second heavily doped semiconductor layer 142 and is not in contact with the crystalline semiconductor layer 12 , and the drain 16D protrudes from the second heavily doped semiconductor layer 142 to partially cover the substrate 10 . It can be seen from FIG. 3 that the first side surface 122 and the second side surface 123 of the crystalline semiconductor layer 12 are respectively covered by the first heavily doped semiconductor layer 141 and the second heavily doped semiconductor layer 142, so the source 16S and the crystallization A first heavily doped semiconductor layer 141 is disposed between the first side surface 122 of the semiconductor layer 12, and a second heavily doped semiconductor layer 142 is disposed between the drain 16D and the second side surface 123 of the crystalline semiconductor layer 12, In this way, the first heavily doped semiconductor layer 141 and the second heavily doped semiconductor layer 142 can block hole conduction, thereby preventing current leakage between the source 16S/drain 16D and the crystalline semiconductor layer 12 .

As shown in FIG. 4 , a gate insulating layer 18 is then formed on the substrate 10 , the crystalline semiconductor layer 12 , the source 16S and the drain 16D, and then a gate 20 corresponding to the crystalline semiconductor layer 12 is formed on the gate insulating layer 18 , to form the thin film transistor element 22 of this embodiment.

Please refer to Figure 5 to Figure 8. 5 to 8 are schematic diagrams of a method for manufacturing a thin film transistor device according to another preferred embodiment of the present invention. In order to simplify the description and facilitate the comparison of the differences between the various embodiments, this embodiment mainly only focuses on the differences. Description will be given without repeating the similarities. As shown in FIG. 5 , firstly, a substrate 30 is provided. Next, a crystalline semiconductor layer 32 is formed on the substrate 30 , and the crystalline semiconductor layer 32 is patterned. The crystalline semiconductor layer 32 includes an upper surface 321 , a first side surface 322 and a second side surface 323 .

As shown in FIG. 6 , a heavily doped semiconductor layer 34 and a conductive layer 36 are sequentially formed on the crystalline semiconductor layer 32 and the substrate 30, wherein the heavily doped semiconductor layer 34 can be formed by, for example, a chemical vapor deposition process, and The conductive layer 36 can be, for example, a metal layer or other conductive layers with good conductivity.

As shown in FIG. 7, the heavily doped semiconductor layer 34 is patterned to form a first heavily doped semiconductor layer 341 and a second heavily doped semiconductor layer 342, and the conductive layer 36 is patterned to form a source 36S and a Drain 36D. In this embodiment, the heavily doped semiconductor layer 34 and the conductive layer 36 are patterned using the same mask, thus having the advantage of simplifying the process, but not limited thereto, for example, the heavily doped semiconductor layer 34 and the conductive layer 36 are also The patterning can be done separately using different masks or otherwise. The first heavily doped semiconductor layer 341 and the second heavily doped semiconductor layer 342 correspond to two sides of the crystalline semiconductor layer 32 respectively, wherein the first heavily doped semiconductor layer 341 covers the first side surface 322 of the crystalline semiconductor layer 32 and The part of the upper surface 321 connected by the first side surface 322, and the first heavily doped semiconductor layer 341 also covers part of the substrate 30; the second heavily doped semiconductor layer 342 covers the second side surface 323 of the crystalline semiconductor layer 32 and is in contact with the second side surface 323 of the crystalline semiconductor layer 32. The second side surface 323 is connected to a portion of the upper surface 321 , and the second heavily doped semiconductor layer 342 also covers a portion of the substrate 30 . In addition, in this embodiment, the edge of the source 36S is substantially aligned with the edge of the first heavily doped semiconductor layer 341 , and the edge of the drain 36D is substantially aligned with the edge of the second heavily doped semiconductor layer 342 . It can be seen from FIG. 7 that the first side surface 322 and the second side surface 323 of the crystalline semiconductor layer 32 are respectively covered by the first heavily doped semiconductor layer 341 and the second heavily doped semiconductor layer 342, so the source 36S and the crystalline A first heavily doped semiconductor layer 341 is disposed between the first side surface 322 of the semiconductor layer 32, and a second heavily doped semiconductor layer 342 is disposed between the drain 36D and the second side surface 323 of the crystalline semiconductor layer 32, In this way, the first heavily doped semiconductor layer 341 and the second heavily doped semiconductor layer 342 can block hole conduction, thereby avoiding the problem of leakage current.

As shown in FIG. 8 , a gate insulating layer 38 is then formed on the substrate 30 , the crystalline semiconductor layer 32 , the source 36S and the drain 36D, and then a gate 40 corresponding to the crystalline semiconductor layer 32 is formed on the gate insulating layer 38 , to form the thin film transistor element 42 of this embodiment.

To sum up, the first side surface and the second side surface of the crystalline semiconductor layer of the thin film transistor element of the present invention are respectively covered by the first heavily doped semiconductor layer and the second heavily doped semiconductor layer, and due to the heavily doped The hetero-semiconductor layer can block hole conduction, thereby avoiding the problem of leakage current. In addition, the method for manufacturing a thin film transistor element of the present invention uses a chemical deposition process to form a heavily doped semiconductor layer instead of an ion implantation process to form a heavily doped semiconductor layer, so the process is not limited by the size of the substrate, and the chemical deposition process Can be integrated in the standard process of amorphous silicon thin film transistor devices. In addition, the thin film transistor device of the present invention is a top-gate thin film transistor device, so when the crystalline silicon semiconductor layer is formed by a high-temperature transfer process, the problem of misalignment will not occur. Furthermore, the thin film transistor device of the present invention uses a crystalline silicon semiconductor layer as a channel, so it has the characteristics of high electron mobility, high drive current and high device reliability, so it can be applied to high-order liquid crystal display devices or organic electroluminescence Display devices and other products.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (19)

1. a thin-film transistor element is characterized in that, comprising:

One substrate;

One crystalline semiconductor layer is arranged on this substrate, and wherein this crystalline semiconductor layer comprises a upper surface, one first side surface and one second side surface;

One patterning severe doping semiconductor layer, be arranged on this crystalline semiconductor layer and this substrate, this patterning severe doping semiconductor layer comprises one first severe doping semiconductor layer and one second severe doping semiconductor layer, wherein this first severe doping semiconductor layer coats this first side surface of this crystalline semiconductor layer and this upper surface of part that is connected with this first side surface, and this second severe doping semiconductor layer coats this second side surface of this crystalline semiconductor layer and this upper surface of part that is connected with this second side surface; And

An one source pole and a drain electrode are arranged at respectively on this first severe doping semiconductor layer and this second severe doping semiconductor layer;

One gate insulator is arranged on this source electrode, this drain electrode and this crystalline semiconductor layer; And

One grid is arranged on this gate insulator.

2. thin-film transistor element according to claim 1 is characterized in that this crystalline semiconductor layer comprises a polysilicon semiconductor layer.

3. thin-film transistor element according to claim 1 is characterized in that, this first severe doping semiconductor layer is this substrate of cover part in addition, and this second severe doping semiconductor layer this substrate of cover part in addition.

4. thin-film transistor element according to claim 3 is characterized in that, the edge of this source electrode substantially with the justified margin of this first severe doping semiconductor layer, and edge that should drain electrode substantially with the justified margin of this second severe doping semiconductor layer.

5. thin-film transistor element according to claim 1 is characterized in that, this source electrode protrudes in this first severe doping semiconductor layer and this substrate of cover part, and this drain electrode protrudes in this second severe doping semiconductor layer and this substrate of cover part.

6. a method of making thin-film transistor element is characterized in that, comprising:

One substrate is provided;

On this substrate, form a crystalline semiconductor layer;

Deposition one severe doping semiconductor layer on this crystalline semiconductor layer and this substrate, and this severe doping semiconductor layer of patterning is to form one first severe doping semiconductor layer and one second severe doping semiconductor layer; And

On this first severe doping semiconductor layer and this second severe doping semiconductor layer, form an one source pole and a drain electrode respectively.

7. the method for making thin-film transistor element according to claim 6 is characterized in that, this crystalline semiconductor layer comprises a polysilicon semiconductor layer.

8. the method for making thin-film transistor element according to claim 6, it is characterized in that, this crystalline semiconductor layer comprises a upper surface, one first side surface and one second side surface, this first severe doping semiconductor layer coats this first side surface of this crystalline semiconductor layer and this upper surface of part that is connected with this first side surface, and this second severe doping semiconductor layer coats this second side surface of this crystalline semiconductor layer and this upper surface of part that is connected with this second side surface.

9. the method for making thin-film transistor element according to claim 8 is characterized in that, this first severe doping semiconductor layer is this substrate of cover part in addition, and this second severe doping semiconductor layer this substrate of cover part in addition.

10. the method for making thin-film transistor element according to claim 9, it is characterized in that, the edge of this source electrode substantially with the justified margin of this first severe doping semiconductor layer, and edge that should drain electrode substantially with the justified margin of this second severe doping semiconductor layer.

11. the method for making thin-film transistor element according to claim 8, it is characterized in that, this source electrode protrudes in this first severe doping semiconductor layer and this substrate of cover part, and this drain electrode protrudes in this second severe doping semiconductor layer and this substrate of cover part.

12. the method for making thin-film transistor element according to claim 6 is characterized in that, other is included in and forms a gate insulator and a grid in this crystalline semiconductor layer, this source electrode and this drain electrode in regular turn.

13. a method of making thin-film transistor element is characterized in that, comprising:

One substrate is provided;

On this substrate, form a crystalline semiconductor layer;

Deposition one severe doping semiconductor layer on this crystalline semiconductor layer and this substrate;

On this severe doping semiconductor layer, form a conductive layer;

This conductive layer of patterning drains to form one source pole and, and this severe doping semiconductor layer of patterning is to form one first severe doping semiconductor layer and one second severe doping semiconductor layer.

14. the method for making thin-film transistor element according to claim 13 is characterized in that, this source electrode, this drain electrode, this first severe doping semiconductor layer and this second severe doping semiconductor layer utilize same mask to carry out patterning.

15. the method for making thin-film transistor element according to claim 13 is characterized in that, this crystalline semiconductor layer comprises a polysilicon semiconductor layer.

16. the method for making thin-film transistor element according to claim 13, it is characterized in that, this crystalline semiconductor layer comprises a upper surface, one first side surface and one second side surface, this first severe doping semiconductor layer coats this first side surface of this crystalline semiconductor layer and this upper surface of part that is connected with this first side surface, and this second side surface of this this crystalline semiconductor layer of second severe doping semiconductor layer and this upper surface of part of being connected with this second side surface.

17. the method for making thin-film transistor element according to claim 16 is characterized in that, this first severe doping semiconductor layer is this substrate of cover part in addition, and this second severe doping semiconductor layer this substrate of cover part in addition.

18. the method for making thin-film transistor element according to claim 17, it is characterized in that, the edge of this source electrode substantially with the justified margin of this first severe doping semiconductor layer, and edge that should drain electrode substantially with the justified margin of this second severe doping semiconductor layer.

19. the method for making thin-film transistor element according to claim 13, it is characterized in that, this source electrode protrudes in this first severe doping semiconductor layer and this substrate of cover part, and this drain electrode protrudes in this second severe doping semiconductor layer and this substrate of cover part.

Images