CN1570741A

CN1570741A - Thin film transistor array substrate and manufacturing method thereof

Info

Publication number: CN1570741A
Application number: CN 200410038226
Authority: CN
Inventors: 来汉中
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2004-05-13
Filing date: 2004-05-13
Publication date: 2005-01-26
Anticipated expiration: 2024-05-13
Also published as: CN100498480C

Abstract

A thin film transistor array substrate is composed of a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, an etch barrier layer and a plurality of pixel electrodes. The scanning wiring and the data wiring are arranged on the substrate so as to divide the substrate into a plurality of pixel areas. Each thin film transistor is configured in the corresponding pixel region and is driven by the corresponding scanning wiring and the corresponding data wiring. The etching barrier layer is disposed above the scan line or the common line and has a plurality of openings. Each pixel electrode is configured in the corresponding pixel region to be electrically connected with the corresponding thin film transistor, wherein a partial region of each pixel electrode is respectively coupled with the corresponding scanning wiring to form a storage capacitor through one opening. In addition, the invention also provides a manufacturing method of the thin film transistor array substrate.

Description

Thin-film transistor array base-plate and manufacture method thereof

Technical field

The invention relates to a kind of thin-film transistor array base-plate (Thin Film Transistorarray, TFT array) and manufacture method, and particularly can increase storage capacitors in each pixel (storage capacitor, thin-film transistor array base-plate Cst) and manufacture method thereof relevant for a kind of.

Background technology

At improving rapidly of multimedia society, be indebted to the tremendous progress of semiconductor subassembly or display device mostly.With regard to display, (Cathode Ray Tube CRT) because of having excellent display quality and its economy, monopolizes monitor market in recent years to cathode-ray tube (CRT) always.Yet, operate the environment of most terminating machine/display equipments on the table for the individual, or with the incision of the viewpoint of environmental protection, if predicted with the trend of saving the energy, cathode-ray tube (CRT) is because of still existing a lot of problems in space utilization and the energy resource consumption, and can't effectively provide solution for the demand of light, thin, short, little and low consumpting power.Therefore, have that high image quality, space utilization efficient are good, the Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT LCD) of low consumpting power, advantageous characteristic such as radiationless becomes the main flow in market gradually.

Thin Film Transistor-LCD (TFT-LCD) mainly is made of thin-film transistor array base-plate, colorful filter array substrate and liquid crystal layer, and wherein thin-film transistor array base-plate is formed by the thin film transistor (TFT) of a plurality of arrayed and with the pixel electrode (pixel electrode) of the corresponding configuration of each thin film transistor (TFT).And the film crystal piping is used as the switch module of liquid crystal display.In addition, in order to control other pixel cell, usually can be via scan wiring (scan line) and data wiring (date line) choosing specific pixel, and by suitable operating voltage is provided, to show the video data of corresponding this pixel.In addition, the subregion of above-mentioned pixel electrode can be covered on scan wiring or the shared wiring (common line) usually, to form storage capacitors.In the known technology, common storage capacitors can be divided into metal level-insulation course-metal level (Metal-Insulator-Metal, MIM) and metal level-insulation course-indium tin oxide layer (Metal-Insulator-ITO, MII) two kinds of frameworks below will be described in detail at the storage capacitor structure of above-mentioned two kinds of frameworks.

Fig. 1 is the diagrammatic cross-section of the storage capacitors of known metal level-insulation course-metal level (MIM) framework.Please refer to Fig. 1, in known dot structure, the storage capacitors Cst of metal level-insulation course-metal level (MIM) framework is coupled to form by the top electrode 120 of scan wiring or shared wiring 100 and its top usually.It should be noted that, in the storage capacitors of metal level-insulation course-metal level (MIM) framework, scan wiring or shared wiring 100 are electrically insulated by gate insulator 110 each other with top electrode 120, so storage capacitors value Cst is relevant with the thickness of gate insulator 110.In other words, the thickness of gate insulator 110 is more little, and storage capacitors value Cst is just big more.In addition, pixel electrode 140 electrically connects by contact hole in the protective seam 130 132 and top electrode 120.

Fig. 2 is the diagrammatic cross-section of the storage capacitors of known metal level-insulation course-indium tin oxide layer (MII) framework.Please refer to Fig. 2, in known dot structure, the storage capacitors of metal level-insulation course-indium tin oxide layer (MII) framework is coupled to form by the pixel electrode 230 of scan wiring or shared wiring 200 and its top usually.Be with metal level-insulation course-metal level (MIM) framework difference; scan wiring in the storage capacitors of metal level-insulation course-indium tin oxide layer (MII) framework or shared wiring 200 are electrically insulated by gate insulator 210 and protective seam 220 each other with pixel electrode 230, so storage capacitors value Cst is relevant with the gross thickness of gate insulator 210 and protective seam 220.In other words, the gross thickness of gate insulator 210 and protective seam 220 is more little, and storage capacitors value Cst is just big more.

In known thin-film transistor array base-plate; if will under the prerequisite that does not influence aperture opening ratio, increase storage capacitors value Cst; then must reduce the thickness of gate insulator 210 and/or protective seam 220, but if the thickness of reduction gate insulator 210 and/or protective seam 220 might make then the assembly reliability (reliability) of thin film transistor (TFT) descend.

Summary of the invention

Purpose of the present invention is providing a kind of thin-film transistor array base-plate exactly, and it can effectively promote the storage capacitors in each pixel.

Another object of the present invention is exactly that a kind of manufacture method of thin-film transistor array base-plate is being provided, its can with existing process compatible, and can effectively promote storage capacitors in each pixel.

For reaching above-mentioned or the present invention of other purpose proposes a kind of thin-film transistor array base-plate, this thin-film transistor array base-plate is made of a substrate, a plurality of scan wiring, plurality of data distribution, plurality of films transistor, an etch barrier and plurality of pixel electrodes.Wherein, scan wiring and data wiring are disposed on the substrate, substrate zone is divided into a plurality of pixel regions.Each thin film transistor (TFT) is disposed in the corresponding pixel region, and drives by corresponding scan wiring and data wiring.Etch barrier series of strata configuration scan wiring top, and etch barrier has plurality of openings.Each pixel electrode is disposed in the corresponding pixel region, and to electrically connect with corresponding thin film transistor (TFT), wherein the subregion of each pixel electrode is coupled as a storage capacitors with corresponding scan wiring respectively by one of them opening.

For reaching above-mentioned or the present invention of other purpose proposes a kind of thin-film transistor array base-plate, this thin-film transistor array base-plate is by a substrate, a plurality of scan wiring, plurality of data distribution, plurality of films transistor, a plurality of shared wiring, an etch barrier, and plurality of pixel electrodes constitutes.Wherein, scan wiring and data wiring are disposed on the substrate, substrate zone is divided into a plurality of pixel regions.Each thin film transistor (TFT) is disposed in the corresponding pixel region, and drives by corresponding scan wiring and data wiring.Shared wiring is disposed on the substrate, and between two adjacent scan wirings.Etch barrier series of strata configuration shared wiring top, and etch barrier has plurality of openings.Each pixel electrode is disposed in the corresponding pixel region, and to electrically connect with corresponding thin film transistor (TFT), wherein the subregion of each pixel electrode is coupled as a storage capacitors with corresponding shared wiring respectively by one of them opening.

Thin-film transistor array base-plate of the present invention for example comprises more that one is disposed at the gate insulator between etch barrier and the scan wiring (or shared wiring), and this gate insulator has the depression of a plurality of openings corresponding to etch barrier.

Thin-film transistor array base-plate of the present invention for example comprises more that one is disposed at the semiconductor layer between etch barrier and the gate insulator.In addition, the thin-film transistor array base-plate of present embodiment for example comprises more that one is disposed at the protective seam on etch barrier and the gate insulator, and these protection series of strata are with the opening exposure of etch barrier.

In the preferred embodiment of the present invention, etch barrier for example comprises a plurality of strip patterns, and each strip pattern is positioned at corresponding scan wiring (or shared wiring) top.In addition, etch barrier also can comprise a plurality of frame shape patterns, and each frame shape pattern is positioned at corresponding pixel electrode below.

In the preferred embodiment of the present invention, the material of pixel electrode for example is indium tin oxide (ITO), indium-zinc oxide (IZO), or other conductor material.

For reaching the manufacture method that above-mentioned or other purpose the present invention proposes a kind of thin-film transistor array base-plate.At first, on a substrate, form one first patterning conductor layer.Then on the substrate and first patterning conductor layer, form a gate insulator and semiconductor material layer in regular turn.Afterwards, on the subregion of semiconductor material layer, form an etch barrier that is positioned at the first patterning conductor layer top.Then, on semiconductor material layer and etch barrier, optionally form an ohmic contact layer, form a conductor layer afterwards again, and above-mentioned conductor layer, ohmic contact layer and the semiconductor material layer of patterning, to form one second patterning conductor layer and a plurality of semiconductor layer that is positioned at the etch barrier and the second patterning conductor layer below simultaneously.Continue it; on base material, form a protective seam; and the protective seam of subregion top that removes second patterning conductor layer to be to form a plurality of contact holes, and protective seam, etch barrier and the semiconductor layer of top, subregion that removes first patterning conductor layer simultaneously is to form plurality of openings.At last, on base material, form plurality of pixel electrodes, wherein each pixel electrode electrically connects by the corresponding contact window and second patterning conductor layer, and the subregion of each pixel electrode is coupled as a storage capacitors by the corresponding opening and first patterning conductor layer.

In the preferred embodiment of the present invention, before forming a conductor layer on semiconductor material layer and the etch barrier, more comprise optionally forming an ohmic contact layer on semiconductor material layer and etch barrier.

In the preferred embodiment of the present invention, the formation method of first patterning conductor layer for example is to form earlier one first conductor layer on base material, and this first conductor layer of patterning more afterwards is to form a plurality of scan wirings and a plurality of grid that is connected with scan wiring.In this embodiment, etch barrier is formed at grid and scan wiring top.

In the preferred embodiment of the present invention, the formation method of first patterning conductor layer for example forms one first conductor layer earlier on base material, this first conductor layer of patterning more afterwards, forming a plurality of scan wirings, a plurality of grid that is connected with scan wiring, and a plurality of shared wiring between two adjacent scan wirings.In this embodiment, etch barrier is formed at grid and shared wiring top.

In the manufacture method of thin-film transistor array base-plate of the present invention, in patterning conductor layer and semiconductor material layer, comprise that more with second patterning conductor layer be the cover curtain, remove the etch barrier of segment thickness.

In the manufacture method of thin-film transistor array base-plate of the present invention, when forming contact hole, more comprise the gate insulator that removes segment thickness, in gate insulator, to form a plurality of depressions corresponding to opening.

Description of drawings

Fig. 1 is the diagrammatic cross-section of the storage capacitors of known metal level-insulation course-metal level (MIM) framework.

Fig. 2 is the diagrammatic cross-section of the storage capacitors of known metal level-insulation course-indium tin oxide layer (MII) framework.

Fig. 3 is the schematic top plan view according to a preferred embodiment of the present invention thin-film transistor array base-plate.

Fig. 4 A is the schematic top plan view according to a preferred embodiment of the present invention etch barrier.

Fig. 4 B is the schematic top plan view according to another preferred embodiment etch barrier of the present invention.

Fig. 5 is the schematic top plan view according to another preferred embodiment thin-film transistor array base-plate of the present invention.

Fig. 6 A to Fig. 6 H is the manufacturing process diagrammatic cross-section according to a preferred embodiment of the present invention thin-film transistor array base-plate.

100,200: scan wiring or shared wiring

110,210: gate insulator

120: top electrode

130,220: protective seam

132: contact hole

140,230: pixel electrode

300,300 ': thin-film transistor array base-plate

310: substrate

312: pixel region

320: scan wiring

330: data wiring

340: thin film transistor (TFT)

342: grid

344: semiconductor layer

344 ': semiconductor material layer

346: source/drain

350: etch barrier

350a: strip pattern

350b: frame shape pattern

352: opening

360: pixel electrode

370: shared wiring

380: gate insulator

382: conductor layer

384: ohmic contact layer

390: protective seam

392: contact hole

394: opening

M1: first patterning conductor layer

M2: second patterning conductor layer

R: depression

Embodiment

Fig. 3 is the schematic top plan view according to a preferred embodiment of the present invention thin-film transistor array base-plate.Please refer to Fig. 3, the thin-film transistor array base-plate 300 of present embodiment is made of a substrate 310, a plurality of scan wiring 320, plurality of data distribution 330, plurality of films transistor 340, an etch barrier 350 and plurality of pixel electrodes 360.

In the present embodiment, substrate 310 for example is the substrate of glass substrate, plastic base or other material.As shown in Figure 3, scan wiring 320 is disposed on the substrate 310 with data wiring 330, substrate 310 is divided into a plurality of pixel regions 312.In more detail, scan wiring 320 for example is disposed on the substrate 310 in parallel with each other, data wiring 330 also for example is disposed on the substrate 310 in parallel with each other, and scan wiring 320 for example is perpendicular to one another with the bearing of trend of data wiring 330, substrate 310 is divided into the pixel region 312 of a plurality of rectangles.

As shown in Figure 3, each thin film transistor (TFT) 340 is disposed in the corresponding pixel region 312, and drives by corresponding scan wiring 320 and data wiring 330.In more detail, thin film transistor (TFT) 340 is adjacent to staggered place (intersection) configuration of its pairing scan wiring 320 and data wiring 330, meaning promptly, thin film transistor (TFT) 340 is disposed on the corner in the pixel region 312.In the present embodiment, thin film transistor (TFT) 340 for example is by a grid 342, the semiconductor layer 344 that is positioned at grid 342 tops and 346 formations of source (source/drain).Wherein, grid 342 for example forms simultaneously with scan wiring 320, and source/drain 346 for example forms simultaneously with data wiring 330.

Please refer to Fig. 3 equally, etch barrier 350 configuration scan wirings 320 tops, and etch barrier 350 has plurality of openings 352.In addition, each pixel electrode 360 is disposed in the corresponding pixel region 312, to electrically connect with corresponding thin film transistor (TFT) 340, wherein the subregion of each pixel electrode 360 is coupled as a storage capacitors with corresponding scan wiring 320 respectively by the opening in the etch barrier 350 352, and this storage capacitors system belongs to the storage capacitors of a kind of metal level-insulation course-indium tin oxide layer (MII) framework, and will be specified in back (Fig. 6 A to Fig. 6 H) relevant for the detail sections structure of this storage capacitors.Hold above-mentionedly, the material of pixel electrode 360 for example is indium tin oxide, indium-zinc oxide, or other conductor material.

Fig. 4 A is the schematic top plan view according to a preferred embodiment of the present invention etch barrier, and Fig. 4 B is the schematic top plan view according to another preferred embodiment etch barrier of the present invention.At first please refer to Fig. 4 A, in one embodiment of this invention, etch barrier 350 for example comprises a plurality of strip pattern 350a, and each strip pattern 350a is positioned at corresponding scan wiring 320 tops.Then please refer to Fig. 4 B, in another embodiment of the present invention, etch barrier 350 for example comprises a plurality of frame shape pattern 350b, and each frame shape pattern 350b is positioned at corresponding pixel electrode 360 belows.

Fig. 5 is the schematic top plan view according to another preferred embodiment thin-film transistor array base-plate of the present invention.Please refer to Fig. 5, the thin-film transistor array base-plate 300 ' of present embodiment is made of a substrate 310, a plurality of scan wiring 320, plurality of data distribution 330, plurality of films transistor 340, a plurality of shared wiring 370, an etch barrier 350 and plurality of pixel electrodes 360.Because the thin-film transistor array base-plate 300 ' of present embodiment is structurally similar to the thin-film transistor array base-plate 300 among Fig. 3, so only locate to be described in detail at the difference place of the two.

Please refer to Fig. 5, shared wiring 370 is disposed on the substrate 300, and between two adjacent scan wirings 320.It should be noted that shared wiring 370 and scan wiring 320 form simultaneously.Because the storage capacitors framework on the thin-film transistor array base-plate 300 ' is on shared wiring 370, therefore etch barrier 350 need be disposed at shared wiring 370 tops, etch barrier 350 herein has plurality of openings 352 equally, so that the subregion of pixel electrode 360 can be by the opening 352 of etch barrier 350 be coupled as a storage capacitors with corresponding shared wiring 370, and will be specified in back (Fig. 6 A to Fig. 6 H) relevant for the detail sections structure of this storage capacitors.

Fig. 6 A to Fig. 6 H is the manufacturing process diagrammatic cross-section according to a preferred embodiment of the present invention thin-film transistor array base-plate.Please refer to Fig. 6 A, at first, form one first patterning conductor layer M1 on a substrate 310, the material of this first patterning conductor layer M1 for example is aluminium or other metal.

When making has the thin-film transistor array base-plate 300 (being illustrated in Fig. 3) of storage capacitors on the grid (Cst on gate) structure, the formation method of the first patterning conductor layer M1 for example forms one first conductor layer (not illustrating) earlier on base material 310, afterwards again with this first conductor layer patterning, to form a plurality of scan wirings 320 and a plurality of grid 342 that is connected with scan wiring 320.

When making has the thin-film transistor array base-plate 300 ' (being illustrated in Fig. 5) of storage capacitors on the shared wiring (Cst on common) structure, the formation method of the first patterning conductor layer M1 for example forms one first conductor layer (not illustrating) earlier on base material 310, afterwards again with this first conductor layer patterning, to form a plurality of scan wirings 320, a plurality of grid 342 that is connected with scan wiring 320 and a plurality of shared wiring 370 between two adjacent scan wirings 320.

Then please refer to Fig. 6 B, then go up comprehensive formation one gate insulator 380 and semiconductor material layer 344 ' in the substrate 310 and the first patterning conductor layer M1.Wherein, the material of gate insulator 380 for example is monox, silicon nitride or other dielectric material, and the material of semiconductor material layer 344 ' for example is amorphous silicon (amorphous silicon).

Then please refer to Fig. 6 C, then on the subregion of semiconductor material 344 ', form an etch barrier 350 that is positioned at first patterning conductor layer M1 top.It should be noted that when making has the thin-film transistor array base-plate 300 (being illustrated in Fig. 3) of storage capacitors on the grid (Cst on gate) structure etch barrier 350 is formed at grid 342 and scan wiring 320 tops.And when making had the thin-film transistor array base-plate 300 ' (being illustrated in Fig. 5) of storage capacitors on the shared wiring (Cst on common) structure, etch barrier 350 was formed at grid 342 and shared wiring 370 tops.

Then please refer to Fig. 6 D, then form a conductor layer 382 on semiconductor material layer 344 ' and etch barrier 350, this conductor layer 382 for example is the metal laminated of aluminium/molybdenum/aluminium (Al/Mo/Al) or the single or composite conductor layer that other is suitable.It should be noted that in order to promote the usefulness of assembly, before forming conductor layer 382, optionally form an ohmic contact layer (ohmic contact layer) 384, to improve the contact performance between conductor layer 382 and the semiconductor material layer 344 '.Hold above-mentionedly, the material of ohmic contact layer 384 for example is n type doped amorphous silicon layer (n-type doped amorphous layer).

Then please refer to Fig. 6 E, conductor layer 382, ohmic contact layer 384 and semiconductor material layer 344 ' that patterning is above-mentioned are to form one second patterning conductor layer M2 and a plurality of semiconductor layer 344 that is positioned at etch barrier 350 and second patterning conductor layer M2 below simultaneously.Similarly, ohmic contact layer 384 also can be patterned, and makes ohmic contact layer 384 only be distributed in second patterning conductor layer M2 below.In other words, ohmic contact layer 384 can have identical pattern with the second patterning conductor layer M2.

Please refer to Fig. 6 E equally, in patterning above-mentioned conductor layer 384 and semiconductor material layer 344 ', the etch barrier 350 that is covered by the second patterning conductor layer M2 can not be removed segment thickness, shown in the A among Fig. 6 E, B.

Then please refer to Fig. 6 F and Fig. 6 G; on base material 310, form a protective seam 390; and the protective seam 390 of subregion top that removes the second patterning conductor layer M1 to be to form a plurality of contact holes 392, and protective seam 390, etch barrier 350 and the semiconductor layer 344 of top, subregion that removes the first patterning conductor layer M1 simultaneously is to form plurality of openings 394.In the present embodiment, for example form contact hole 392 and opening 394 in little shadow/etched mode, and after little shadow/etch process, contact hole 392 can expose the second patterning conductor layer M1 of part, and opening 394 can expose gate insulator 380, even the gate insulator 380 of segment thickness can be removed, in gate insulator 380, to form a plurality of depression R corresponding to opening 394.It should be noted that because the existence of etch barrier 350, gate insulator 380 R that only can etchedly go out to cave in, gate insulator 380 can't be by eating thrown or broken hole.

Please refer to Fig. 6 H at last, on base material 310, form plurality of pixel electrodes 360 at last, wherein each pixel electrode 360 electrically connects by the corresponding contact window 392 and the second patterning conductor layer M2, and the subregion of each pixel electrode 360 is coupled as a storage capacitors by the corresponding opening 394 and the first patterning conductor layer M1.It should be noted that gate insulator 380 surface goes up formed depression R and will make the reduced down in thickness of gate insulator 380, and then increase the storage capacitors value of unit area.

In sum, thin-film transistor array base-plate of the present invention and manufacture method thereof have following advantage at least:

1. in the present invention's the thin-film transistor array base-plate, storage capacitors and aperture opening ratio (aperture ratio) all can obtain further lifting.

2. the manufacture method of thin-film transistor array base-plate of the present invention and existing process compatible under the prerequisite of revising technology not significantly, can effectively increase the storage capacitors value of unit area.

Claims

1. A thin film transistor array substrate, characterized in that it comprises:

a substrate;

A plurality of scanning wirings are arranged on the substrate;

A plurality of data wirings are arranged on the substrate, wherein the scanning wirings and the data wirings divide the substrate into a plurality of pixel areas;

a plurality of thin film transistors, each of the thin film transistors is disposed in one of the pixel regions, wherein the thin film transistors are driven by the scanning lines and the data lines;

an etch barrier layer, the etch barrier layer is configured above the scanning lines, wherein the etch barrier layer has a plurality of the openings; and

A plurality of pixel electrodes, each of the pixel electrodes is arranged in one of the pixel regions to be electrically connected with one of the corresponding thin film transistors, wherein a partial area of each of the pixel electrodes passes through the One of them is opened and coupled with one of the scanning lines respectively to form a storage capacitor.

2. The thin film transistor array substrate according to claim 1, further comprising a gate insulating layer disposed between the etching barrier layer and the scanning wires.

3. The TFT array substrate as claimed in claim 2, wherein the gate insulating layer has a plurality of recesses, and each of the recesses corresponds to one of the openings of the etch barrier layer.

4. The thin film transistor array substrate as claimed in claim 2, further comprising a semiconductor layer disposed between the etching barrier layers and the gate insulating layer.

5. The thin film transistor array substrate according to claim 2, further comprising a protection layer disposed on the etching barrier layer and the gate insulating layer, and forming the openings of the etching barrier layer exposed.

6. The thin film transistor array substrate according to claim 1, wherein the etching barrier layer comprises a plurality of striped patterns, and each of the striped patterns is located above one of the corresponding scanning lines .

7 . The thin film transistor array substrate as claimed in claim 1 , wherein the etching barrier layer comprises a plurality of frame patterns, and each of the frame patterns is located below one of the corresponding pixel electrodes.

8. The thin film transistor array substrate as claimed in claim 1, wherein the material of the pixel electrodes comprises one of indium tin oxide and indium zinc oxide.

9. A thin film transistor array substrate, characterized in that it comprises:

a substrate;

A plurality of scanning wirings are arranged on the substrate;

A plurality of shared wirings are arranged on the substrate, and each of the shared wirings is located between two adjacent scanning wirings;

an etch barrier layer, the etch barrier layer is configured above the shared wirings, wherein the etch barrier layer has a plurality of the openings; and

A plurality of pixel electrodes, each of the pixel electrodes is arranged in one of the pixel regions to be electrically connected with one of the corresponding thin film transistors, wherein a partial area of each of the pixel electrodes passes through the One of them is opened and coupled with one of the shared wirings respectively to form a storage capacitor.

10. The thin film transistor array substrate according to claim 9, further comprising a gate insulating layer disposed between the etching barrier layer and the shared wirings.

11. The TFT array substrate as claimed in claim 10, wherein the gate insulating layer has a plurality of recesses, and each of the recesses corresponds to one of the openings of the etching barrier layer.

12. The thin film transistor array substrate as claimed in claim 10, further comprising a semiconductor layer disposed between the etching barrier layers and the gate insulating layer.

13. The thin film transistor array substrate according to claim 10, further comprising a protective layer disposed on the etching barrier layer and the gate insulating layer, and forming the openings of the etching barrier layer exposed.

14. The thin film transistor array substrate according to claim 9, wherein the etch barrier layer comprises a plurality of striped patterns, and each of the striped patterns is located above one of the corresponding shared wirings .

15 . The thin film transistor array substrate as claimed in claim 9 , wherein the etch barrier layer comprises a plurality of frame-shaped patterns, and each of the frame-shaped patterns is located below one of the corresponding pixel electrodes.

16. The thin film transistor array substrate as claimed in claim 9, wherein the material of the pixel electrodes comprises one of indium tin oxide and indium zinc oxide.

17. A method for manufacturing a thin film transistor array substrate, comprising:

forming a first patterned conductor layer on a substrate;

sequentially forming a gate insulating layer and a semiconductor material layer on the substrate and the first patterned conductor layer;

forming an etching barrier layer above the first patterned conductor layer on a partial region of the semiconductor material layer;

forming a conductor layer on the semiconductor material layer and the etch barrier layer;

patterning the conductor layer and the semiconductor material layer to simultaneously form a second patterned conductor layer and a plurality of semiconductor layers below the etch barrier layer and the second patterned conductor layer;

forming a protective layer on the substrate;

removing the passivation layer above a partial region of the second patterned conductor layer to form a plurality of contact windows, and simultaneously removing the passivation layer, the etch barrier layer and the passivation layer above a partial region of the first patterned conductor layer semiconductor layers to form a plurality of openings: and

A plurality of pixel electrodes are formed on the substrate, each of the pixel electrodes is electrically connected to the second patterned conductor layer through one of the corresponding contact windows, and a partial area of each of the pixel electrodes is connected through One of the openings is coupled with the first patterned conductor layer as a storage capacitor.

18. The method for manufacturing a thin film transistor array substrate according to claim 17, wherein forming the first patterned conductor layer comprises:

forming a first conductor layer on the substrate; and

The first conductor layer is patterned to form a plurality of scan lines and a plurality of gates connected to the scan lines.

19. The method for manufacturing a thin film transistor array substrate as claimed in claim 18, wherein the etching barrier layer is formed above the gates and the scanning lines.

20. The method for manufacturing a thin film transistor array substrate according to claim 17, wherein forming the first patterned conductor layer comprises:

forming a first conductor layer on the substrate; and

The first conductive layer is patterned to form a plurality of scan lines, a plurality of gates connected to the scan lines, and a plurality of shared lines between two adjacent scan lines.

21. The manufacturing method of the thin film transistor array substrate as claimed in claim 20, wherein the etching barrier layer is formed above the gates and the shared wirings.

22. The method for manufacturing a thin film transistor array substrate according to claim 17, further comprising using the second patterned conductive layer as a mask while patterning the conductive layer and the semiconductor material layer, moving removing a partial thickness of the etch barrier layer.

23. The method for manufacturing a thin film transistor array substrate according to claim 17, further comprising removing a part of the thickness of the gate insulating layer while forming the contact windows, so that the gate insulating layer A plurality of depressions corresponding to the openings are formed in the center.

24. The method for manufacturing a thin film transistor array substrate according to claim 17, further comprising forming an ohmic contact layer on the semiconductor material layer before forming a conductive layer on the semiconductor material layer and the etching barrier layer. layer on top of the etch barrier layer.