CN1383200A - Design checking method and device of single chip system - Google Patents
Design checking method and device of single chip system Download PDFInfo
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- CN1383200A CN1383200A CN 01115546 CN01115546A CN1383200A CN 1383200 A CN1383200 A CN 1383200A CN 01115546 CN01115546 CN 01115546 CN 01115546 A CN01115546 A CN 01115546A CN 1383200 A CN1383200 A CN 1383200A
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Abstract
This invention relates to a designed method of checking SoC and its device. The device is composed of a method with the following steps: checking each IC core of SoC, using the analog test platform of each core provided by suppliers of silicon IC and core, using the analog checking platform researched by SoC designers and FPGA/emulator with attached logic to check the interface among each core and general line on the core chip and attached logic, checking the timing critical line among cores and SoC and using the SoC bulk analog test platform and applied program to carry on the bulk design check.
Description
Invention field
The invention describes a kind of method and apparatus, it is used for verification and has the design integrity of SoC (monolithic system) IC of a plurality of functions nuclear cores.And more particularly, for SoC design verification method and apparatus, wherein the timing, nuclear of according to the expectation function of each nuclear core, respectively examining in-core between core interface and the work of SoC IC total system, can assess design verification.
Background of invention
In recent years, asic technology from the multichip system theoretical developments to the system-on-a-chip theory that adopts the embedded nuclear core.These system-on-a-chips are by using multi-functional pre-design model, and so-called " nuclear core " (intellectual property just or IP) that serves many purposes makes.These nuclear cores use high level description language (HDL) as Verilog/HDL (being called soft nuclear) usually, or with transistor design such as GDSII (being called stone).Monolithic system is made of jointly stone and soft nuclear, realizes on the sheet function such as microprocessor, large memories array, sound and image controller, modulator-demodulator, the Internet tuner, two and three dimensions graphics controller, DSP function or the like.
Usually, these nuclear cores can be bought from nuclear core supply company there, are integrated SoC of formation then.When the nuclear core was bought from the outside, nuclear core supplier provided plan and nuclear core to intend testboard.Therefore,, needn't anyly change, just can directly use nuclear core testboard to come the work of verification nuclear core in integrated SoC designs the nuclear core is integrated when advancing among the SoC.
At present, describe design with the piece and the sub-piece that use system's level language such as Verilog/VHDL language to form, and utilize performance/door one-level Verilog/VHEL simulator to come board design.Before being designed to silicon IC, such simulation is used to check its actual functional capability.Design verification is a most important and the most difficult task in the SoC design, just can not find and eliminate design mistake because do not carry out the global function verification.Because analog rate is slow and the SoC design scale is big, it almost is impossible that SoC level design verification uses existing tool and method.
Verification is meant to be checked in esse object.For system design, it is meant with regard to specification requirement checks design.In system design, carrying out verification is in order to prove that the conversion from an abstraction hierarchy to another is correct.Purpose be see under actual conditions system realize and create after whether by such work of expection.Monolithic system is meant a hardware components with a plurality of embedded nuclear cores.Therefore, the SoC design verification comprises the verification of examining core, the interconnection verification between the nuclear core and the verification of combined system work.
At present, along with the raising of SoC specification requirement, performance model is also in development, so that can make the simulation test bench that is used for design verification or system works verification.System-level verification is carried out according to design level.At first, the leaf-size class piece in nuclear core one-level, carries out the correctness inspection with independent mode usually.Then, examine the correctness of the interface between core according to transaction types and data content inspection.Next step is to move application software or carry out suitable testboard test on the chip that is fully assembled.This comprises the common verification of hardware/software (M, Keating and P.Bricaud " Reuse methodology manual ", Kluwer Academic Press, 1998; J.Stcunstrub and W.Wolf, " Hardware-Software co-design ", KluwerAcademic Press, 1997).The software verification can only be undertaken by the running time of soft code, therefore, must carry out software and hardware and simulate jointly.Usually, hardware model ASIC (application-specific integrated circuit (ASIC)) form or use FPGA (field programmable gate array) is also developed, and is used for verification is carried out in total system work.
Function check
Fig. 1 has described the method for calibration of using what type on the design of the nuclear core on the different concept hierarchies and each level at present.From the highest concept hierarchy to minimum concept hierarchy, Fig. 1 has provided performance HDL level 21, RTL level (register transfer language) 23, door one-level 25 and structural design level 27.List in corresponding to the method for calibration of these different concepts levels in the square frame 28 of Fig. 1.The fundamental type of verification test is as follows:
(1) whether consistency test, it is consistent with designing requirement to be used for test.
(2) quadrant check, test is in minimum and complex situations under the maximal condition and quadrant situation as voltage, temperature and operation.
(3) random experiment is the driftlessness test that can find very concealed mistake basically.
(4) real sign indicating number test is undertaken by operation actual design application program, so that correct incorrect function.
(5) return test, after any change is done in design, do one group of test.General each mistake fixes on really and needs to add a new test case under the extra test condition.
The development of testboard needs function and the target SoC according to the nuclear core.For example, the processor testboard is carried out the test program based on its instruction group, and bus control unit connects nuclear core (as PCI nuclear core) testboard use bus functional model and bus monitor provides excitation and checks simulation output result.The problem that exists in this method is that performance test bed speed is extremely slow.
After producing test event (excitation or figure), need to check whether the response of output is correct.Now, this manually carries out by observing output waveform, but when design changed, this desk checking method was impossible realize.The method of another kind of verification response output is an operation practical application software, is that software and hardware is simulated jointly basically.This method does not make full use of existing computational resource, thereby efficient is very low.And on this testboard, the actual treatment between nuclear core (core) and application program only accounts for the sub-fraction of whole simulation cycle.Therefore, had only the sub-fraction function check.
The interface verification
In the SoC design, the interface between the nuclear core needs verification.Usually interface has regular address and data structure, and the nuclear core is linked to each other with on-chip bus with nuclear core or nuclear core.This interface also is controlling organization and the signal with certain form, as request/authorized agreement and bus control unit.The regular structure of these interfaces can be determined by data and the control signal sequence of handling limited quantity.
The interface verification needs all possible incident of each interface, thereby this can not finish, because can not produce all possible test event.What therefore, carry out is limited verification.After having done limited verification, next task is that verification nuclear core has correct operation to all data and all data sequences that each nuclear core receives.Such verification also is impossible, therefore, says it is incomplete on the whole body of the present verification of doing, because in single treatment, all different data values are very many.
Timing verification
Timing verification is more difficult than function check.Static timing analysis is present most widely used method.Static timing analysis is the typical chart that is used for adopting the nuclear core that various technological synthesis handle.The use prospect of static timing analysis allows of no optimist, because adopt this method can not correctly reject wrong circuit.Reject wrong circuit employing and manually carry out, therefore, it can't eliminate mistake.The mistake that is modeled as these types of door one-level provides a kind of rational inspection, but it is not a complete solution, because this analogy method needs the time of overspending to produce excitation and simulates all one-level timing circuits.And, in the simulation of door one-level, do not do the timing analysis of worst case, because these analyses are too complicated, quantity is too big, so that the designer can not correctly identify.
Whole SoC design check
The main target of SoC design verification is that the method that adopts the terminal use to use is come the verification whole system.This needs the application of the real system of all functional modes (being hardware model) of examining cores and some.If this is a new system, these application do not have so.Subject matter is analog rate.Such as, even in RTL one-level (register transfer language level), starting the operating system on processor also needs a few hours.In order to improve analog rate, can use two kinds of method: a, concept hierarchy high more, analog rate is fast more; B, simulate or do model with hardware.
Than higher model, the RTL model is as function nuclear core for concept hierarchy, and performance or ISA (instruction set architecture) model is as memory and processor core core, and bus functional model and monitor produce with communication block and the inspection incident.For SoC such as intermediate processor, certain application code that produces in simulated environment is used for SoC.When adopting application software, what almost can not do, it is only limited to checks that silicon works or inoperative fully, and finds basic problem.At present, by on communication interface, using the method for sequence checking device/monitor or bus monitor manually to find mistake.Yet analog rate is very slow, and approximately 10 cycles of per second, this is too slow so that can't do any application.
When while analog hardware and software, so-called common simulation that Here it is.Come analog hardware with a C language function, carry out whole system just as C programmer of operation.Yet this is not a design verification, because this is not to realize on the layer, but feasibility study or performance verification.HDL/RTL describes and is used for the whole system verification, because it represents the realization of hardware components.Common simulation needs communicating by letter between one or more HDL simulators and the C/C++ program (need compiler, installation procedure, chain program and from other programs of computer operating system).Therefore, another problem in the common simulation is the communication issue between the different simulators.
Hardware model
All design troops all attempt to make one-level silicon to play a role fully, but design over half has all been failed when being applied to this silicon in the system first.This is owing to lack the verification of system's one-level or the design verification of SoC one-level.In order to ensure obtaining success first, should carry out more practical application simulation.Because simulated time is oversize, unique actual solution is to use exaflex injection type at present, though it is expensive very big.Available techniques is FPRA/LPGA and emulation.
Do design on a small scale, can make FPGA (field programmable gate array) or LPGA (laser programmable gate array) model.Though FPGA and LPGA lack the speed of door tally function and ASIC, they can make small nut core or fritter, and can not be used for whole body SoC.Several FPGA can be interconnected on the circuit board, and the SoC model that is used to form a whole.In this case, need cut apart the SoC chip again if pinpoint the problems, the interconnection between FPGA will change so, need a new boards, and it is expensive therefore changing, and need a large amount of time.
Emulation technology provides a selectable method for a collection of FPGA that is used for large chip, and it provides programmable interconnect, fixed head design, big relatively door numeration and special memory and processor support program.If global design is applied on the replicating machine, simulation velocity can be faster than analog rate.Yet, to compare with actual silicon, its execution speed is still very slow.If quite a few input main frame of chip data or testboard data, simulation performance can reduce greatly.Another shortcoming of this method is its expense.At present, the price of commercial analogue system is all more than 1,000,000 dollars.
When design scale is too big (millions of transistors), unique available method is to set up an actual silicon model and debugging final system at present.In this case, use same silicon can reject the first few mistake, and do not need to add new silicon.2～3 silicon process-cycles of whole process need, and every increase process-cycle can improve the development cost of entire product greatly.
As previously described, with regard to performance, expense and speed, prior art can not be tested effectively with verification SoC and be designed.Therefore, semicon industry needs an energy at a high speed, low expense to carry out the new method and the device of SoC design verification completely.
Brief summary of the invention
Therefore, an object of the present invention is to provide a kind of SoC design verification method and apparatus, this method and apparatus can carry out SoC design verification completely with regard to the interconnection of each function, nuclear of examining core between core, the performance of total system.
Another object of the present invention provides a kind of SoC design verification method and apparatus, and this method and apparatus can at a high speed, low expense carry out SoC design verification completely.
Another purpose of the present invention provides a design verification station, and wherein carrying out the SoC design verification is in order to verify the whole body function of SoC.
Another purpose of the present invention provides a kind of SoC design verification method and apparatus, and than existing system, this method and apparatus can make the user more easily debug the nuclear core of SoC.
The invention provides a kind of design verification or global function verification new method and device, this method and apparatus has solved the existing difficulty of design verification of the embedded nuclear core in the monolithic IC system.The inventor is referred to as the design verification station, because it is used to the whole body function of verification SoC.The system configuration of describing during this uses is very effective, compares with previously described any system, and expense is lower and fundamentally different.
One aspect of the present invention is a kind of design verification method, and this method is used for the integrated functionality nuclear core of a plurality of embeddings of verification SoC.The method comprising the steps of: the simulation test bench that silicon IC by using each nuclear core and nuclear core supplier provide, come verification to be integrated in and respectively examine core among the SoC; By the simulation test bench of use SoC designer development and the FPGA/ simulator of subsidiary logic (gluelogic), come verification respectively to examine the interface between core, the on-chip bus and the subsidiary logic of nuclear core; Verification nuclear core is to the timing of nuclear core and the critical route of timing (critical path) of SoC level; Carry out the master-plan verification by simulation test bench and the application program of using whole SoC.
The present invention is a kind of SoC design verification device on the other hand.This device comprises: a main system computer is used for carrying out with the user integrated operation of interface and controlling Design calibration equipment; A plurality of verification unit, it receives the testboard data of autonomous system computer, and utilizes this testboard data generation to be used for testing the test pattern (pattern) that a plurality of functions of wanting the integrated SoC of advancing are examined cores; And a system bus, it links to each other a plurality of verification unit with the main system computer.In this device of the present invention, a plurality of silicon IC are connected with verification unit, to receive test pattern from verification unit, and generation response output, this output is assessed by verification unit and main system computer, wherein silicon IC have one with the function nuclear identical internal structure of core and the function that are integrated among the SoC.
The figure brief introduction
Figure 1 shows that concept hierarchy and corresponding check method in core design of function nuclear and the design verification.
Fig. 2 is a flow chart, shows global concept and the design verification process of the monolithic system IC corresponding with the present invention.
Fig. 3 is a general block diagram, shows design verification global concept of the present invention, and it comprises a correlation between electric design automation (EDA) environment and the design verification of the present invention station.
Fig. 4 A is a block diagram, and it is the SoC that the EDA environment among Fig. 3 designs down, and block diagram shown in Fig. 4 B is a basic structure at design verification station among Fig. 3.
Block diagram shown in Figure 5 is the very detailed structure illustration of of design verification of the present invention station, comprising a plurality of verification unit.
Block diagram shown in Figure 6 is a kind of structure of the verification unit among Fig. 5, and it has one based on event tester.
Block diagram shown in Figure 7 is a kind of verification unit structure, and this verification unit is used for assessing the subsidiary logic that SoC is in test mode.
Block diagram shown in Figure 8 is another kind of verification unit structure, and this verification unit is used for assessing the subsidiary logic that SoC is in test mode.
Block diagram shown in Figure 9 is another design verification station of the present invention, and it supports the advanced application language.
Block diagram shown in Figure 10 is another design verification station of the present invention, and this chart understands to have a structural relation that the execution plate of function nuclear core to be tested is installed.
Block diagram shown in Figure 11 is another design verification of the present invention station, and wherein a plurality of verification unit are directly received the main system computer control.
The detailed introduction of preferred embodiment
The overall flow of SoC design verification method of the present invention is seen shown in Figure 2.This method of calibration is come according to the systematic procedure of 4 steps: core is respectively examined in verification; The verification interface comprises on-chip bus and subsidiary logic; Verification regularly; The overall system performance of terminal check SoC.
More specifically, in the step, checking routine at first comes verification respectively to examine core by the functional test desk that uses silicon IC and nuclear core at S31.Then, program running is to next step S32, comes interconnection between verification nuclear core by the FPGA/ simulation unit of using subsidiary logic, comprises the function of on-chip bus and the function of subsidiary logic.In next step S33, by using simulation test bench and the SoC level critical route of nuclear core to the communication of nuclear core, the timing that comes verification nuclear core.In the end among the step S34, carry out the design verification of whole body SoC by using global function simulation test bench and operation application software.
Method of the present invention is to realize by device shown in Figure 3, this device shown new test macro global concept and with electric design automation (EDA) environmental relation.The upper left side of Fig. 3 is EDA, here, and utilization cad tools designing semiconductor equipment such as SoC 43.The lower right of Fig. 3,50 realize the present invention at the design verification station.The SoC design verification is carried out based on the design data that produces in test data and SoC 43 design environments in design verification station 50.Wherein, not only to test the silicon IC of each the integrated nuclear core that has among the SoC, and will test SoC 43.
In this example, SoC 43 comprises function nuclear core A, B and C, and more detailed structure is seen Fig. 4 A.Behind 41 times designs of EDA environment SoC 43, just obtain a design data file 45 and a test data file 53.Through various data conversion treatment, design data 45 is converted into physical level (level) data of representing each, the semiconductor integrated circuit that these formations design.According to the physical level data, actual SoC 49 results from the semiconducter IC course of processing (silicon process).Yet, among the present invention, not the direct complete SoC of test, respectively examine core but in design verification station 50, use represent among the SoC 43, as examining the independent IC of core A, B, C.
By the test data 53 that the 54 usefulness SoC design phases of testboard obtain, come the actuating logic simulation, produce a data file 55 as the Verilog/VCD file, it has shown input one output relation of respectively examining core and/or SoC total system.Explain that as following data in the VCD file 55 are incident forms.Data in the VCD file 55 are sent in the incident file 58 in the design verification station 50.Design verification station 50 comprises one group based on event tester 59 (verification unit 66 among Fig. 4 B), and this group is carried out test based on event tester with the program of mentioning among Fig. 2.
A basic structure at design verification station 50 sees shown in the sketch 4B that it is used for the common development/verification of software/hardware.This design verification station 50 comprises a plurality of verification unit (VU) 66
1～66
N, can reconfigure these verification unit according to the pin of equipment to be tested.These calibration equipments 66
1～66
NBe assigned to silicon IC68
1～68
N, these silicon IC has function and the circuit structure that SoC to be assessed goes up corresponding integrated nuclear core A～N.
The integral implementation of main system CPU 62 control checking routines, it and verification unit 66
1～66
NLink to each other by system bus 64.Before checking procedure begins, offer main system CPU 62 examine design data 61 and the testboard data 63 of the design phase of core A～N from each.
The more detailed description at design verification station 50 is seen Fig. 5, wherein for ease of explanation, the design verification station is expressed as one group of design verification station DVS
1～DVS
6This fact shows so a kind of situation: assess the SoC with nuclear core A～E and subsidiary logic with its design certainty.In this example, configuration verification center DVS
1Test " bus master examines core " (nuclear core A), configuration verification center DVS
2Test " processor core core " (nuclear core B), configuration verification center DVS
3And DVS
4Test " specific function nuclear core " (nuclear core C and D), configuration verification center DVS
5Test " memory core core " (nuclear core E).Similarly, configuration verification center DVS
6Test the subsidiary logic among the SoC.Among the present invention, for ease of design verification, the above-mentioned nuclear core A～E that mentions is at silicon IC68 independently
1～68
5In systematic statement.
As Fig. 4 B and shown in Figure 5, system comprises bus structures.System bus 64 can be an Industry Standard Architecture, and as VME, VXI or pci bus, it allows data to be sent to verification unit 66 from main system CPU 62
1～66
5Each pin.System's pin can be disposed by the user, that is to say, the user can examine the silicon IC68 of core A～E according to each
1～68
5I/O the test pin of verification unit is classified.Silicon IC68
1～66
5The electronic equipment and the equipment that are installed in pin load plate (being " electronic equipment of pin " from now on) 69
1～69
5On, and interconnect by interconnect bus 71.
As shown in Figure 5, each pin group (branch is tasked verification unit) also comprises a Controlled CPU 67, and it is used for control data stream, examines core 68 to silicon
1～68
5Analogue data application, response ratio, arrange different tasks and supervision for each piece/nuclear core and respectively examine the state of core and SoC.Controlled CPU 67
1～67
6Interconnect, and link to each other with main system CPU by bus system 64.In the design verification station DVS of subsidiary logic, a clock synchronization unit 75 and an arbitration unit 76 are arranged, be used to promote data to pass to main system CPU 62 and design verification station DVS
1～DVS
6Controlled CPU 67
1～67
6In, or promote that data send.
Before checking procedure began, main system CPU 62 installed each testboard data 78, and gives verification unit 66 this data allocations
1～66
5This main system CPU 62 controls overall process in design verification, comprising: user interface, be the overabsorption control of common verification operation application software and verification unit on the nuclear core of design.In each design verification station DVS, verification unit 66 is given the silicon IC68 of nuclear core correspondence the test pattern that forms based on the testboard data.Further, each verification unit 66 is as using based on event tester, has introduction below these.
Incident (test pattern) is applied on the DUT by the pin electronics equipment 69 of Fig. 5.In fact pin electronics equipment 69 link to each other the designated equipment pin of test pin with their silicon IC68 (DUT).Basically, pin circuit equipment 69 comprises an interface circuit that connects verification unit 66 and silicon IC68 to be tested.For example, each interface circuit is made up of execution plate, one or more driver and a comparator (not drawing among the figure).Driver is for test pattern being delivered to the input pin of DUT, and comparator compares response output and the desired value of DUT.The execution plate is used for connecting the DUT in the test.
The verification of single nuclear core
Among the present invention, respectively examine core A～E, used the silicon IC68 that respectively examines core for verification
1～68
5This silicon IC68 is generally from nuclear core supply company and their processing cooperative venture.As Fig. 4 B and shown in Figure 5, the reorganization whole system, each nuclear core distributes a verification unit 66.Be verification, loading has the testboard of respectively examining core of the I/O information of respectively examining core to main system CPU 62.
Be arranged in after main system CPU 62 reconfigures system's pin in the verification unit 66 of each nuclear core, and assign a Controlled CPU 67.Should be noted that in order to improve systematic function with Controlled CPU 67 of each pin assignments, rather than the mode that each verification unit 66 is joined a Controlled CPU 67 realizes.This way directly and has at all improved the performance of the system among Fig. 4 B and Fig. 5, and specific practice is not described here.
Based on the I/O of nuclear core, the configuration of verification unit 66 can be 64～256 (2
NForm) any one between individual number of pins.Basically, these pins are based on the event tester passage, and it allows to drive/compare operation.Allow this of pin to reconfigure as Fig. 4 B and system shown in Figure 5, and they are arranged in respectively examine on the core.Therefore, in essence, whole system is configured in a plurality of verification unit 66, and each verification unit is distributed to an IP or nuclear core, as shown in Figure 5.Therefore, concerning each nuclear core, the VU66 of assignment is the incident check system of a special use.At the patent application number be: described an incident check system in 09/406300 the United States Patent (USP) " based on the semiconductor test system of incident ", can simply describe below.The event simulation vector (do function and structure inspection with) of nuclear core can be used for examining core (silicon IC68), and its response energy observes, and compares by this VU66 and analogue data.
For examining core function and timing verification, main system CPU 62 sends the simulation test bench data of nuclear core to the Controlled CPU 67 of relevant verification unit 66.These data are design one simulation test values of this nuclear core, it comprise signal value and timing information with identification when signal value situation of (incident test pattern) during from 0 → 1 or 1 → 0 variation.Therefore, needn't change, these data can directly apply to nuclear core silicon 68.
Because these data are design simulation data, zero defect nuclear core can proper operation the same just like simulation.This response can be observed and be compared by Be Controlled CPU 67 in verification unit 66.Any deviation of simulation can be detected by Controlled CPU 67.This has guaranteed that any defective among the nuclear core IC on any verification unit 66 can both be detected.This step has guaranteed that before SoC level design verification, the silicon IC of the nuclear core on the verification unit 66 is flawless.
Should be noted that: than existing system, it is easier that this method and apparatus of the present invention also makes when the user debugs the nuclear core.This be because: use event data, existing check system environment is identical with original design simulated environment (being the EDA environment).
Verification unit (incident is surveyed device)
As mentioned above, each verification unit 66 among the present invention is configured to one based on event tester.Like this one has simple declaration based on event tester in Fig. 6.The more detailed description sees that the patent No. above-mentioned is 09/406300 United States Patent (USP) " based on the semiconductor test system of incident ", and this patent belongs to same assignee of the present invention.In based on event tester, when signal from 0 → 1 or when 1 → 0 changes, test pattern is described as the time span parameter with respect to reference point.In the test data in common cycle, test pattern is described with the generated data of timing data, Wave data and the vector data of each test period.When the semiconductor equipment actuating logic that designs was simulated, because existing design automation tool produces the incident test data, therefore, event test system can directly be used the analogue data of semiconductor equipment design phase generation.
In the example of Fig. 6, verification unit 66 comprises that the Controlled CPU 67 and the verification unit that are connected on pin-unit (system) bus 63 write decoder 83, an internal bus 85, an address sequence generator 88,90, one decompress(ion) unit 92 of 87, one event memories of a fault memorizer, timer counter and adjust logic 93, and an incident generation unit 94.Verification unit 66 offers test pattern by pin electronics equipment and has the silicon IC68 that examines core.
Verification unit is write decoder 83 and is used to discern verification unit 66, so that main system CPU 62 can dispose verification unit 66 for system bus 64 by transmitting one group of address through selection.Internal bus 85 be hardware based on a bus in the event tester, link to each other with most of functional blocks usually, as address sequence generator 88, fault memorizer 87, decompress(ion) unit 92, timer counter and adjustment logic 93 and incident generation unit 94.
As mentioned above, Controlled CPU 67 is sent instruction based on other the functional block of the nuclear core testboard data of coming autonomous system CPU 62 in verification unit 66.Fault memorizer 87 store test results are as from the fault message of the nuclear core silicon IC68 of comparator (not shown) and the address signal that address sequence generator 88 provides.The information in the fault memorizer 87 of being stored in is used to examine the accident analysis stage of core and SoC.
Address sequence generator 88 provides address date for event memory 90.Event memory 90 each timing of events data of storage.Such as, event memory 90 with two kinds independently mode store event data, a kind of mode is the timing data of control (reference) clock cycle of storage integral multiple, and another kind of mode method is the fractional part of stored reference clock cycle or the timing data of several fractional parts.
Further, the timing data in the event memory 90 is compressed to reduce memory space.The packed data that decompress(ion) unit 92 receives from event memory 90 is by decompress(ion) programe reduction timing data.The decompress(ion) timing data is provided for timer counter and adjusts logic 93.
Timer counter and adjustment logic 93 serve as according to producing existing incident with the timing data from event memory 90.By last timing data is obtained whole timing data in the Calais mutually with existing timing data.Timer counter and adjustment logic 93 can be revised timing data according to scale factor.This zoom operations of timing data comprises according to scale factor increases timing data (each △ t or absolute time).Incident generation unit 94 is a foundation with the whole timing data that comes from timer counter and adjustment logic 93, produces the real-time event signal.Incident generating unit 94 offers pin electronics equipment 69 to event signal (test pattern).
The verification of interface, on-chip bus and subsidiary logic
Most of SoC design comprises the design in advance of examining core, is that nuclear core integrator (SoC designer) designs yet integral body has certain logic, so that carry out some very special functions and be connected different nuclear cores.This logic is commonly referred to " subsidiary logic ".Generally, subsidiary logic realized by cases of otherwise standard design, yet, embed recently that FPGA (field programmable gate array) is recommended to be used for realizing this logic.As mentioned above, with prior art, can only carry out rough, incomplete verification to this logic.
With the method for suggestion, the verification of this logic is the design verification station DVS by the subsidiary logic of verification shown in Figure 5
6In special-purpose subsystem carry out, basic skills is as follows:
(1) use interconnect bus 71 that each the silicon IC68 among Fig. 5 is coupled together with modelling SoC on-chip bus.This is a system bus, and it couples together each nuclear core A～E, the action that comes the modelling on-chip bus by this nuclear core.This bus becomes the instruction and data of SoC one-level stream (examining core to another from a nuclear core) the instruction and data stream (from a VU to another VU) of design verification station one-level.Therefore, this bus has any request/authorized agreement of SoC on-chip bus and examines all data processing of core interface at each.
(2) use FPGA realizes the subsidiary logic on the special-purpose subsystem.Other method is the subsidiary logic of simulation on special-purpose subsystem.These two kinds of methods are seen Fig. 7 and Fig. 8 respectively.
Figure 7 shows that the simulator subsystem.In the method, can use any commercial simulation system.Among Fig. 7, the test data in the synthesized RTL of the subsidiary logic of having packed in the simulator 72 and the subsidiary logic testing file 77.For this simulator subsystem is linked to each other with other verification unit 66, use commercial simulator to do clock synchronization unit and arbitration unit.Controlled CPU 67 is carried out clock alignment and communication task with main system CPU 62.
Figure 8 shows that the FPGA method.In this method, the design of subsidiary logic realizes by using FPGA 73, and FPGA 73 is regarded as a silicon IP or nuclear core.Realize subsidiary logic if utilize to embed FPGA in SoC, this FPGA 73 embeds one of FPGA (subsidiary logic) independently duplicate exactly so.This FPGA 73 is used as independently IP and distributes to special-purpose verification unit.
If realize subsidiary logic by cases of otherwise standard design in SoC, the RTL of so subsidiary logic can realize on single FPGA that this FPGA is used on the special-purpose VU.With this understanding, in most cases, the speed of FPGA is slower than the non-standard subsidiary logic among the SoC.Therefore, clock synchronization unit 75 and the bus arbiter unit 76 that need add of this special cell.Except service speed slowly, this VU and other VU are identical, and its operation is also identical with other VU.
Timing verification
In case respectively examined function, interface and the subsidiary logic verify of core, just can carry out timing verification to the critical route of SoC one-level.It should be noted: after finishing the step 31 and 32 among Fig. 2, all each several parts of SoC and be interconnected in design verification of the present invention station and all can obtain.The function of single nuclear core and the verification of subsidiary logic, and respectively examine the also verification of timing of core.Therefore, the simulation test bench of SoC one-level and overall applicability program all can be used for total system, just in case what mistake is arranged, but also ascertainment error is present on nuclear core integrated.
In the described method of invention, preferably move the simulation vector (test data) of a spot of SoC one-level.This vector is used for the critical route of timing and the nuclear core one nuclear core correctness regularly of verification SoC one-level.For this reason, the simulation test bench of SoC one-level is installed on the host CPU.In the design of SoC, develop the critical route of timing that such simulation test bench is used for the verification design.These test datas (vector) are the incident forms, with present technology, generally can obtain the data of VCD form, and this VCD form come from the Verilog/VHDL simulator.
The vector value of testboard data is used for checking SoC to connect the critical route of each timing of SoC each several part.As describing, design verification of the present invention station comprises all parts of SoC, can predict, and can carry out and generation and the identical result of simulation program as the simulation test bench that timing verification is used.Arbitrarily the deviation of analog result is represented a mistake, this mistake with the design simulation environment facies with event context of the present invention in be easy to debugging.
SoC verification or global design verification
For carrying out the global function verification of SoC system, carry out the SoC level function vector that produces during design one simulation at the verification center.These vectors also are the incident forms.Usually, these vectors produce (Verilog/VHDLRTL model or performance model) by SoC design application software.Yet the different piece of SoC is checked on these vector whiles or different time ground, so that utilize Whole Response to judge the overall performance of SoC.
When application program is write with high-level language such as C/C++ language or binary form, need API (application programming interfaces) and PLI (program language interface) to come these programs are packed among the main system CPU 62, and need them that the external world and main system CPU 62 are connected, as shown in Figure 9.
In order to accomplish this point, main system CPU 62 utilize multiple bus protocol (as Fig. 5 and shown in Figure 9 many-BP) carry out multiple distributed control.It go up to carry out one at application task (application software) " branch " operation, application task is divided into a plurality of subtasks, for arranging the time and they are distributed to the VU66 that different correspondences is respectively examined core in each subtask.It should be noted: this " branch " and operation run on high-level language such as Verilog/VHDL or even the application software of C/C++ language compilation on.Therefore, for carry out application task in the appointment computing environment of being made up of a plurality of verification unit 66, the system's compiler with multiple distributed control is carried out the application task " branch " operation.
At this " branch " operation after, each VU66 is distributed to by system bus 64 in the subtask.Controlled CPU 67, arbitration unit 76 and clock synchronization unit 75 allow to communicate by letter and error-free received data is sent to the Controlled CPU 67 of each VU66 from main system CPU 62.This structure with main system CPU 62, arbitration unit 76 and clock synchronization unit 75 is seen Fig. 9.
Assign based on the subtask, Controlled CPU 67 is applied to respectively examine core to event vector, and gathers response therefrom.Then, utilize Controlled CPU, bus arbiter unit and clock synchronization unit to transmit correct data once more, this response is delivered among the main system CPU 62.This main system CPU 62 carries out " synthesizing " operation, to merge different responses and to form the SoC Whole Response.This response and analog response are made comparisons, to determine whether proper operation of SoC.If this is an application software, this response is the expected results of application program so.For example Video Applications running software result is a figure.The deviation of the application of any analogue data or expection output all can be identified by main system CPU 62, and the designer can debug at an easy rate, because same with the original design environment facies based on the environment of incident.
Fixture or execution plate
Design verification of the present invention station needs one to carry out plate, can examine core 68 to silicon by this plate and link to each other with subsidiary logic FPGA.In the example of Fig. 5～Fig. 9, each nuclear core provides an apparatus mounting plate or carries out plate 69 (a design verification station DVS).The block diagram of Figure 10 has provided another structure of carrying out plate.Among Figure 10, each is carried out plate 90 and comprises nuclear core and the subsidiary logic that all are to be tested.Connector 95 is examined between the core 68 with silicon at VU66 and is used to be connected both.
It is closely similar with the execution plate of testing apparatus commonly used that this carries out plate 90, and that is a multilayer printed circuit board.The main difference of carrying out plate 90 and testing apparatus execution plate is: testing apparatus is carried out on the plate has only a DUT, and comprises the silicon IC68 and the subsidiary logic FPGA of all nuclear cores on the execution plate 90 in the design verification of the present invention station.
Figure 11 is another design verification station of the present invention, and wherein a plurality of verification unit are directly by the main system computer control.In this example, be different from each example of front, each design verification station does not comprise Controlled CPU, but is directly controlled by main system computer 62 by system bus 64.Therefore, the response assessment of all tasks such as clock alignment, nuclear core, timing assessment and whole SoC assessment or the like are all done by main system computer 62.
Though only a concrete example is carried out specific description and description here, but under the prerequisite of spirit of the present invention and desired extent, according to above-mentioned guidance and in the scope of appended claim, the present invention is done some modifications and change is fully passable.
Claims (33)
1, a kind of design verification is based on the method for the SoC (Single Chip Microcomputer (SCM) system) of embedded nuclear core, and this method may further comprise the steps:
What the integrated SoC of advancing was wanted in verification respectively examines core, is undertaken by the simulation test bench that uses the silicon IC that respectively examines core and nuclear core supplier to provide;
Come verification respectively to examine the interface between core, on-chip bus and subsidiary (glue) logic of nuclear core by the simulation test bench of use SoC designer development and the FPGA/ simulator of subsidiary logic;
The timing between verification nuclear core and the critical route of timing of SoC level; And
By using whole SoC simulation test bench and application software to carry out the global design verification,
2, design verification method as claimed in claim 1, wherein checking procedure is to carry out after a plurality of verification unit are distributed to the silicon IC that respectively examines core.
3, design verification method as claimed in claim 1, wherein checking procedure is to carry out after a plurality of verification unit are distributed to the silicon IC that respectively examines core, wherein the test pin of verification unit is configured with reference to the I/O pin of silicon IC to be tested.
4, design verification method as claimed in claim 1, wherein checking procedure is to carry out after a plurality of verification unit are distributed to the silicon IC that respectively examines core, wherein each verification unit is configured to one based on event tester, this tester produces test pattern based on event data, and event data is described test pattern with numerical value change amount and timing.
5, design verification method as claimed in claim 4, the simulation test bench of wherein respectively examining core has a data format based on incident, and therefore, utilization verification unit (based on event tester) is easy to debug mistake in the nuclear core of SoC.
6, a kind of design verification is based on the method for the SoC (Single Chip Microcomputer (SCM) system) of embedded nuclear core, and this method may further comprise the steps:
Produce a plurality of silicon IC, each all has the circuit structure of the correspondence nuclear core of wanting on the integrated SoC of advancing;
A plurality of verification unit are provided, and each verification unit are distributed to the silicon IC of each nuclear core;
By interconnect bus silicon IC is interconnected, and modelling in SoC, design be used to connect the on-chip bus of respectively examining core;
Export verification to want nuclear core among the integrated SoC of advancing by application testing pattern on silicon IC and the response that monitors silicon IC;
Wherein directly produce test pattern by the simulation test bench that uses nuclear core supplier to provide.
7, design verification method as claimed in claim 6 also comprises a step: by simulator analog interface and subsidiary logic, come verification to want interface and subsidiary logic between the integrated SoC of advancing center core.
8, design verification method as claimed in claim 6 also comprises a step: realize interface function and subsidiary logic by utilizing field programmable gate array (FPGA), come verification nuclear to want interface and subsidiary logic between the nuclear core of the integrated SoC of advancing.
9, design verification method as claimed in claim 6 also comprises a step: provide the test and excitation that produces based on whole SoC level testboard data by the silicon IC to each nuclear core, come timing and the critical route of SoC level timing between verification nuclear core.
10, design verification method as claimed in claim 6 also comprises step: by simulation test bench and the application working procedure that uses whole SoC, carry out the global design verification.
11, design verification method as claimed in claim 6, wherein checking procedure is to carry out after a plurality of verification unit are distributed to the silicon IC that respectively examines core.
12, design verification method as claimed in claim 6, wherein checking procedure is to carry out after a plurality of verification unit are distributed to the silicon IC that respectively examines core, wherein each verification unit is configured to one based on event tester, should produce test pattern based on event data based on event tester, this event data is described test pattern by data variation amount and timing.
13, design verification method as claimed in claim 12, the simulation test bench of wherein respectively examining core has a data format based on incident, and therefore, utilization verification unit (based on event tester) is easy to debug mistake in the nuclear core of SoC.
14, design verification method as claimed in claim 6, wherein checking procedure is to carry out after a plurality of verification unit are distributed to the silicon IC that respectively examines core, wherein the test pin of verification unit is to be configured at the I/O pin with reference to silicon IC to be tested.
15, a kind of design verification wherein is integrated with a plurality of function nuclear cores based on the device of the SoC (Single Chip Microcomputer (SCM) system) of embedded nuclear core in this SoC, and this device comprises:
A main system computer, the integrated operation of it and user interface and controlling Design calibration equipment;
A plurality of verification unit, it receives the testboard data of autonomous system computer, and utilize these testboard data to produce and be used to test the test pattern that a plurality of functions of wanting the integrated SoC of advancing are examined cores, wherein have a reception to come the control computer of the testboard data of autonomous system computer in each verification unit; And
A system bus is used for a plurality of verification unit and main system computer are carried out interface;
Wherein a plurality of silicon IC link to each other with verification unit, with the test pattern of reception from verification unit, and produce response output, and this response output is assessed by verification unit and main system computer; And wherein silicon IC have one with SoC in integrated functionality nuclear core internal structure completely.
16, design verification device as claimed in claim 15, wherein the control computer based in each verification unit is that the silicon IC that distributes to verification unit produces test pattern and the response output of silicon IC is assessed in the testboard data that come from the main system computer through system bus.
17, design verification device as claimed in claim 15, wherein each verification unit is assigned to a silicon IC.
18, design verification device as claimed in claim 15, wherein each verification unit is assigned to a silicon IC, and wherein the I/O pin of the test pin reference silicon IC to be tested of verification unit is configured.
19, as the design verification device of stating of claim 15, wherein each verification unit has one group of test pin, and the mount structure of the pin configuration of verification unit foundation silicon IC to be tested can arbitrarily change.
20, design verification device as claimed in claim 15, wherein each verification unit has one group of test pin, the mount structure of verification unit can arbitrarily change according to the pin configuration of silicon IC to be tested, and wherein the size of pin group is determined by main system CPU according to the I/O pin number of distributing to the silicon IC of verification unit.
21, design verification device as claimed in claim 15, wherein each verification unit has a control computer, this control computer receives the testboard data that come from the main system computer by system bus, and produce test pattern to the silicon IC that distributes to this verification unit, assess the response output of silicon IC then.And wherein each test pin at verification unit all is provided with a control computer.
22, design verification device as claimed in claim 15, wherein the silicon IC of verification unit evaluate assign examines core with the verification function corresponding; And verification unit is wanted interface and subsidiary logic between the silicon IC among the integrated SoC of advancing by simulator analog interface and subsidiary logic evaluation.
23, design verification device as claimed in claim 15, wherein verification unit assessment distributed silicon IC with verification function corresponding nuclear core; And verification unit is assessed interface and subsidiary logic between the silicon IC that wants among the integrated SoC of advancing also by using the field programmable gate array to realize interface function and subsidiary logic.
24, design verification device as claimed in claim 15, wherein main system computer and verification unit provide based on SoC level testboard data by the silicon IC that respectively examines core to representative and produce test and excitation, come regularly critical route of timing between verification nuclear core and SoC level.
25, design verification device as claimed in claim 15, wherein main system computer and verification unit are come the verification global design by using whole SoC simulation test bench and application program.
26, design verification device as claimed in claim 15, wherein main system computer and verification unit are come the verification global design by simulation test bench and the application program of using whole SoC; And wherein the main system computer is by being divided into calculation task a plurality of subtasks and with distributed way these a plurality of verification unit being distributed in each subtask and give each verification unit the SoC application computes Task Distribution of separating.
27, design verification device as claimed in claim 15, wherein main system computer and verification unit are by using whole SoC simulation test bench and application checks global design; And wherein the main system computer is by being divided into calculation task a plurality of subtasks, and with distributed way these a plurality of verification unit distributed in each subtask and come to give each verification unit a SoC application software distribution of computation tasks of separating; And wherein the silicon IC of the incompatible self checking of host level unit response with the Whole Response that forms SoC wrong to determine whether/fault.
28, design verification device as claimed in claim 15 comprises that is also carried out a plate, and this plate carries silicon IC corresponding in each verification unit.
29, design verification device as claimed in claim 15 comprises that is also carried out a plate, and this plate carries all silicon IC and subsidiary logic to be tested.
30, design verification device as claimed in claim 15, wherein each verification unit is configured to based on event tester, and this tester produces test pattern according to event data, and this event data is described test pattern with numerical value change and timing thereof.
Therefore 31, design verification device as claimed in claim 30, the simulation test bench of wherein respectively examining core has a data format based on incident, utilizes verification unit (based on event tester) to be easy to debug mistake in the nuclear core of SoC.
32, design verification device as claimed in claim 15, wherein each verification unit is configured to comprise based on event tester:
An event memory is used to store each timing of events data, and this timing data is that the fractional part (fractional part data) by integral multiple of reference clock cycle (integer part data) and reference clock cycle forms.This timing data is the time difference between predetermined reference point and the current event;
The address sequence generator produces the address date that is used for the access event memory;
An event count logic produces an incident initial signal, and this signal has been delayed the reference clock cycle that has multiplied each other with these integer part data;
An incident generating unit is according to from the incident initial signal of event count logic be used to show that the fractional part data of this test pattern produce each incident; With
A verification unit is write decoder, is used to seek the address of verification unit, so that this verification unit is distributed to the pin of silicon IC.
33, a kind of design verification wherein is integrated with a plurality of function nuclear cores based on the device of the SoC (Single Chip Microcomputer (SCM) system) of embedded nuclear core in this SoC, and this device comprises:
A main system computer is used for integrated operation with user interface and controlling Design calibration equipment;
A plurality of verification unit receive the testboard data of autonomous system computer, and utilize this testboard data generation to be used for testing the test pattern that a plurality of functions of wanting the integrated SoC of advancing are examined cores; And
A system bus links to each other the main system computer interface to these a plurality of verification unit;
Wherein a plurality of silicon IC link to each other with verification unit, will be by the response output of verification unit and main system computer evaluation from the test pattern and the generation of verification unit so that receive; And wherein silicon IC have one with want the integrated SoC of advancing in the identical internal structure of function nuclear core;
And wherein the main system computer is carried out and is produced the test pattern that will offer silicon IC, response output, the timing of carrying out SoC and the whole tasks of interface evaluates of assessment silicon IC, and the global design verification of SoC.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100389425C (en) * | 2004-12-28 | 2008-05-21 | 北京六合万通微电子技术有限公司 | Method and equipment for implementing verification of digital-analog mixed type IC |
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| CN100454196C (en) * | 2005-02-28 | 2009-01-21 | 株式会社东芝 | Method for verifying safety apparatus and safety apparatus verified by the same |
| CN102043699A (en) * | 2010-11-02 | 2011-05-04 | 青岛海信信芯科技有限公司 | SOC (System on a Chip) debugging and verifying device and method |
| CN102088374A (en) * | 2010-11-25 | 2011-06-08 | 中国航空无线电电子研究所 | Stimulating module for testing universal performance of serial interface |
| CN102088374B (en) * | 2010-11-25 | 2013-01-02 | 中国航空无线电电子研究所 | Stimulating module for testing universal performance of serial interface |
| CN102263983A (en) * | 2011-04-14 | 2011-11-30 | 青岛海信信芯科技有限公司 | SOC (System on a Chip) verification method and debugging tool for radio frequency signals |
| US11408934B2 (en) | 2017-12-22 | 2022-08-09 | Nvidia Corporation | In system test of chips in functional systems |
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| US12078678B2 (en) | 2017-12-22 | 2024-09-03 | Nvidia Corporation | In system test of chips in functional systems |
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