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Li et al., 2024 - Google Patents

A multi-level verification method for a quad-core RISC-V SoC

Li et al., 2024

Document ID
13622932964247710646
Author
Li L
Ren Y
Liu X
Tan N
Publication year
Publication venue
2024 9th International Conference on Integrated Circuits and Microsystems (ICICM)

External Links

Snippet

Verification is a time-consuming and resource-intensive task in System-on-Chip (SoC) design. However, a single verification method often fails to effectively meet diverse verification needs. In this paper, we present a multi-level verification method that divides …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/318357—Simulation
    • G—PHYSICS
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    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
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    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G—PHYSICS
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    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G—PHYSICS
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    • G06F2217/70—Fault tolerant, i.e. transient fault suppression

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