CN1302138A

CN1302138A - Multiplex shunt with variable bit rate and multiplex shunting method

Info

Publication number: CN1302138A
Application number: CN 99126991
Authority: CN
Inventors: 舒曦辉
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 1999-12-24
Filing date: 1999-12-24
Publication date: 2001-07-04
Anticipated expiration: 2019-12-24
Also published as: CN1129279C

Abstract

In a multiple shunt, input code stream is first converted in an SIPO shift register from serial one into parallel one, then byte arranged as required, and finally converted in a P/S converter into serial code steam in bit rate different from that of input code stream. The multiplex shunt includes mainly SIPO shift register, latch and P/S converter. In the circuit, devices, such as one-out-of-eight selector, are used for easy delay control, high speed and practicality. The persent invention is also suitable for use for multiple input code stream.

Description

The multiplexing splitter of variable bit rate and multiplexing minute path method

The present invention relates to big capacity Program Controling of Digital Exchange technology, be specifically related to realize the multiplexing bypass technology of high-speed transfer, more particularly, relate to a kind of multiplexing splitter of variable bit rate.

The principle of multiplexing block diagram of PCM30/32 as shown in Figure 1 at present.Shift register is 8 SI PO shift registers among Fig. 1, its 8 Bits Serial sign indicating number in each time slot under CP control becomes 8 parallel-by-bit sign indicating numbers, therefore shift register eight lines of D0～D7 that come out, but 8 bit codes at shift register output D0～D7 do not occur simultaneously, but in an appearance of CP control next bit, when later half cycle of the CP of time slot last (D7), just 8 ready parallel-by-bit sign indicating numbers of conversion are sent into latch.When a CP pulse comes then, 8 bit parallel sign indicating numbers can be exported through the 8-1 electronic selector.The function of electronic selector is that the 8 parallel-by-bit sign indicating numbers of 8 HW are arranged, merged by a graded.

Fig. 2 is the splitter frame of 8 end pulse codes, goes here and there out 8 bit shift register by latch and incorporating into and forms.Latch is as depositing usefulness, and its input is directly coupled together by digital switching network.The latch that is connected to splitter by digital switching network is that 8 end pulse codes connect together, but can separately enter the latch of respectively holding pulse code, and this is because the terminal pin of the latch of each end pulse code is connected to the different pulse of time location.The latch of the first end PCM meets TD0^CP, the second termination TD1^CP ... the 8th termination TD7^CP.Under digit pulse TD0～TD7 control, D0～D7 that just can 8 HW is written to latch 0～7 respectively, and promptly D0～D7 of HW0 writes latch 0, and D0～D7 of HW1 writes latch 1 ...When the TD0 of next time slot, in preceding half period of CP the set end S of shift register is set to 1, shift register set at this moment is so just send into D0～D7.When next CP arrives, TD=0, so the S end is 0, and not set of shift register, only displacement is just sent outward with one one of the beat of CP, and up to the TD0 of next time slot appearance, set is one again ... the sign indicating number that walks abreast can be become serial code like this.

The shortcoming of the multiplexing splitter of above-mentioned tradition mainly contains: 1) 88 in the multiplexer select 1 to realize that for reality difficulty is bigger, when especially utilizing programming device, not only can take many resources, and the bad control of time delay, are difficult to accomplish very high-speed; 2) can only use dumb at 8 inputs.

Purpose of the present invention is exactly in order to overcome the above problems, and a kind of multiplexer and splitter are provided, and not only makes design realize the big reduction of difficulty, and can expand easily, realizes multiplexing shunt at a high speed.

The present invention realizes that the scheme of above-mentioned purpose comprises multiplexing splitter and multiplexing minute path method, and they had both belonged to same design.This design mainly is: earlier through seal in/and go out shift register and will import serial code stream and be transformed to parallel code stream, again the byte in the code stream is arranged on request, be transformed into the fast serial code stream that is different from input code speed of sign indicating number after incorporate/go here and there out converter into.The scheme of its multiplexing splitter and multiplexing minute path method is as follows respectively:

Multiplexing splitter comprises multiplexer part and splitter part, wherein multiplexer partly comprise seal in/and go out shift register, latch, splitter partly comprises latch, seals in/and go out shift register, it is characterized in that: in the multiplexer part, described sealing in/and go out also to include ranking circuit in the shift register, form S/P conversion and ranking circuit, its input is multi-path low speed code stream HW0, HW1 ... HWn, its output is parallel code stream, the parallel code stream of output put in order for:

HW0TS0 HW1TS0 ... HWnTS0 HW0TS1 HW1TS1 ... HWnTS1 ... HW0TS31HW1TS31 ... HWnTS31 is TS0, TS1 wherein ... TS31 is the time slot in each code stream; Way and latch figure place according to input code flow are divided into one or more groups with above-mentioned parallel code stream, and correspondingly, latch also has one or more, the corresponding one group of parallel code stream of each latch; Identical and the phase place difference of the clock frequency of all latchs, its output signal is input to a plurality of P/S converters respectively, or is input to a plurality of inputs of a P/S converter; The output of described P/S converter is the output of high speed serialization code stream; In the described splitter part, be connected to the S/P converter before latch, the input of described S/P converter is the high-speeld code-flow input of splitter, the input of its output termination latch; The output termination P/S translation circuit input of latch, the output of P/S translation circuit is the low speed code stream output of splitter.

Path method comprised multiplexing method and divided path method two parts in described multiplexing minute, it is characterized in that: described multiplexing method may further comprise the steps: utilize S/P conversion and ranking circuit multi-path low speed code stream HW0, the HW1 with input ... HWn is transformed to the parallel code stream of output, and the sequence arrangement that will export parallel code stream is: HW0TS0 HW1TS0 ... HWnTS0 HWOTS1 HW1TS1 ... HWnTS1 ... HW0TS31HW1TS31 ... HWnTS31, wherein TS0, TS1 ... TS31 is the time slot in each code stream; Way and latch figure place according to input code flow are divided into one or more groups with above-mentioned parallel code stream, and every group is input to one respectively clock frequency is identical and latch that phase place has nothing in common with each other; The output signal of latch is input to a plurality of P/S converters respectively, or a plurality of inputs that are input to a P/S converter carry out the P/S conversion; Output signal after the conversion of described P/S converter is the high speed serialization code stream; Path method may further comprise the steps in described minute: the high-speeld code-flow that receives is input to the input of S/P converter, carries out the S/P conversion; Output to the input of latch through the signal of S/P conversion, and output to P/S translation circuit input through latch; Output after the conversion of P/S translation circuit is the low speed code stream output signal of splitter.

Owing to adopted above scheme, do not have 8 to select 1 such device in the circuit, device P/S that uses and time delays such as S/P converter, latch are easy to control, and can accomplish high-speed, reduced practical difficulty, when especially utilizing programming device, benefit is more obvious.Because all be input code flow to be transformed into parallel code stream earlier handle, this pattern not only is suitable for the situations of 8 inputs again, also can be suitable for the situation (be generally 8 multiple) of more a plurality of input code flows.

Fig. 1 is traditional multiplexer block diagram.

Fig. 2 is traditional splitter block diagram.

Fig. 3 is required A0-A7 timing waveform when 8 end pulse codes exchange in traditional multiplexing splitter.

Fig. 4-6b is four kinds of embodiment schematic diagrams of multiplexer of the present invention.

Fig. 7 is included in a schematic diagram in the P/S converter of n*8 position with n 8 P/S converters.

Fig. 8-the 11st, four kinds of embodiment schematic diagrams of splitter of the present invention.

Figure 12 is the circuit diagram of multiplexing splitter more specifically of the present invention.

Figure 13 is the used sequential schematic diagram of MT9085 among Figure 12.

Figure 14 is that the FPGA internal clocking among Figure 12 is adjusted schematic diagram.

Also the present invention is described in further detail in conjunction with the accompanying drawings below by specific embodiment.

Multiplexing/splitter comprises multiplexer part and splitter part, and the two is arranged in the same equipment.

As Fig. 4-6b, briefly say, multiplexer comprise seal in/and go out shift register, latch 2, it is characterized in that: described sealing in/and go out also to include ranking circuit in the shift register, form S/P conversion and ranking circuit 1, its input is multi-path low speed code stream HW0, HW1 ... HWn, its output is parallel code stream, the parallel code stream of output put in order for:

HW0TS0 HW1TS0 ... HWnTS0 HW0TS1 HW1TS1 ... HWnTS1 ... HW0TS31 HW1TS31 ... HWnTS31 is TS0, TS1 wherein ... TS31 is the time slot in each code stream; Way and latch 2 figure places according to input code flow are divided into one or more groups with above-mentioned parallel code stream, and correspondingly, latch 2 also has one or more, each latch 2 corresponding one group of parallel code stream; Identical and the phase place difference of the clock frequency of all latchs 2, its output signal is input to a plurality of P/S converters 3 respectively, or is input to a plurality of inputs of a P/S converter 3; The output of described P/S converter 3 is the output of high speed serialization code stream.

P/S converter wherein is made up of latch, and available global clock keeps synchronously its output.

Correspondingly, as Fig. 8-11, splitter comprises latch 2 ', seals in/and go out shift register 3 ', it is characterized in that: be connected to S/P converter 1 ' before at latch 2 ', the input of described S/P converter 1 ' is the high-speeld code-flow input of splitter, the input of its output termination latch 2 '; The output termination P/S translation circuit 3 ' input of latch 2 ', the output of P/S translation circuit 3 ' is the low speed code stream output of splitter.

Also be connected between described latch 2 ' and the P/S translation circuit 3 ' alternative circuit 4 or three select a circuit 4 ', the output of latch 2 ' connects P/S translation circuit 3 ' input by described alternative circuit 4.

Multiplexer provided by the invention is applicable to multiple sign indicating number speed, and structured flowchart is shown in Fig. 4-7.High sign indicating number speed must be 8 integral multiple of low bit rate, and the high-speeld code-flow of this multiplexer can have two kinds of speed S0, S1, and the speed of the two differs one times, perhaps multiple speed more.Device is described below among each figure:

1, S/P conversion and ranking circuit 1 (be called for short S/P) are different with common S/P, and this S/P not only goes here and there input code flow-and conversion, and the code stream that will walk abreast sorts.To import low speed code stream 0～n and count HW0～n respectively, time slot in each code stream is used TS31 (x=0,1,2,31) expression, then the order of parallel output code flow is as follows: HW0TS0HW1TS0 ... HWnTS0HW0TS1HW1TS1 ... HWnTS1 ... HW0TS31HW1TS31 ... HWnTS31.

2,8 latchs 2 are used for the output of temporary S/P, and when preventing to handle in subordinate, the output of S/P causes interference.Reason that need not 1 16 latch with 28 latchs is to adapt to 2 kinds of output code speed, the identical and phase place difference of the clock frequency of 2 latchs.

3,8 or 16 or 24 P/S converters 3 (being called for short P/S) are 24 P/S when output code speed is S2; When output code speed is S1, be 16 P/S; When output code speed is S0, be 28 P/S.Realized that like this output can be 2 kinds of sign indicating number speed.

Wherein Fig. 4 is that input low speed code stream is 16 the tunnel, and the output high-speeld code-flow is 2 the tunnel, the situation when every road is 8 times of sign indicating numbers speed of low speed code stream.Wherein reason that need not 1 16 latch with 28 latchs is to adapt to 2 kinds of output code speed.Just can make their clock frequencies identical with 2 latchs, the phase place difference by adjustment.

Fig. 5 is that input low speed code stream is 16 the tunnel, and the output high-speeld code-flow is 1 the tunnel, the situation when every road is 16 times of sign indicating numbers speed of low speed code stream.

Fig. 6 a is that input low speed code stream is 24 the tunnel, and the output high-speeld code-flow is 3 the tunnel, the situation when being 8 times of sign indicating numbers speed of low speed code stream.

Fig. 6 b is that input low speed code stream is 24 the tunnel, and the output high-speeld code-flow is 1 the tunnel, the situation when every road is 24 times of sign indicating numbers speed of low speed code stream.

In Fig. 4, Fig. 6 a,, 2 and 38 P/S converters have been used respectively for adapting to the output of multipath high-speed code stream.In fact, 2 and 38 P/S converters can be contained in one 2 respectively ^*8 or 3 ^*In 8 P/S converters (wherein ^*The expression multiplication sign, down together).Fig. 7 is contained in 1 n with n 8 P/S converters ^*Schematic diagram in 8 P/S converters has saved among the figure and has put fractional part synchronously, and FD is d type flip flop (D is an input, and Q is an output, and C is an input end of clock), and CK is an input clock.In shift sequence, draw the output of a tap as serial code stream in per the 8th d type flip flop output.Like this, if the CK clock frequency is 8 times of input code flow, then this P/S is equivalent to n 8 P/S; If the CK clock frequency is 16 times of input code flow, then this P/S is equivalent to n/2 16 P/S; If the CK clock frequency is the n of input code flow ^*8 times, then this P/S is equivalent to a n ^*8 P/S.

Splitter is the reverse process of multiplexer, is about to high-speeld code-flow and is connected into some low speed code streams by the byte branch.Here high-speeld code-flow can have two kinds of sign indicating number speed S0, S1 equally, and the two speed differs one times, and its structure is shown in Fig. 8-11.

1,8 or 16 S/P converters 1 ' are 8 S/P when sign indicating number speed is S0 at a high speed; When sign indicating number speed is S1 at a high speed, be 16 S/P.

2,16 latchs 2 ' carry out buffer memory to 16 parallel-by-bit data, avoid disturbing in the data of carrying out come by higher level S/P when next stage is handled.

3, eight alternative circuit 4 are made up of 8 alternatives, and the 16 parallel-by-bit data that latch are switched, and form 8 parallel-by-bit output code flows.The internal arrangement order of 8 parallel-by-bit code streams is identical with the S/P output code flow in the multiplexer.

4, P/S translation circuit 3 ' is converted to the output of serial low speed code stream with 8 parallel-by-bit code streams, is equivalent to the reverse process of S/P in the multiplexer.

Wherein Fig. 8 is input as 2 road high-speeld code-flows, is output as 16 road low speed code streams, the situation when high-speeld code-flow is 8 times of sign indicating numbers speed of low speed code stream.

Fig. 9 is input as 1 road high-speeld code-flow, is output as 16 road low speed code streams, the situation when high-speeld code-flow is 16 times of sign indicating numbers speed of low speed code stream.

Figure 10 is input as 1 road high-speeld code-flow, is output as 8 road low speed code streams, the situation when high-speeld code-flow is 8 times of sign indicating numbers speed of low speed code stream.

Figure 11 is input as 3 road high-speeld code-flows, is output as 24 road low speed code streams, the situation when high-speeld code-flow is 8 times of sign indicating numbers speed of low speed code stream.

The fast conversion example of sign indicating number below in conjunction with between 16 2M and 2 16M and 1 32M further describes the present invention.

The The general frame of whole translation circuit is as shown in figure 12:

S/P in the multiplexer and the P/S in the splitter adopt the MT9085 of Mitel company to realize, by the working method of MT9085 is set, can realize string-also string conversion.Concrete sequential chart as shown in figure 13.

Adopt FPGA (Field Programmable arrays) to realize other parts of multiplexing splitter.As can be seen, no matter how much sign indicating number speed is at a high speed, through just there not being the difference of sign indicating number speed behind the S/P, this just requires the internal control sign indicating number constant from the structure chart of multiplexing splitter.Therefore extremely important to the processing method of internal clocking.The simplest and the clearest kind method is exactly by conversion, and the FPGA clock internal is unified.Its principle such as Figure 14:

By a selection signal SELECT, the FPGA internal clocking is unified.No matter input clock is 16M or 32M, after selecting, just becomes fixing output, and later like this clock generation circuit also obtains unified.By this thought,, also need not change circuit and just can realize conversion between 32 * 2M and 2 * 32M or the 1 * 64M even input code flow doubles.The present invention utilizes the synchronous logic design to the multiplexing splitter of tradition is improved, and not only makes design realize the big reduction of difficulty, and can expand easily, realizes multiplexing/minute device at a high speed.

Clearly, from the description to device promptly utilize as can be known above-mentioned multiplexing splitter realize variable bit rate multiplexing/method along separate routes.Be summarized as follows:

Multiplexing method may further comprise the steps: utilize S/P conversion and ranking circuit multi-path low speed code stream HW0, the HW1 with input ... HWn is transformed to the parallel code stream of output, and the sequence arrangement that will export parallel code stream is: HW0TS0 HW1TS0 ... HWnTS0 HW0TS1 HW1TS1 ... HWnTS1 ... HW0TS31 HW1TS31 ... HWnTS31, wherein TS0, TS1 ... TS31 is the time slot in each code stream; Way and latch figure place according to input code flow are divided into one or more groups with above-mentioned parallel code stream, and every group is input to one respectively clock frequency is identical and latch that phase place has nothing in common with each other; The output signal of latch is input to a plurality of P/S converters respectively, or a plurality of inputs that are input to a P/S converter carry out the P/S conversion; Output signal after the conversion of described P/S converter is the high speed serialization code stream;

Divide path method may further comprise the steps: the high-speeld code-flow that receives to be input to the input of S/P converter, to carry out the S/P conversion; Output to the input of latch through the signal of S/P conversion, and output to P/S translation circuit input through latch; Output after the conversion of P/S translation circuit is the low speed code stream output signal of splitter.

Described herein S/P conversion is meant serial/parallel conversion, and the P/S conversion is meant parallel/serial conversion.

Claims

1, a kind of multiplexing splitter of variable bit rate, comprise multiplexer part and splitter part, wherein multiplexer partly comprise seal in/and go out shift register, latch (2), splitter partly comprises latch (2 '), seals in/and go out shift register (3 '), it is characterized in that: in the multiplexer part, described sealing in/and go out also to include ranking circuit in the shift register, form S/P conversion and ranking circuit (1), its input is multi-path low speed code stream HW0, HW1 ... HWn, its output is parallel code stream, the parallel code stream of output put in order for:

HW0TS0 HW1TS0 ... HWnTS0 HW0TS1 HW1TS1 ... HWnTS1 ... HW0TS31HW1TS31 ... HWnTS31 is TS0, TS1 wherein ... TS31 is the time slot in each code stream; Way and latch (2) figure place according to input code flow are divided into one or more groups with above-mentioned parallel code stream, and correspondingly, latch (2) also has one or more, the corresponding one group of parallel code stream of each latch (2); Identical and the phase place difference of the clock frequency of all latchs (2), its output signal is input to a plurality of P/S converters (3) respectively, or is input to a plurality of inputs of a P/S converter (3); The output of described P/S converter (3) is the output of high speed serialization code stream; In the described splitter part, be connected to S/P converter (1 ') before at latch (2 '), the input of described S/P converter (1 ') is the high-speeld code-flow input of splitter, the input of its output termination latch (2 '); Output termination P/S translation circuit (the 3 ') input of latch (2 '), the output of P/S translation circuit (3 ') are the low speed code stream output of splitter.

2, the multiplexing splitter of variable bit rate as claimed in claim 1 is characterized in that: the P/S converter (3) in the described multiplexer part is made up of latch, and available global clock keeps synchronously its output; Also be connected to alternative circuit (4) between latch (2 ') in the described splitter part and the P/S translation circuit (3 '), the output of latch (2 ') connects P/S translation circuit (3 ') input by described alternative circuit (4).

3, a kind of multiplexing minute path method of variable bit rate comprises multiplexing method and divides path method two parts, and it is characterized in that: described multiplexing method may further comprise the steps:

Utilize S/P conversion and ranking circuit (1) multi-path low speed code stream HW0, HW1 with input ... HWn is transformed to the parallel code stream of output, and the sequence arrangement that will export the code stream that walks abreast is:

HW0TS0 HW1TS0 ... HWnTS0 HWOTS1 HW1TS1 ... HWnTS1 ... HW0TS31HW1TS31 ... HWnTS31 is TS0, TS1 wherein ... TS31 is the time slot in each code stream;

Way and latch (2) figure place according to input code flow are divided into one or more groups with above-mentioned parallel code stream, and every group is input to one respectively clock frequency is identical and latch (2) that phase place has nothing in common with each other;

The a plurality of inputs that the output signal of latch (2) are input to a plurality of P/S converters (3) respectively or are input to a P/S converter (3) carry out the P/S conversion;

Output signal after described P/S converter (3) conversion is the high speed serialization code stream;

Path method may further comprise the steps in described minute:

The high-speeld code-flow that receives is input to the input of S/P converter (1 '), carries out the S/P conversion;

Output to the input of latch (2 ') through the signal of S/P conversion, and output to P/S translation circuit (3 ') input through latch (2 ');

Output after P/S translation circuit (3 ') conversion is the low speed code stream output signal of splitter.