CN1129279C - Multiplex shunt with variable bit rate and multiplex shunting method - Google Patents

Abstract

The invention discloses a variable code rate multiplexing splitter and a multiplexing splitting method. First, the input serial code stream is converted into a parallel code stream through a serial in/parallel out shift register, and then the code stream in the code stream is converted into a parallel code stream. The bytes are arranged according to the requirements, and finally converted into a serial code stream whose code rate is different from the input code rate through the merge-in/serial-out converter. The main devices in the multiplexing splitter are serial input/parallel output shift registers, latches and P/S converters. There is no one-of-eight device in the circuit, the time delay is easy to control, and high speed can be achieved, which reduces practical difficulties. And it can be adapted to the situation of more input code streams.

Description

Variable code rate demultiplexer and demultiplexing method

The invention relates to a large-capacity program-controlled digital switching technology, in particular to a multiplexing and demultiplexing technology for realizing high-speed transmission, and more specifically, to a variable code rate multiplexing and demultiplexing device.

The block diagram of multiplexing principle of PCM30/32 is shown in Fig. 1 at present. The shift register in Figure 1 is an 8-bit serial in-parallel shift register. Under the control of the CP, the 8-bit serial code in each time slot becomes an 8-bit parallel code, so the shift register comes out with eight lines D0~D7 , but the 8-bit codes at the output terminals D0~D7 of the shift register do not appear at the same time, but appear bit by bit under the control of the CP. In the second half cycle of the CP of the last bit (D7) of the time slot, the Send the 8-bit parallel code that has been transformed into the latch. When a CP pulse comes, the 8-bit parallel code can be output through the 8-1 electronic selector. The function of the electronic selector is to arrange and merge the 8-bit parallel codes of 8 HWs in a certain order.

Figure 2 is a splitter frame of 8-terminal pulse code, which is composed of a latch and an 8-bit shift register that is connected in series. The latch is used as a register, and its input is directly connected by the digital switching network. The latches connected to the splitter by the digital switching network are connected together with 8-terminal pulse codes, but the latches of each terminal pulse code can be separated, because the pins of the latches of each terminal pulse code There are pulses with different time positions. The latch of the PCM at the first end is connected to TD0＾CP, the second end is connected to TD1＾CP...the eighth end is connected to TD7＾CP. Under the control of bit pulse TD0~TD7, D0~D7 of 8 HWs can be written into latches 0~7 respectively, that is, D0~D7 of HW0 can be written into latch 0, and D0~D7 of HW1 can be written into latches. register 1....... At TD0 of the next time slot, set the setting terminal S of the shift register to 1 in the first half cycle of the CP, at this time the shift register is set, and then D0 ~ D7 are sent into. When the next CP arrives, TD=0, so the S terminal is 0, the shift register is not set, only shifted, and it is sent out one by one at the beat of the CP, until TD0 in the next time slot appears, and then set One bit... This turns the parallel code into a serial code.

The disadvantages of the above-mentioned traditional multiplexing splitter mainly include: 1) It is difficult to implement 8 out of 8 multiplexers in the multiplexer, especially when using programmable devices, not only will it take up a lot of resources, but also the time delay is not good Control, it is difficult to achieve very high speed; 2) It can only be used for 8 inputs, and the application is not flexible.

The object of the present invention is to solve the above problems and provide a multiplexer and splitter, which not only greatly reduces the difficulty of design and implementation, but also can be easily expanded to realize high-speed multiplexing and splitting.

The solution of the present invention to achieve the above object includes a multiplexer and a multiplexer and a multiplexer, both of which belong to the same idea. The idea is mainly: first convert the input serial code stream into a parallel code stream through the serial-in/parallel-out shift register, then arrange the bytes in the code stream according to requirements, and finally transform it into A serial code stream whose code rate is different from the input code rate. The schemes of the multiplexing splitter and the multiplexing splitting method are as follows:

The multiplexing splitter includes a multiplexer part and a splitter part, wherein the multiplexer part includes a serial input/parallel output shift register and a latch, and the splitter part includes a latch, a serial input/parallel output shift register The bit register is characterized in that: in the multiplexer part, the serial input/parallel output shift register also includes a sorting circuit to form an S/P conversion and sorting circuit, and its input end is a multi-channel low-speed code stream HW0 , HW1...HWn, its output terminal is a parallel code stream, and the sequence of the output parallel code stream is:

HW0TS0 HW1TS0…HWnTS0 HW0TS1 HW1TS1…HWnTS1…HW0TS31HW1TS31…HWnTS31 Among them, TS0, TS1…TS31 are the time slots in each code stream; according to the number of input code streams and the number of latch bits, the above parallel code streams are equally divided into One or more groups, correspondingly, there are one or more latches, and each latch corresponds to a group of parallel code streams; all latches have the same clock frequency but different phases, and their output signals are respectively input to multiple P/S converter, or input to a plurality of input terminals of a P/S converter; the output terminal of the P/S converter is the output end of the high-speed serial code stream; in the splitter part, An S/P converter is connected before the latch, and the input end of the S/P converter is the high-speed code stream input end of the splitter, and its output terminal is connected to the input end of the latch; The output terminal is connected to the input terminal of the P/S conversion circuit, and the output terminal of the P/S conversion circuit is the low-speed code stream output terminal of the splitter.

The multiplexing and demultiplexing method includes two parts: a multiplexing method and a demultiplexing method, and is characterized in that: the multiplexing method includes the following steps: using S/P conversion and sorting circuits to input multiple low-speed code streams HW0, HW1 ...HWn is transformed into parallel code streams at the output terminal, and the order of the output parallel code streams is arranged as follows: HW0TS0 HW1TS0...HWnTS0 HW0TS1 HW1TS1...HWnTS1...HW0TS31HW1TS31...HWnTS31, where TS0, TS1...TS31 are time intervals in each code stream slot; according to the number of channels of the input code stream and the number of bits of the latch, the above-mentioned parallel code stream is divided into one or more groups, and each group is respectively input to a latch with the same clock frequency and different phases; the lock The output signals of the registers are respectively input to a plurality of P/S converters, or input to a plurality of input terminals of a P/S converter for P/S conversion; the output signal transformed by the P/S converter is It is a high-speed serial code stream; the branching method includes the following steps: input the received high-speed code stream to the input end of the S/P converter, and perform S/P conversion; the signal output through the S/P conversion to the lock The input terminal of the register, and the output of the latch to the input terminal of the P/S conversion circuit; the output terminal transformed by the P/S conversion circuit is the low-speed stream output signal of the splitter.

Due to the adoption of the above scheme, there is no device such as 8 to 1 in the circuit, and the time delay of the used devices such as P/S and S/P converters and latches is easy to control, and can achieve high speed, reducing the Practical difficulties, especially when using programmable devices, the benefits are more apparent. Since the input code streams are converted into parallel code streams before processing, this mode is not only suitable for the case of 8 inputs, but also for the case of more input code streams (generally a multiple of 8).

Figure 1 is a block diagram of a traditional multiplexer.

Figure 2 is a block diagram of a traditional splitter.

Fig. 3 is A0-A7 timing pulse waveform required for 8-port pulse code exchange in a traditional multiplexing splitter.

4-6b are schematic diagrams of four embodiments of the multiplexer of the present invention.

Fig. 7 is a schematic diagram of including n 8-bit P/S converters in one n*8-bit P/S converter.

8-11 are schematic diagrams of four embodiments of splitters of the present invention.

Fig. 12 is a schematic circuit diagram of a more specific multiplexing splitter of the present invention.

Figure 13 is a timing diagram for the MT9085 in Figure 12.

FIG. 14 is a schematic diagram of FPGA internal clock adjustment in FIG. 12 .

The present invention will be described in further detail below through specific embodiments and in conjunction with the accompanying drawings.

The multiplexer/demultiplexer includes a multiplexer part and a demultiplexer part, both of which are arranged in the same device.

As shown in Figure 4-6b, generally speaking, the multiplexer includes a serial-in/parallel-out shift register and a latch 2, which is characterized in that: the serial-in/parallel-out shift register also includes a sorting circuit, consisting of S/P conversion and sorting circuit 1, its input end is multi-channel low-speed code stream HW0, HW1...HWn, its output end is parallel code stream, and the order of arrangement of the output parallel code stream is:

HW0TS0 HW1TS0...HWnTS0 HW0TS1 HW1TS1...HWnTS1...HW0TS31 HW1TS31...HWnTS31 where TS0, TS1...TS31 are time slots in each code stream; The above-mentioned parallel code streams are equally divided into one or more groups, correspondingly, there are one or more latches 2, and each latch 2 corresponds to a group of parallel code streams; all latches 2 have the same clock frequency but different phases , its output signal is input to a plurality of P/S converters 3 respectively, or is input to a plurality of input terminals of a P/S converter 3; The output terminal of the P/S converter 3 is a high-speed serial code stream output terminal.

Among them, the P/S converter is made up of latches, and the global clock can be used to keep its output synchronized.

Correspondingly, as shown in Fig. 8-11, the splitter includes a latch 2', a serial-in/parallel-out conversion circuit (P/S conversion circuit) 3', which is characterized in that an S /P converter 1', the input end of the S/P converter 1' is the high-speed code stream input end of the splitter, and its output end is connected to the input end of the latch 2'; the input end of the latch 2' The output terminal is connected to the input terminal of the P/S conversion circuit 3', and the output terminal of the P/S conversion circuit 3' is the low-speed code stream output terminal of the splitter.

Between the described latch 2' and the P/S conversion circuit 3', there is also a two-to-one circuit 4 or a three-to-one circuit 4', and the output end of the latch 2' is connected through the two-to-one circuit 4. P/S conversion circuit 3'input end.

The multiplexer provided by the present invention is applicable to various code rates, and the structural block diagram is shown in Fig. 4-7. The high code rate must be an integer multiple of 8 of the low code rate, and the high-speed code stream of the multiplexer can have two speeds S0 and S1, and the difference between the two speeds is doubled or more. The devices in each figure are described as follows:

1. The S/P conversion and sorting circuit 1 (S/P for short) is different from the common S/P. The S/P not only performs serial-parallel conversion on the input code stream, but also sorts the parallel code stream. The input low-speed code streams 0~n are respectively counted as HW0~n, and the time slots in each code stream are represented by TS31 (x=0, 1, 2, ... 31), then the order of parallel output code streams is as follows: HW0TS0HW1TS0...HWnTS0HW0TS1HW1TS1...HWnTS1...HW0TS31HW1TS31...HWnTS31.

2. The 8-bit latch 2 is used to temporarily store the output of the S/P to prevent the output of the S/P from causing interference during the lower-level processing. The reason for using two 8-bit latches instead of one 16-bit latch is to adapt to two output code rates, and the two latches have the same clock frequency but different phases.

3. 8 or 16 or 24-bit P/S converter 3 (referred to as P/S) is 24-bit P/S when the output code rate is S2; when the output code rate is S1, it is 16-bit P/S; When the output code rate is S0, it is two 8-bit P/S. In this way, the output can be 2 code rates.

Among them, Figure 4 shows the situation when the input low-speed code stream is 16 channels, the output high-speed code stream is 2 channels, and each channel is 8 times the code rate of the low-speed code stream. Among them, the reason for using two 8-bit latches instead of one 16-bit latch is to adapt to two output code rates. With 2 latches, they can be adjusted to have the same clock frequency and different phases.

Figure 5 shows the situation when there are 16 low-speed code streams input and 1 high-speed code stream output, each of which is 16 times the code rate of the low-speed code stream.

Figure 6a shows the situation when 24 low-speed code streams are input and 3 high-speed code streams are output, which is 8 times the code rate of the low-speed code stream.

Figure 6b shows the situation when 24 low-speed code streams are input and 1 high-speed code stream is output, each of which is 24 times the code rate of the low-speed code stream.

In Figure 4 and Figure 6a, two and three 8-bit P/S converters are used respectively in order to adapt to the output of multiple high-speed code streams. In fact, 2 and 3 8-bit P/S converters can be included in a 2*8 or 3*8-bit P/S converter respectively (where * represents a multiplication sign, the same below). Fig. 7 is a schematic diagram of including n 8-bit P/S converters in one n*8-bit P/S converter. The synchronous setting part is omitted in the figure, and FD is a D flip-flop (D is an input terminal , Q is the output terminal, C is the clock input terminal), and CK is the input clock. In the shift sequence, every 8th D flip-flop output pulls a tap as the output of the serial code stream. In this way, if the CK clock frequency is 8 times the input code stream, the P/S is equivalent to n 8-bit P/S; if the CK clock frequency is 16 times the input code stream, the P/S is equivalent to n/ Two 16-bit P/S; if the CK clock frequency is n*8 times of the input code stream, the P/S is equivalent to one n*8-bit P/S.

The demultiplexer is the reverse process of the multiplexer, that is, the high-speed code stream is divided into several low-speed code streams by bytes. Here, the high-speed code stream can also have two code rates S0 and S1, and the difference between the two speeds is doubled. The structure is shown in Figure 8-11.

1, 8 or 16 bit S/P converter 1 ' when the high-speed code rate is S0, be 8 bits of S/P; When the high-speed code rate is S1, be 16 bits of S/P.

2. The 16-bit latch 2' caches the 16-bit parallel data to avoid data interference from the upper-level S/P when the next-level processing is performed.

3. The eight optional-one circuits 4 are composed of eight optional-one circuits, which switch the latched 16-bit parallel data to form an 8-bit parallel output code stream. The internal sequence of the 8-bit parallel code stream is the same as the S/P output code stream in the multiplexer.

4. The P/S conversion circuit 3' converts the 8-bit parallel code stream into a serial low-speed code stream output, which is equivalent to the reverse process of S/P in the multiplexer.

Figure 8 shows the situation when the input is 2 high-speed code streams, the output is 16 low-speed code streams, and the high-speed code stream is 8 times the code rate of the low-speed code stream.

Figure 9 shows the situation when the input is 1 high-speed code stream, the output is 16 low-speed code streams, and the high-speed code stream is 16 times the code rate of the low-speed code stream.

Figure 10 shows the situation when the input is 1 high-speed code stream, the output is 8 low-speed code streams, and the high-speed code stream is 8 times the code rate of the low-speed code stream.

Figure 11 shows the situation when the input is 3 high-speed code streams, the output is 24 low-speed code streams, and the high-speed code stream is 8 times the code rate of the low-speed code stream.

The present invention will be further described below in conjunction with examples of code rate conversion between 16 2Ms, 2 16Ms and 1 32M.

The overall block diagram of the entire conversion circuit is shown in Figure 12:

The S/P in the multiplexer and the P/S in the splitter are implemented by Mitel's MT9085. By setting the working mode of MT9085, serial-to-parallel conversion can be realized. The specific timing diagram is shown in Figure 13.

Use FPGA (Field Programmable arrays) to realize other parts of the multiplexer. It can be seen from the structure diagram of the demultiplexer that no matter what the high-speed code rate is, there is no difference in the code rate after S/P, which requires the internal control code to remain unchanged. Therefore, the processing method of the internal clock is very important. The simplest method is to unify the clocks inside the FPGA through transformation. The principle is shown in Figure 14:

Through a selection signal SELECT, the FPGA internal clock is unified. Regardless of whether the input clock is 16M or 32M, after selection, it becomes a fixed output, so that the subsequent clock generation circuits are also unified. Through this idea, even if the input code stream is doubled, the conversion between 32×2M and 2×32M or 1×64M can be realized without changing the circuit. The invention improves the traditional multiplexer and splitter, uses synchronous logic design, not only greatly reduces the difficulty of design and realization, but also can be expanded conveniently to realize high-speed multiplexer/splitter.

Obviously, from the description of the device, we can know the method of implementing variable code rate multiplexing/demultiplexing by using the above-mentioned multiplexer/demultiplexer. A brief description is as follows:

The multiplexing method includes the following steps: using the S/P conversion and sorting circuit to transform the input multiple low-speed code streams HW0, HW1...HWn into output parallel code streams, and arrange the order of the output parallel code streams as: HW0TS0 HW1TS0 …HWnTS0 HW0TS1 HW1TS1…HWnTS1…HW0TS31 HW1TS31…HWnTS31, where TS0, TS1…TS31 are the time slots in each code stream; according to the number of input code streams and the number of latches, the above parallel code streams are equally divided into One or more groups, each group is input to a latch with the same clock frequency and different phases; the output signal of the latch is respectively input to multiple P/S converters, or input to a P/S P/S conversion is performed at multiple input terminals of the converter; the output signal converted by the P/S converter is a high-speed serial code stream;

The branching method includes the following steps: input the received high-speed code stream to the input end of the S/P converter, and perform S/P conversion; output the signal transformed by S/P to the input end of the latch, and The output of the register is sent to the input terminal of the P/S conversion circuit; the output terminal transformed by the P/S conversion circuit is the low-speed stream output signal of the splitter.

The S/P conversion described herein refers to the serial/parallel conversion, and the P/S conversion refers to the parallel/serial conversion.

Claims (3)

1. A variable code rate multiplexing splitter, comprising a multiplexer part and a splitter part, wherein the multiplexer part includes a serial input/parallel output shift register, a latch (2), and a splitter The device part includes a latch (2') and a serial-in/parallel-out conversion circuit (3'), and it is characterized in that: in the multiplexer part, the serial-in/parallel-out shift register also includes a sorting circuit , forming the S/P conversion and sorting circuit (1), its input end is multi-channel low-speed code stream HW0, HW1...HWn, its output end is parallel code stream, and the arrangement sequence of the output parallel code stream is: HW0TS0 HW1TS0…HWnTS0 HW0TS1 HW1TS1…HWnTS1…HW0TS31 HW1TS31…HWnTS31 where TS0, TS1…TS31 are time slots in each code stream; Code streams are equally divided into one or more groups, correspondingly, there are one or more latches (2), and each latch (2) corresponds to a group of parallel code streams; the clock frequency of all latches (2) The same but with different phases, the output signals are respectively input to a plurality of P/S converters (3), or input to multiple input terminals of a P/S converter (3); the P/S converter (3) The output end of is the output end of the high-speed serial code stream; In the described splitter part, before the latch (2'), an S/P converter (1') is connected, and the S/P converter The input terminal of (1') is the high-speed code stream input terminal of the splitter, and its output terminal is connected to the input terminal of the latch (2'); the output terminal of the latch (2') is connected to the P/S conversion circuit (3') input end, and the output end of the P/S conversion circuit (3') is the low-speed code stream output end of the splitter. 2. The multiplexing splitter of variable code rate as claimed in claim 1 is characterized in that: the P/S converter (3) in the multiplexer part is made up of a latch, which can be used by a global clock. Its output keeps synchronously; Also be connected with two select one circuit (4) between the latch (2') and P/S conversion circuit (3') in the splitter part, latch (2') The output terminal of the P/S conversion circuit (3') is connected to the input terminal of the P/S conversion circuit (3') through the said one-of-two circuit (4). 3, a kind of multiplexing branching method of variable code rate, comprise two parts of multiplexing method and branching method, it is characterized in that: described multiplexing method comprises the following steps: Utilize the S/P conversion and sorting circuit (1) to transform the input multi-channel low-speed code streams HW0, HW1...HWn into output parallel code streams, and arrange the order of the output parallel code streams as follows: HW0TS0 HW1TS0…HWnTS0 HW0TS1 HW1TS1…HWnTS1…HW0TS31HW1TS31…HWnTS31 where TS0, TS1…TS31 are time slots in each stream; According to the number of channels of the input code stream and the number of bits of the latch (2), the above-mentioned parallel code stream is divided into one or more groups, and each group is respectively input to a latch (2) with the same clock frequency and different phases. ); Inputting the output signal of the latch (2) to a plurality of P/S converters (3) or multiple input terminals of a P/S converter (3) respectively for P/S conversion; The output signal converted by the P/S converter (3) is a high-speed serial code stream; The branching method includes the following steps: The high-speed code stream that will receive is input to the input end of S/P converter (1 '), carries out S/P conversion; The signal output through S/P conversion is to the input terminal of latch (2 '), and the output to P/S conversion circuit (3 ') input terminal through the output of latch (2 '); The output end transformed by the P/S conversion circuit (3') is the low-speed stream output signal of the splitter.

Images