CN1287445C - Method for making trench capacitor shallow trench insulation - Google Patents

Abstract

The invention provides a method for manufacturing shallow trench insulation of a trench capacitor, which comprises the following steps: providing a semiconductor substrate with a hard mask thereon, wherein the semiconductor substrate has a plurality of deep trench capacitor structures formed thereon, each deep trench capacitor structure comprising a capacitor electrode, a capacitor dielectric layer, a capacitor bottom electrode and a neck oxide layer; depositing a dielectric layer on the semiconductor substrate; planarizing the dielectric layer to the surface of the hard mask, wherein the residual dielectric layer fills the recess gap above the deep trench capacitor structure; depositing a buffer layer on the semiconductor substrate; forming a photoresist mask on the buffer layer, wherein the photoresist mask is defined with a shallow trench insulation pattern opening; performing plasma dry etching, protecting each deep trench capacitor structure by using the dielectric layer and the neck oxide layer as etching masks through the shallow trench insulation pattern opening, selectively etching the buffer layer and the hard mask, and finally etching the semiconductor substrate to form an insulation shallow trench; and filling a trench insulating material into the shallow insulating trench.

Description

Method for making trench capacitor shallow trench insulation

technical field

The invention relates to a method for manufacturing trench capacitor shallow trench insulation, in particular to a method for manufacturing trench capacitor shallow trench insulation compatible with a logic process.

Background technique

With the trend of miniaturization of various electronic products, the design of DRAM components must also meet the requirements of high integration and high density, and the trench capacitor DRAM component structure is one of the high-density DRAM structures widely used in the industry. A deep trench is etched in the semiconductor substrate and a trench capacitor is formed in it, so the size of the memory unit can be effectively reduced and the chip space can be properly utilized.

Please refer to FIG. 1 to FIG. 5 . FIG. 1 to FIG. 5 are cross-sectional schematic diagrams of shallow trench insulation for making trench capacitors in the prior art. As shown in FIG. 1 , the semiconductor chip 1 is divided into a logic area (logic area) 11 and a memory array area (memory array area) 12 . A plurality of deep trench capacitor structures 20 have been fabricated in the storage array area 12 of the semiconductor chip 1 in FIG. 1 . Generally, the fabrication of the deep trench capacitor structure 20 is to etch a deep trench opening (not shown) in the silicon substrate 10 through a hard mask (hard mask) 14, and then form a capacitor electrode, capacitor dielectric layer 22, Capacitor bottom electrode (storage node) 24 and neck oxide (collar oxide) layer 26. A recess 28 is formed above the deep trench capacitor structure 20 .

As shown in FIG. 2 , next, a doped-silicate glass layer 32 , such as a borosilicate glass (BSG) layer or borophosphosilicate glass (BPSG) layer, is deposited on the semiconductor chip 1 with a thickness of about 3000 to 4000 angstroms. The doped silicon glass layer 32 covers the hard mask 14 and fills the recess 28 above the deep trench capacitor structure 20 .

As shown in Figure 3, then, deposit a bottom anti-reflection layer (BARC) 34 on the doped silicon glass layer 32, then coat a photoresist layer on the bottom anti-reflection layer (BARC) 34, then apply the photoresist The layer is photolithographically imaged by the existing yellow light process, and after being baked, a photoresist is formed with a shallow trench insulation pattern opening 43 defining a memory array area (memory arrayarea) 12 and a logic region 11 defining a shallow trench insulation pattern opening 45 Mask 36.

As shown in FIG. 4 , a plasma dry etching process is then performed, using the photoresist mask 36 as an etching mask to etch the bottom anti-reflective layer 34, the doped silicon glass layer 32, the hard mask downward through the shallow trench insulation pattern opening 43. The film 14 , the silicon substrate 10 , a part of the capacitor bottom electrode 24 and the neck oxide layer 26 form an insulating shallow trench 53 . Simultaneously, the bottom anti-reflective layer 34 , the doped silicon glass layer 32 , the hard mask 14 and the silicon substrate 10 are etched downward through the STI pattern opening 45 to form the isolation shallow trench 54 in the logic region 11 . Subsequently, the photoresist mask 36 , the bottom anti-reflection layer 34 and the doped silica glass layer 32 are removed.

Finally, as shown in FIG. 5 , trench insulating material 58 is filled in the insulating shallow trench 53 and the insulating shallow trench 54 and planarized, that is, the fabrication of the existing trench capacitor shallow trench insulation is completed.

However, there are still many disadvantages in the above-mentioned manufacturing method of the existing trench capacitor STI. Firstly, since the deep trench capacitor structure 20 is relatively complex, the composition of the etching plasma is complicated and difficult to control during STI etching. This is because the bottom anti-reflection layer 34, the doped silicon glass layer 32, the hard mask 14, the silicon substrate 10, a part of the capacitor lower electrode 24 and the neck need to be etched downward through the shallow trench insulation pattern opening 43 to form the insulating shallow trench 53. Oxide layer 26. Furthermore, the existing trench capacitor shallow trench isolation method needs to use a thicker doped silicon glass layer 32 as a mask, resulting in poor critical dimension (critical dimension, CD) uniformity and density/dense (iso/dense) dense) CD deviation between patterns. In addition, the existing trench capacitor STI manufacturing method is not compatible with the logic process.

Contents of the invention

Accordingly, the main purpose of the present invention is to provide an improved method for manufacturing trench capacitor STI, which is compatible with logic technology and solves the above-mentioned problems.

The above object of the present invention is achieved by the following technical solutions.

Option One

A method for manufacturing trench capacitor shallow trench insulation, comprising:

Provide a semiconductor substrate with a hard mask on it, wherein the surface of the semiconductor substrate is divided into a logic area and a storage array area, and a plurality of deep trench capacitor structures have been fabricated in the storage array area, and each deep trench capacitor The structure includes a capacitor electrode, a capacitor dielectric layer, a capacitor lower electrode and a neck oxide layer; its features are:

depositing a dielectric layer on the semiconductor substrate;

planarizing the dielectric layer to the surface of the hard mask, and the remaining dielectric layer fills the recessed gap above the deep trench capacitor structure;

depositing a buffer layer on the semiconductor substrate;

depositing a bottom anti-reflective layer (BARC) on the buffer layer;

Forming a photoresist mask defining an opening of a shallow trench insulation pattern in a memory array area and an opening of a shallow trench insulation pattern in a logic area on the bottom anti-reflection layer;

Performing a plasma dry etching, protecting each of the deep trench capacitor structures by using the dielectric layer and the neck oxide layer as an etching mask through the opening of the shallow trench insulation pattern in the memory array area and the opening of the shallow trench insulation pattern in the logic area, Selectively etch the bottom anti-reflection layer, the buffer layer, and the hard mask, and finally etch the semiconductor substrate to form insulating shallow trenches in the memory array area and shallow insulating trenches in the logic area;

removing the photoresist mask and bottom anti-reflection layer; and

Trench insulating material is filled in the insulating shallow trenches in the storage array area and the insulating shallow trenches in the logic area.

The method for making trench capacitor shallow trench insulation is characterized in that: the method for planarizing the dielectric layer is to use a chemical mechanical polishing (CMP) process, using the hard mask as a polishing stop layer, planarizing the dielectric layer to the hard mask surface.

The method for making trench capacitor shallow trench insulation is characterized in that: the hard mask includes silicon nitride.

The method for making trench capacitor shallow trench insulation is characterized in that: the buffer layer is made of silicon nitride.

The method for making trench capacitor shallow trench insulation is characterized in that: the thickness of the buffer layer is about 500 angstroms.

Option II

A method for making trench capacitor shallow trench insulation, comprising:

Provide a semiconductor substrate with a hard mask on it, wherein a plurality of deep trench capacitor structures have been fabricated on the semiconductor substrate, each of the deep trench capacitor structures includes a capacitor electrode, a capacitor dielectric layer, a capacitor lower electrode and Neck oxide layer; characterized by:

depositing a dielectric layer on the semiconductor substrate;

planarizing the dielectric layer to the surface of the hard mask, and the remaining dielectric layer fills the recessed gap above the deep trench capacitor structure;

depositing a buffer layer on the semiconductor substrate;

forming a photoresist mask defining an opening of a STI pattern on the buffer layer;

Performing a plasma dry etching, through the opening of the shallow trench insulation pattern, using the dielectric layer and the neck oxide layer as an etching mask to protect each of the deep trench capacitor structures, and selectively etching the buffer layer and the hard mask film, and finally etch the semiconductor substrate to form insulating shallow trenches;

removing the photoresist mask; and

The trench insulating material is filled in the insulating shallow trench.

The method for making trench capacitor shallow trench insulation is characterized in that: the method of planarizing the dielectric layer is to use a chemical mechanical polishing process, using the hard mask as a polishing stop layer, and polishing the dielectric layer The electrical layers are planarized to the hard mask surface.

The method for making trench capacitor shallow trench insulation is characterized in that: the hard mask includes silicon nitride.

The method for making trench capacitor shallow trench insulation is characterized in that: the buffer layer is made of silicon nitride.

The method for making trench capacitor shallow trench insulation is characterized in that: the thickness of the buffer layer is about 500 angstroms.

In the preferred embodiment of the present invention, a method for manufacturing trench capacitor shallow trench insulation is disclosed, which includes providing a semiconductor substrate with a hard mask on it, wherein a plurality of deep trenches have been formed on the semiconductor substrate A trench capacitor structure, each of the deep trench capacitor structures includes a capacitor electrode, a capacitor dielectric layer, a capacitor lower electrode, and a neck oxide layer; a dielectric layer is deposited on the semiconductor substrate; and the dielectric layer is planarized to On the surface of the hard mask, the remaining dielectric layer fills the recessed gap above the deep trench capacitor structure; a buffer layer is deposited on the semiconductor substrate; a shallow trench insulation pattern is formed on the buffer layer The photoresist mask of the opening; perform a plasma dry etching, through the opening of the shallow trench insulation pattern, use the dielectric layer and the neck oxide layer as an etching mask to protect each of the deep trench capacitor structures, and selectively etch The buffer layer, the hard mask, and finally etch the semiconductor substrate to form insulating shallow trenches; and filling trench insulating materials in the insulating shallow trenches.

The advantages of the present invention are:

Compared with the prior art, after the deep trench capacitor structure is completed, the present invention fills the recessed gap on the deep trench capacitor structure with a silicon-oxygen dielectric layer, then covers a silicon nitride buffer layer, and finally forms a shallow capacitor by selective etching. Trench insulation. In this way, the use of an overly thick doped silica glass layer 32 can be avoided, and thus the CD uniformity can be controlled. In addition, since the present invention does not etch the deep trench capacitor structure 20 , the etching recipe used in the etching of the STI is relatively simple and easy to control. In addition, the process of the present invention is more compatible with the logic process.

Description of drawings

FIG. 1 to FIG. 5 are schematic cross-sectional views of shallow trench insulation for making trench capacitors in the prior art.

6 to 11 are schematic cross-sectional views of the fabrication method of shallow trench insulation for trench capacitance compatible with logic process according to the present invention.

Detailed ways

Please refer to FIG. 6 to FIG. 11 . FIG. 6 to FIG. 11 are cross-sectional schematic diagrams of the trench capacitor shallow trench isolation manufacturing method compatible with the logic process of the present invention, wherein the same or similar components and regions still use the same symbols. As shown in FIG. 6 , the semiconductor chip 1 is divided into a logic area 11 and a memory array area 12 . A plurality of deep trench capacitor structures 20 have been fabricated in the storage array area 12 of the semiconductor chip 1 in FIG. 1 . The fabrication of the deep trench capacitor structure 20 is to first etch a deep trench opening (not shown) in the silicon substrate 10 through the hard mask 14, and then form a capacitor electrode, a capacitor dielectric layer 22, a capacitor lower electrode 24 and a neck electrode in the opening. Oxide layer 26. A recessed gap 28 is formed above the deep trench capacitor structure 20 .

As shown in FIG. 7 , a dielectric layer, preferably a silicon oxide layer formed by high-density plasma chemical vapor deposition (HDPCVD) is deposited on the semiconductor chip 1 . Next, a chemical mechanical polishing process is performed, and the hard mask 14 is used as a polishing stop layer to planarize the dielectric layer to the surface of the hard mask 14 . The remaining dielectric layer 62 fills the recessed gap 28 above the deep trench capacitor structure 20 . At this time, the semiconductor chip 1 has a nearly flat surface profile.

As shown in FIG. 8 , a buffer layer 64 with a thickness of about 500 angstroms is then deposited on the surface of the semiconductor chip 1 . The buffer layer 64 can be silicon nitride or silicon oxynitride (SiON), preferably silicon nitride, but not limited thereto. As shown in FIG. 9, a bottom anti-reflection layer 34 is deposited on the buffer layer 64, and then a photoresist layer is coated on the bottom anti-reflection layer 34, and then the photoresist layer is photolithographically imaged with the existing yellow light process. , and baked to form the STI pattern opening 43 defining the memory array region 12 and the photoresist mask 36 defining the STI pattern opening 45 in the logic region 11 . In other embodiments, the bottom anti-reflection layer 34 may also be omitted.

As shown in FIG. 10 , plasma dry etching is then performed to pass through the STI pattern opening 43 and the STI pattern opening 45, and use the dielectric layer 62 and the neck oxide layer 26 as an etching mask to protect each deep trench capacitor structure 20 , selectively etching the bottom anti-reflection layer 34 , the buffer layer 64 , the hard mask 14 , and finally etching the silicon substrate 10 to form the insulating shallow trenches 53 of the memory array area 12 and the insulating shallow trenches 54 of the logic area 11 . It can be seen from the figure that the plasma composition used for etching the insulating shallow trench is only for the selective etching of the bottom anti-reflective layer 34, the buffer layer 64, the hard mask 14 and the silicon substrate 10, but for the dielectric layer 62 and the neck The oxide layer 26 has a high etch selectivity, so the damage to the deep trench capacitor structure 20 is small, thereby forming a T-shaped cross-section insulating shallow trench 53 in the memory array region 12 as shown in the figure.

Finally, as shown in FIG. 11 , the photoresist mask 36 and the bottom anti-reflective layer 34 are removed, and then trench insulating material 58 is filled in the insulating shallow trench 53 and the insulating shallow trench 55, and planarized, and the present invention is completed. Fabrication of Trench Capacitor Shallow Trench Insulation.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the patent of the present invention.

Claims (10)

1. A method for making trench capacitor shallow trench insulation, comprising: Provide a semiconductor substrate with a hard mask on it, wherein the surface of the semiconductor substrate is divided into a logic area and a storage array area, and a plurality of deep trench capacitor structures have been fabricated in the storage array area, and each deep trench capacitor The structure includes a capacitor electrode, a capacitor dielectric layer, a capacitor lower electrode and a neck oxide layer; its features are: depositing a dielectric layer on the semiconductor substrate; planarizing the dielectric layer to the surface of the hard mask, and the remaining dielectric layer fills the recessed gap above the deep trench capacitor structure; depositing a buffer layer on the semiconductor substrate; depositing a bottom anti-reflection layer on the buffer layer; Forming a photoresist mask defining an opening of a shallow trench insulation pattern in a memory array area and an opening of a shallow trench insulation pattern in a logic area on the bottom anti-reflection layer; Performing a plasma dry etching, protecting each of the deep trench capacitor structures by using the dielectric layer and the neck oxide layer as an etching mask through the opening of the shallow trench insulation pattern in the memory array area and the opening of the shallow trench insulation pattern in the logic area, Selectively etch the bottom anti-reflection layer, the buffer layer, and the hard mask, and finally etch the semiconductor substrate to form insulating shallow trenches in the memory array area and shallow insulating trenches in the logic area; removing the photoresist mask and bottom anti-reflection layer; and Trench insulating material is filled in the insulating shallow trenches in the storage array area and the insulating shallow trenches in the logic area. 2. The method for making trench capacitor shallow trench insulation according to claim 1, characterized in that: the method for planarizing the dielectric layer is to use a chemical mechanical polishing process, and use the hard mask as a polishing stop layer, planarizing the dielectric layer to the hardmask surface. 3. The method for manufacturing trench capacitor STI according to claim 1, characterized in that: the hard mask comprises silicon nitride. 4. The method for manufacturing trench capacitor STI according to claim 1, wherein the buffer layer is made of silicon nitride. 5. The method for manufacturing trench capacitor shallow trench insulation according to claim 1, wherein the thickness of the buffer layer is about 500 angstroms. 6. A method for making trench capacitor shallow trench insulation, comprising: Provide a semiconductor substrate with a hard mask on it, wherein a plurality of deep trench capacitor structures have been fabricated on the semiconductor substrate, each of the deep trench capacitor structures includes a capacitor electrode, a capacitor dielectric layer, a capacitor lower electrode and Neck oxide layer; characterized by: depositing a dielectric layer on the semiconductor substrate; planarizing the dielectric layer to the surface of the hard mask, and the remaining dielectric layer fills the recessed gap above the deep trench capacitor structure; depositing a buffer layer on the semiconductor substrate; forming a photoresist mask defining an opening of a STI pattern on the buffer layer; Performing a plasma dry etching, through the opening of the shallow trench insulation pattern, using the dielectric layer and the neck oxide layer as an etching mask to protect each of the deep trench capacitor structures, and selectively etching the buffer layer and the hard mask film, and finally etch the semiconductor substrate to form insulating shallow trenches; removing the photoresist mask; and The trench insulating material is filled in the insulating shallow trench. 7. The method for making trench capacitor shallow trench insulation according to claim 6, characterized in that: the method of planarizing the dielectric layer is to use a chemical mechanical polishing process, and use the hard mask as a polishing stop layer, planarizing the dielectric layer to the hardmask surface. 8. The method for manufacturing trench capacitor STI according to claim 6, characterized in that: the hard mask comprises silicon nitride. 9. The method for manufacturing trench capacitor STI according to claim 6, wherein the buffer layer is made of silicon nitride. 10. The method for manufacturing trench capacitor shallow trench insulation according to claim 6, wherein the buffer layer has a thickness of about 500 angstroms.

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