CN1255869C - Fault Location Method of Scan Chain in Logic Integrated Circuit - Google Patents

Abstract

For each corresponding scan chain set in a plurality of logic integrated circuits with the same configuration, a plurality of initial value vectors related to an inverter are extracted. And comparing the initial value vectors in the same corresponding scan chain set with each other to confirm elements with fixed values in the initial value vectors. When the number of the elements with the fixed value reaches a predetermined percentage, the elements with the fixed value are selected as a standard pattern of the corresponding scan chain set. And comparing the initial value vector of the scan chain in the logic integrated circuit to be subjected to fault location with the standard pattern related to the scan chain so as to determine whether the scan chain in the logic integrated circuit to be subjected to fault location has a fault inverter.

Description

Fault Location Method of Scan Chain in Logic Integrated Circuit

technical field

The invention relates to a fault location method for logic integrated circuits. In particular, the invention relates to a method for fault location of a scan chain in a logic integrated circuit.

Background technique

In order to meet the needs of the computer, communication, and consumer electronics markets, the semiconductor industry has begun to move towards the development direction of integrating the entire complex system on a single chip. With the continuous advancement of semiconductor manufacturing technology, the total number of logic gates that can be accommodated in a single chip design is also increasing. It is foreseeable that this trend will continue in the next few years. Faced with the sharp increase in chip complexity, the accompanying chip failure analysis is also more difficult.

In the testing of logic integrated circuits, scanning is a very effective design for test (DFT) with very high fault coverage. It can enter the test mode without affecting the normal operation of the logic integrated circuit, and use the scan chain formed by the inverter to detect the fault point in the logic circuit. Referring to FIG. 1 , a method for analyzing faults of logic integrated circuits by scanning is briefly described below.

A logic integrated circuit 1 includes various functional circuit modules 13 . In order to test that the logic integrated circuit 1 can operate normally, multiple scan chains are designed in the logic integrated circuit 1, such as 121, 122, and 123 marked in Figure 1. The scan chain is composed of a plurality of inverters. It is connected with each functional circuit module 13 . For example, the scan chain 121 is composed of a plurality of inverters 1211 and connected to the functional circuit module 13 . When entering the test mode, the functional circuit module 13 transmits the execution result to the connected inverter 1211, and transmits the result to the next inverter 1211 as the time period changes, and finally outputs the result of the entire scan chain, as shown in the figure 1 marked 1212, 1222, 1232. Then, according to the correct output result of the scan chain output, it can be judged that the output result of a certain inverter of a certain scan chain is incorrect, and the fault point of the logic integrated circuit 1 is located to achieve the purpose of fault analysis.

In the application of the above fault analysis method, a reset circuit 11 with a reset (set/reset) function must be designed in the logic integrated circuit 1 to set the initial state of the inverter to logic 0 or logic 1, generally Set to logic 0. As the complexity of the chip increases, the number of scan chains must be increased to effectively locate the fault point in the functional circuit module 13 . Therefore, the number of reset circuits also increases along with the increase in the number of scan chains. Some of the reset circuits have special functions, while some reset circuits are only used for resetting the initial values of the inverters in the scan chain. These reset circuits solely for resetting the initial value of the inverter occupy a certain area of the wafer, making the design of the wafer unable to be effectively reduced, and at the same time making the number of wafers produced per unit wafer area less.

Contents of the invention

In order to overcome the deficiencies in the prior art, an object of the present invention is to provide a fault location method for a scan chain in a logic integrated circuit, which can effectively reduce the chip area.

Another object of the present invention is to provide a fault location method for a scan chain in a logic integrated circuit, which can produce more chips per unit wafer area.

In order to achieve the above object, the present invention provides a fault location method for a scan chain in a logic integrated circuit, the logic integrated circuit includes at least one scan chain, the scan chain is composed of a plurality of inverters, characterized in that: the method includes :,.

A step of collecting initial values, the step of collecting initial values is used to retrieve a plurality of initial value vectors associated with inverters for each corresponding scan chain set in a plurality of logic integrated circuits with the same configuration as statistical samples;

A selected standard pattern step, the selected standard pattern step is used to compare the initial value vectors in the same corresponding scan chain set with each other to confirm that the initial value vector has a fixed value for each corresponding scan chain set element, when the number of the elements with the fixed value reaches a predetermined percentage, select the element with the fixed value as a standard pattern of the corresponding scan chain set; and

A fault location step, the fault location step is used to compare the initial value vector of the scan chain in the logic integrated circuit for fault location and the standard pattern associated with the scan chain, so as to determine the fault location Whether the scan chain in the logic IC has a faulty inverter.

In addition, the step of locating the fault further includes: locating the faulty inverter when the scan chain in the logic integrated circuit to be faulty is determined to have a faulty inverter.

Moreover, the fault location step further includes: when a faulty inverter is found in the scan chain in the logic integrated circuit to be faulty located, referring to a logic integrated circuit layout to find the faulty logic integrated circuit fault location.

According to the fault location method of the scan chain in the logic integrated circuit of the present invention, there is no need to design redundant reset circuits in the logic integrated circuit, and at the same time, the fault analysis and location of the logic integrated circuit still maintains extremely high accuracy. Therefore, the area of a single wafer can be effectively reduced, and a larger number of wafers can be produced per unit wafer area.

Description of drawings

FIG. 1 shows a schematic diagram of the configuration of a logic integrated circuit in the prior art.

FIG. 2 shows a flowchart of a fault location method for a scan chain in a logic integrated circuit according to the present invention.

FIG. 3 shows a schematic diagram of the configuration of a logic integrated circuit according to the present invention.

FIG. 4 shows a schematic diagram of a plurality of logic integrated circuits distributed on a single wafer and different wafers as a statistical sample.

Description of component symbols:

1 Known logic integrated circuits

11 Reset circuit

121, 122, 123 scan chain

1211, 1221, 1231 Inverter

1212, 1222, 1232 Scan chain output

13 Functional circuit module

3 The logic integrated circuit of the present invention

311, 312, 313 scan chain

3111～3116 Inverter

32 Functional circuit module

33 Initial value vector

41, 42 Wafer

411, 421, 422, 423 wafers

S21 Collect initial value step

S22 Select standard drawing steps

S23 Fault location steps

Detailed ways

The method for locating a scan chain fault in a logic integrated circuit according to a preferred embodiment of the present invention will be described below with reference to the accompanying drawings, wherein the same components will be described with the same reference symbols.

Please refer to FIG. 2 , which shows a fault location method for a scan chain in a logic integrated circuit according to the present invention, wherein the logic integrated circuit includes at least one scan chain, and each scan chain is composed of a plurality of inverters. The method includes: a step S21 of collecting initial values, a step S22 of selecting a standard pattern, and a step S23 of fault location.

The initial value collection step S21 retrieves an initial value vector associated with an inverter for each corresponding scan chain set in a plurality of logic integrated circuits with the same configuration as a statistical sample. For example, please refer to FIG. 3 , which shows a logic integrated circuit 3 in a statistical sample, which includes a plurality of scan chains 311 , 312 , and 313 and a plurality of functional circuit modules 32 . The scan chain 311 is composed of six inverters 3111 , 3112 , 3113 , 3114 , 3115 , and 3116 . The initial values of the inverters 3111, 3112, 3113, 3114, 3115, and 3116 are read from the logic integrated circuit 3 according to the cycle of the scan clock. For example, the initial values of the inverters 3111 , 3112 , 3113 , 3114 , 3115 , and 3116 in the scan chain 311 are output through the inverter 3116 according to the period of the scan clock. In this case, the initial value of the inverter 3116 is first output, and then the initial values of the inverters 3115 , 3114 , 3113 , 3112 , and 3111 are output sequentially. For example, as shown in FIG. 3 , the initial state vector 33 of the scan chain 311 is 010101, which represents the initial states of the inverters 3111, 3112, 3113, 3114, 3115, and 3116 in the scan chain 311. value. Similarly, after a specific time period determined based on the number of inverters of the scan chains 312 and 313 , the initial value vectors associated with the inverters of the scan chains 312 and 313 can be obtained respectively.

As mentioned above, multiple logic integrated circuits with the same configuration are used as statistical samples in the present invention. For example, FIG. 4 shows a plurality of logic integrated circuits of the same configuration, each of which is represented by a rectangle. The plurality of logical integrated circuits with the same configuration can be formed on different wafers (such as wafer 411 of wafer 41 and wafer 421 of wafer 42), or formed on different locations of the same wafer (such as wafer 42 of wafer 42). wafers 421, 422, and 423). The plurality of scan chains in the plurality of logic integrated circuits with the same configuration can be classified into a plurality of corresponding scan chain sets. The initial value collection step S21 retrieves initial value vectors for each scan chain in each grid, and classifies the initial value vectors belonging to the same set of corresponding scan chains together for subsequent steps.

The selected standard pattern step S22 compares the initial value vectors in the corresponding scan chain set with each other from the initial value vectors collected in the initial value collection step S21 to confirm that there is a fixed value (logic 0 or logic 0 in the initial value vector) 1) Elements. Theoretically, the initial value vectors in the same set of corresponding scan chains should be identical to each other. However, due to unavoidable manufacturing process variations in the integrated circuit manufacturing process, the initial value vectors in the same set of corresponding scan chains are actually not exactly the same. Therefore, the step S22 of selecting a standard pattern uses a statistical method to determine the position and number of elements with fixed values in the initial value vector for each corresponding scan chain set. When the number of the elements with fixed values reaches a statistically significant value, the elements with fixed values can be used to represent the initial value vector associated with the scan chain. In the following, this representative vector of initial values is called the golden pattern.

The fault location step S23 is to compare the initial value of the scan chain in a logic integrated circuit to be fault located with the standard pattern associated with the scan chain, so as to determine whether the scan chain in the logic integrated circuit to be fault located is Faulty inverter. When a faulty inverter is identified in the scan chain in the logic integrated circuit to be fault located, the fault location step S23 can also locate the faulty inverter.

In order to make the fault location method of the scan chain in the logic integrated circuit of the present invention easier to understand, an example is given to illustrate. As shown in Table 1 below, suppose there is a logic integrated circuit, which includes scan chains A, B, and C, etc., and the number of inverters used to form scan chains A, B, and C are 1045, 900, and 2000, respectively. . According to the method of the present invention, first according to the step of collecting the initial value, the automatic test equipment (Automatic Test Equipment, ATE) collects the scan chains A, B, and C, etc. vector of initial values for the device.

Table 1 scan chain number scan chain length number of elements in the initial value vector fixed to logical 1 Number of elements in the initial value vector fixed to logical 0 number of elements in the initializer vector with fixed values % of all elements A 1045 501 483 984 94.2% B 900 380 478 858 95.3% C 2000 1120 725 1845 92.3%      

Next, according to the step of selecting a standard pattern, each initial value vector in the same corresponding scan chain set is compared with each other to confirm elements with fixed values (logic 0 or logic 1) in the initial value vector. Taking scan chain A in Table 1 as an example, in the corresponding scan chain set of scan chain A, the number of elements fixed as logic 1 in the initial value vector is 501, and the number of elements fixed as logic 0 is 483. Therefore, the total number of elements with fixed values in the initial value vector is 984, accounting for 94.2% (=984/1045×100%) of the number of all elements in the initial value vector of scan chain A. If it is assumed that when the number of elements with fixed values in the initial value vector exceeds 90% of the number of all elements, these elements with fixed values can be used as the standard pattern associated with the scan chain, then the standard pattern of scan chain A is was identified. Similarly, the standard patterns of scan chain B and scan chain C are also determined in the same manner.

In the fault location step, the automatic test equipment is first used to collect the initial value vector of the scan chain in the logic integrated circuit to be fault located. Then, comparing the initial value vector of the scan chain in the logic integrated circuit for fault location with the standard pattern of the scan chain, so as to determine whether the scan chain in the logic integrated circuit for fault location has a faulty inverter. For example, Table 2 shows the initial value vector and a part of the standard pattern of the scan chain for fault location. It can be known from Table 2 that in the 54th to 59th inverters, the initial value vector of the scan chain to be fault located is the same as that of the standard pattern. However, in the 50th to 53rd inverters, the value of the initial value vector of the scan chain to be fault location is different from the value of the standard pattern, and the scan chain to be fault location corresponds to the 50th to 53rd The initial values of the inverters are all logic 0. Accordingly, it can be deduced that the initial value of the 53rd inverter fails when it is passed to the 54th inverter, so that no matter what the initial values of the 50th to 53rd inverters are, they all output after passing through the 54th inverter to logic 0.

Table 2 Inverter number … 50 51 52 53 54 55 56 57 58 59 … Initial value vector of a scan chain of a logic integrated circuit to be fault located … 0 0 0 0 1 1 1 1 0 0 … The standard pattern of the scan chain … 1 1 1 1 1 1 1 1 0 0 …

If you want to further find out the cause of the fault, you can refer to the circuit layout of the logic integrated circuit to be fault located, start from the connection path from the 53rd inverter to the 54th inverter, and gradually find out the cause of the fault . The possible range of faults must include the connection path from the 53rd inverter to the 54th inverter, and all metal wires that have an equipotential effect with this path.

According to the fault location method of the scan chain in the logic integrated circuit of the present invention, there is no need to use a reset circuit in the logic integrated circuit, the area of a single chip can be effectively reduced, and more chips can be produced per unit wafer. In addition, the fault location method of the scan chain in the logic integrated circuit according to the present invention has extremely high accuracy for the fault analysis and location of the logic integrated circuit, and can effectively locate the fault point.

The above descriptions are illustrative only, not restrictive. Anyone skilled in the art can make equivalent modifications based on the above-mentioned embodiments of the present invention without departing from its spirit and scope. For example, in the foregoing embodiments, the number of elements with fixed values in the initial value vector exceeds 90% of all elements, as the selection condition for the standard pattern. However, anyone skilled in the art can adjust the ratio to 80% or 99% according to the conditions or stability of the manufacturing process, or the design of the logic integrated circuit. In addition, several scan chains need to be monitored for a single logic integrated circuit, and appropriate adjustments can be made according to factors such as manpower, complexity of the logic integrated circuit, and manufacturing difficulty. Therefore, any equivalent modification or change without departing from the spirit and scope of the present invention shall be included in the claims of the present invention.

Claims (6)

1. A method for fault location of a scan chain in a logic integrated circuit, the logic integrated circuit includes a plurality of scan chains, the scan chain is made up of a plurality of inverters, it is characterized in that: the method includes: A step of collecting initial values, for using an automatic test equipment to retrieve a plurality of initial value vectors associated with the inverters for each corresponding scan chain set in a plurality of logic integrated circuits with the same configuration as statistical samples; a selected standard pattern step for comparing each initial value vector in the same set of corresponding scan chains with each other to confirm for each corresponding set of scan chains that an element with a fixed value in the initial value vector, when the selecting the element with the fixed value as a standard pattern of the corresponding scan chain set when the number of the elements with the fixed value reaches a predetermined percentage; and A fault location step, which is used to compare the initial value of the scan chain in the logic integrated circuit for fault location with the standard pattern associated with the scan chain, so as to determine the scan in the logic integrated circuit for fault location Whether the chain has a faulty inverter. 2. The fault location method for scan chains in logic integrated circuits as claimed in claim 1, wherein the initial value vector is arranged by data stored in each of the plurality of inverters, and the data to logic 0 or logic 1. 3. The method for fault location of a scan chain in a logic integrated circuit as claimed in claim 1, wherein the initial value of the scan chain in the logic integrated circuit to be fault located is collected by an automatic test equipment. 4. The fault location method of scan chain in the logic integrated circuit as claimed in claim 1, is characterized in that: this fault location step also comprises: When the scan chain in the logic integrated circuit to be fault located is determined to have a faulty inverter, the faulty inverter is located. 5. The fault location method of scan chain in logic integrated circuit as claimed in claim 1, is characterized in that: this fault location step also comprises: When the scan chain in the logic integrated circuit to be fault located is determined to have a faulty inverter, a fault location of the faulty logic integrated circuit is found by referring to a logic integrated circuit layout. 6. The fault location method of the scan chain in the logic integrated circuit as claimed in claim 5, characterized in that: the scope of the fault location of the fault logic integrated circuit includes the connection path between the inverter of the fault and the fault logic integrated circuit And all the metal wires associated with that faulty inverter.

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