CN101566669A - Semiconductor integrated circuit device and device and method for reliability test thereof - Google Patents

Abstract

The invention discloses a semiconductor integrated circuit device and a device and a method for a reliability test thereof. The circuit device comprises an either-or circuit module, three triggers and a voter. The device realizes the function of a scan trigger while realizing triple module redundancy of a storage node, and improves the reliability and mensurability of a semiconductor integrated circuit chip with lower cost by a simple digital logic circuit.

Description

A semiconductor integrated circuit device and its reliability testing device and testing method

technical field

The present invention relates to the technical field of semiconductor integrated circuits, in particular to the field of high reliability semiconductor integrated circuit design and the field of semiconductor integrated circuit testing, more specifically, the present invention relates to a highly reliable semiconductor integrated circuit device and its reliability testing device and Test Methods.

Background technique

In the field of semiconductor integrated circuit chip design, with the increasing scale of integrated circuits, the number of transistors accommodated on a single integrated circuit is increasing, and even functional modules such as processor cores, memories, and DSP cores are also integrated into a single chip. SOC (System on Chip, System on Chip) is formed in it. This leads to an increasing complexity of integrated circuits. According to the basic point of view in the field of fault tolerance, the more complex the system, the lower the reliability. On the other hand, the feature size of integrated circuits presents a decreasing trend, which leads to an increase in the probability of failures such as electromigration and gate oxide breakdown, resulting in permanent failures; at the same time, integrated circuits with small feature sizes are also more susceptible to high energy Under the influence of particle rays, etc., single event effects appear, forming various failures including "soft errors".

The above reasons make reliability a problem that must be solved in integrated circuit design.

The method of triple-mode redundancy is a commonly used method to improve the reliability of integrated circuits, especially storage nodes such as flip-flops. The method of triple-mode redundancy and voting can effectively improve the reliability of integrated circuit chips. However, due to the fault tolerance of the triple-mode redundancy, the failure of the redundant logic cannot be screened out, thus reducing the reliability of the system to a certain extent.

In the field of semiconductor integrated circuit chip testing, the testability of semiconductor integrated circuits has become more and more difficult with the increase of the complexity of integrated circuits. It is difficult to screen out faults in chips only by using functional vector coverage. faults cannot be detected. In the field of testing, the method of inserting scan chains for testing is widely adopted in the industry. The method is to replace conventional flip-flops with scan flip-flops, scan flip-flops are connected in one or several scan chains, use specific tools to generate scan data (also called scan vectors), and use scan clocks to transfer scan data to each scan trigger device. The scan output is then observed and compared to expected results to identify faults. Tools can be used to generate a variety of scan data in order to cover as many possible errors as possible.

But the overhead of replacing regular flip-flops with scan flip-flops is very high. In a circuit with a scanning design, the scanning unit and its control circuit will occupy 30% of the total area of the chip. Even in a microprocessor chip where memory components occupy most of the area, the silicon area occupied by the scanning unit and its control circuit is still large compared to the combinational logic circuit. And the commonly used scanning test method cannot test the errors in the redundant logic.

The practice of triple-mode redundancy has greatly increased the number of storage nodes in an integrated circuit, thereby significantly increasing the chip area. If all the flip-flops of the triple-mode redundancy are replaced with scan flip-flops, the chip area will be larger, and the increase of the chip area will further reduce its reliability.

Contents of the invention

The object of the present invention is to provide a semiconductor integrated circuit device and its reliability device and testing method, which realizes the function of a scan flip-flop while realizing triple-mode redundancy, saves chip area, and improves the reliability of the semiconductor integrated circuit chip. sex.

A semiconductor integrated circuit device, including at least one reliability testing device, the reliability testing device includes an alternative circuit module, three flip-flops, and a voter;

The output terminals of the two alternative circuit modules are respectively connected to the data input terminals of the three flip-flops;

The output terminals of the three flip-flops are respectively connected to the three input terminals of the voter;

The clock terminals of the three flip-flops are not connected, and they are respectively driven by the clock trees of the three semiconductor integrated circuits.

The clock trees are clock trees CK0, CK1, and CK2 of semiconductor integrated circuits.

The voter is a three-input voting circuit device.

The three clock trees input a clock from a pin of the semiconductor integrated circuit device, and then branch and control at the starting point of the clock tree.

The three clock trees are input by multiple pins of the semiconductor integrated circuit device, and each clock is individually controlled to be turned on, off and connected to other clocks.

The integrated circuit device further includes at least one scan chain, and the scan chain links the data output of each level of reliability testing device with the scan data input of the next level of reliability testing device.

The semiconductor integrated circuit device is a semiconductor digital integrated circuit.

In order to realize the purpose of the present invention, a reliability testing device for a semiconductor integrated circuit device is also provided, which includes a two-choice one circuit module, three flip-flops, and a voting device;

The output terminals of the two alternative circuit modules are respectively connected to the data input terminals of the three flip-flops;

The output terminals of the three flip-flops are respectively connected to the three input terminals of the voter;

The clock terminals of the three flip-flops are not connected, and they are respectively driven by the clock trees of the three semiconductor integrated circuits.

In order to realize the purpose of the present invention, a reliability testing method of a semiconductor integrated circuit device is further provided, comprising the following steps:

Step A, controlling the on and off states of the three clock trees of the semiconductor integrated circuit, and assigning an initial value to the flip-flop of the reliability device through the scan chain of the semiconductor integrated circuit;

Step B, turn off some clocks, turn on and connect the rest of the clocks, and perform a scan test.

Step C, repeating the operations from step A to step B until the test combination is completed, and the faults in the semiconductor integrated circuit are tested.

In the step A, the assigning an initial value to the trigger includes the following steps:

In the scanning state, all the three clock trees of the semiconductor integrated circuit are turned on and connected, and the constant value "0" is set at the input end of the scan chain and scanned for a long enough time to assign the initial value "0" to all flip-flops.

In the step B, a scanning test is carried out, including the following steps:

Turn off the clock CK0, turn on and connect the clocks CK1 and CK2, and perform a scan test.

In the step A, the assigning an initial value to the trigger includes the following steps:

In the scanning state, first assign the initial value "0" to all flip-flops, then turn off CK0, set a constant value "1" at the input of the scan chain and scan for a long enough time, the final result is the initial value of the flip-flop corresponding to CK0 is "0", and the initial value of other flip-flops is "1".

In the step B, a scanning test is carried out, including the following steps:

Turn off the clocks CK0 and CK1, turn on the clock CK2, and perform a scan test.

In the step C, the fault in the semiconductor integrated circuit is tested, including the following steps:

If the test results of all test combinations are consistent, it is sufficient to indicate that there is no fault in the chip;

If the test results under any one or several combinations are inconsistent, it means that there is a fault.

The beneficial effects of the present invention are: the reliability device and testing method of the semiconductor integrated circuit of the present invention realize the scanning test of the semiconductor integrated circuit reinforced by triple-mode redundancy reliability with a relatively small area overhead, and solve the problems in the usual scanning test. Unable to detect redundant logic errors. Therefore, the purpose of improving the reliability of the semiconductor integrated circuit chip is achieved.

Description of drawings

Fig. 1 is the circuit diagram of the reliability testing device of semiconductor integrated circuit device of the present invention;

Fig. 2 is a working flow chart of the testing method of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, a semiconductor integrated circuit device and its reliability testing device and testing method of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

The semiconductor integrated circuit device and its reliability testing device and testing method of the present invention improve the reliability of storage nodes at the cost of a small area, and at the same time control the clocks separately so that faults in redundant logic can be detected out, thereby ensuring the reliability of the semiconductor integrated circuit.

In order to achieve the above object, the present invention provides a semiconductor integrated circuit device, including a scan chain, which also includes at least one reliability testing device, as shown in Figure 1, the reliability testing device includes a two-choice circuit module 11, Three flip-flops 12, 13 and 14, and a voter 15.

The semiconductor integrated circuit device includes a scan chain, and the scan chain links the data output of each level of reliability testing device with the scan data input of the next level of reliability testing device.

The output end of the two-choice circuit module 11 is respectively connected to the data input ends of three flip-flops 12, 13 and 14;

The output terminals of the three flip-flops 12, 13 and 14 are respectively connected to the three input terminals of the voter 15;

The clock terminals of the three flip-flops 12, 13 and 14 are not connected, and they are respectively driven by the clock trees CK0, CK1 and CK2 of the three semiconductor integrated circuits;

The one-of-two circuit module, flip-flop and voter are all typical circuits in the field of integrated circuit design.

The one-of-two circuit module is a commonly used circuit module in the existing reliability testing circuit. It is used for its data output from the scan data input terminal in the scanning state and its output from the data input terminal in the normal working state. That is, the function of the one-out-of-the-two circuit module is to select whether the integrated circuit device works in the reliability test state or in the normal work state.

The voter can be any kind of three-input voting circuit device.

The role of the voter comes from the concept of triple-mode redundancy. The so-called triple-mode redundancy means that a piece of data is stored in three locations. If the data in a certain location is wrong for some reason, then because of the existence of the voter, the output When the data of these three positions are voted, the correct data can be finally given (two correct VS one wrong = correct result).

As a possible implementation, the three clock trees CK1, CK2, and CK3 can be input with a clock from a pin of the semiconductor integrated circuit chip device, and then branched and controlled at the starting point of the clock tree.

As another possible implementation, the three clock trees CK1 , CK2 , and CK3 can be generated by other methods and input by multiple pins, which can individually control the on and off of each clock and its connection with other clocks.

The reliability testing device is a triple-mode redundant storage circuit in normal operation, which acts as a trigger.

In the scanning state, the reliability testing device can control the three clock tree terminals respectively, so as to realize the scanning test of the combined circuit between the pipeline stages and the test of the redundant logic itself.

The semiconductor integrated circuit device may be a semiconductor digital integrated circuit with various functions and types.

The present invention also provides a semiconductor integrated circuit reliability testing method. The working process of the semiconductor integrated circuit reliability testing method of the present invention will be described in detail below with reference to FIG. 2 . The method includes the following steps:

Step S100, controlling the on and off states of the three clock trees of the semiconductor integrated circuit, and assigning an initial value to the flip-flop of the reliability testing device in the scanning state through the scan chain of the semiconductor integrated circuit;

As a method that can be implemented (mode M), it is possible to turn on and connect all three clock trees of the semiconductor integrated circuit in the scanning state (that is, "scan enable" is high), and set a constant value at the input end of the scanning chain "0" and scan long enough to assign an initial value of "0" to all flip-flops.

As another method that can be implemented (mode N), it is also possible to set all flip-flops to the initial value "0" in the scanning state (that is, "scan enable" is high), and then turn off CK0. The input terminal is set to a constant value "1" and scanned for a long enough time. The final result is that the initial value of flip-flop 12 is "0", and the initial value of flip-flops 13 and 14 is "1".

The opening, closing and connection of the three clocks of the semiconductor integrated circuit are existing integrated circuit design techniques, so they will not be described in detail in the present invention.

Step S200, turn off some clocks, turn on and connect the remaining clocks, and perform a scan test;

If the method M is used to assign the initial value in step S100, the clock CK0 can be turned off, the clocks CK1 and CK2 can be turned on and connected, and the scan test can be performed by using a common scan test method.

If the method N is used to assign the initial value in step S100, the clocks CK0 and CK1 can be turned off, the clock CK2 can be turned on, and a common scan test method is used to perform a scan test.

The common scan test method is an existing integrated circuit scan test method in the industry, so it will not be described in detail in the present invention.

In step 300, the operations from step S100 to step S200 are repeated until the test combination is completed, and the fault in the semiconductor integrated circuit is tested.

If the test results of all test combinations are consistent, it is sufficient to indicate that there is no fault in the chip;

If the test results under any one or several combinations are inconsistent, at least it indicates that there is a fault, and more scanning test vectors are needed to locate the specific fault.

The generation of scan test vectors is a part of the common scan test method, which is an existing IC scan test vector generation method in the industry, so it will not be described in detail in the present invention.

In the embodiment of the present invention, the complete test combination may be the following combination:

Assign initial value "0" to flip-flops 11, 12 and 13, turn off CK0, turn on and connect CK1 and CK2 for testing;

Assign initial value "0" to flip-flops 11, 12 and 13, turn off CK1, turn on and connect CK0 and CK2 for testing;

Assign initial value "0" to flip-flops 11, 12 and 13, turn off CK2, turn on and connect CK0 and CK1 for testing;

Assign initial value "1" to flip-flops 11, 12 and 13, turn off CK0, turn on and connect CK1 and CK2 for testing;

Assign initial value "1" to flip-flops 11, 12 and 13, turn off CK1, turn on and connect CK0 and CK2 for testing;

Assign initial value "1" to flip-flops 11, 12 and 13, turn off CK2, turn on and connect CK0 and CK1 for testing;

As another implementation, the complete test combination can also be the following combination:

Trigger 11 is assigned an initial value of "0", 12 is assigned an initial value of "1", CK0 and CK1 are turned off, and CK2 is turned on for testing;

Trigger 11 assigns an initial value "1", 12 assigns an initial value "0", turns off CK0 and CK1, and turns on CK2 test;

Trigger 11 is assigned an initial value of "0", 13 is assigned an initial value of "1", CK0 and CK2 are turned off, and CK1 test is turned on;

Trigger 11 assigns an initial value "1", 13 assigns an initial value "0", turns off CK0 and CK2, and turns on CK1 test;

Trigger 12 assigns initial value "0", 13 assigns initial value "1", turns off CK1 and CK2, and turns on CK0 test;

Trigger 12 assigns initial value "1", 13 assigns initial value "0", turns off CK1 and CK2, and turns on CK0 test;

The semiconductor integrated circuit device and its reliability testing device and testing method of the present invention improve the reliability of storage nodes at the cost of a small area, and at the same time control the clocks separately so that faults in redundant logic can be detected out, thereby ensuring the reliability of the semiconductor integrated circuit. Adopting the semiconductor integrated circuit of the invention can realize high reliability and high testability of the system with simple digital logic circuit and relatively small cost.

The method for testing the reliability of the semiconductor integrated circuit of the present invention is simple to implement, and the reinforcement of the reliability can be completed only by using a general digital logic circuit, which is simple and easy to use.

Other aspects and features of the present invention will be apparent to those skilled in the art from the above description of specific embodiments of the present invention in conjunction with the accompanying drawings.

The specific embodiments of the present invention have been described and illustrated above, and these embodiments should be considered as exemplary only, and are not used to limit the present invention, and the present invention should be interpreted according to the appended claims.

Claims (18)

1. A semiconductor integrated circuit device, characterized in that it includes at least one reliability testing device, and the reliability testing device includes a two-to-one circuit module, three flip-flops, and a voting device; The output terminals of the two alternative circuit modules are respectively connected to the data input terminals of the three flip-flops; The output terminals of the three flip-flops are respectively connected to the three input terminals of the voter; The clock terminals of the three flip-flops are not connected, and they are respectively driven by the clock trees of the three semiconductor integrated circuits. 2. The integrated circuit device according to claim 1, wherein the clock tree is a clock tree CK0, CK1, CK2 of a semiconductor integrated circuit. 3. The integrated circuit device of claim 1, wherein said voter is a three-input voting circuit device. 4. The integrated circuit device according to any one of claims 1 to 3, wherein the three clock trees input a clock from a pin of the semiconductor integrated circuit device, and then at the starting point of the clock tree Fork and control. 5. The integrated circuit device according to any one of claims 1 to 3, characterized in that, the three clock trees are input by a plurality of pins of the semiconductor integrated circuit device, and independently control the on, off and off of each clock. Connections to other clocks. 6. The integrated circuit device according to any one of claims 1 to 3, further comprising at least one scan chain, the scan chain connects the data output of each level of reliability testing device with the next level of reliability The scan data inputs of the test fixtures are linked together. 7. The integrated circuit device according to claim 6, wherein the semiconductor integrated circuit device is a semiconductor digital integrated circuit. 8. A reliability testing device for a semiconductor integrated circuit device, characterized in that it includes a two-choice circuit module, three flip-flops, and a voting device; The output terminals of the two alternative circuit modules are respectively connected to the data input terminals of the three flip-flops; The output terminals of the three flip-flops are respectively connected to the three input terminals of the voter; The clock terminals of the three flip-flops are not connected, and they are respectively driven by the clock trees of the three semiconductor integrated circuits. 9. The reliability test device for a semiconductor integrated circuit device according to claim 8, wherein said voting device is a three-input voting circuit device. 10. The reliability testing device for a semiconductor integrated circuit device according to claim 8 or 9, characterized in that, one pin of the semiconductor integrated circuit device inputs a clock into the three clock trees, and then The starting point for bifurcation and control. 11. The reliability testing device for a semiconductor integrated circuit device according to claim 8 or 9, characterized in that the three clock trees are input by multiple pins of the semiconductor integrated circuit device, and each clock is individually controlled to be turned on , shutdown and connections to other clocks. 12. A reliability testing method for a semiconductor integrated circuit device, comprising the following steps: Step A, controlling the on and off states of the three clock trees of the semiconductor integrated circuit, and assigning an initial value to the flip-flop of the reliability device in the scanning state through the scan chain of the semiconductor integrated circuit; Step B, turn off some clocks, turn on and connect the rest of the clocks, and perform a scan test. 13. The reliability testing method according to claim 12, further comprising the following steps: Step C, repeating the operations from step A to step B until the test combination is completed, and the faults in the semiconductor integrated circuit are tested. 14. The reliability testing method according to claim 12 or 13, characterized in that, in said step A, said assigning an initial value to the trigger comprises the following steps: In the scanning state, all the three clock trees of the semiconductor integrated circuit are turned on and connected, and the constant value "0" is set at the input end of the scan chain and scanned for a long enough time to assign the initial value "0" to all flip-flops. 15. The reliability testing method according to claim 14, characterized in that, in the step B, performing a scan test comprises the following steps: Turn off the clock CK0, turn on and connect the clocks CK1 and CK2, and perform a scan test. 16. The reliability testing method according to claim 12 or 13, characterized in that, in said step A, said assigning an initial value to the trigger comprises the following steps: In the scanning state, first assign the initial value "0" to all flip-flops, then turn off CK0, set a constant value "1" at the input of the scan chain and scan for a long enough time, the final result is the initial value of the flip-flop corresponding to CK0 is "0", and the initial value of other flip-flops is "1". 17. The reliability testing method according to claim 16, characterized in that, in the step B, performing a scan test comprises the following steps: Turn off the clocks CK0 and CK1, turn on the clock CK2, and perform a scan test. 18. The reliability testing method according to claim 13, characterized in that, in the step C, testing out the fault in the semiconductor integrated circuit comprises the following steps: If the test results of all test combinations are consistent, it is sufficient to indicate that there is no fault in the chip; If the test results under any one or several combinations are inconsistent, it means that there is a fault.

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