CN1235411C - Flow-line-based frame predictive mode coding acceleration method - Google Patents

Abstract

The invention relates to the technical field of network media communication, in particular to a pipeline-based intra-frame prediction mode block coding acceleration method. The steps are as follows: divide the video frame into macroblocks (such as 16*16), then divide the macroblock into subblocks (such as 4*4), and predictively encode each subblock in intra-frame prediction mode. It can greatly accelerate the speed of intra-frame coding without increasing resource consumption, thereby increasing the speed of video coding. The characteristics of the present invention are: based on the assembly line structure, without increasing resource consumption; suitable for any block-based intra-frame predictive encoding, with strong applicability; adjusting sub-block encoding order according to the assembly line requirements; and improving encoding speed. The invention is suitable for video coding design.

Description

Pipeline-Based Acceleration Method for Intra Prediction Mode Block Coding

technical field

The invention relates to the technical field of network media communication, in particular to a pipeline-based intra-frame prediction mode block coding acceleration method.

technical background

With the rapid development and wide application of multimedia technology and network technology, the dissemination of various video data through the network has become more and more widely used. Because the original video data requires a huge bandwidth and has great redundancy, it is usually compressed and then transmitted through encoding. In some real-time or near-real-time environments (such as video conferencing, etc.), the encoder is required to achieve a sufficiently high encoding speed. The huge amount of video encoding calculations requires the use of accelerated algorithms for the encoding process.

Video coding began in the late 1980s. From MPEG-1, H.261 to the current MPEG-4, H.264, there has been a long research history, and many international standards have been proposed, but the basic idea is still block compression and motion predict. Based on the intra-frame macroblock prediction method in the previous standard, H.264 proposes a new intra-frame prediction mode - 4*4 intra-frame prediction, which divides a 16*16 macroblock into 16 For 4*4 sub-blocks, intra-frame prediction is performed on each sub-block, and each has an independent prediction mode. This mode improves the coding efficiency, but also brings about the increase of computational complexity and the slowdown of coding speed, and the speed of intra-frame coding can be greatly accelerated by adopting the pipeline-based acceleration method proposed by the present invention.

Contents of the invention

The purpose of the present invention is to provide a pipeline-based method for accelerating block coding in intra-frame prediction mode. The present invention includes the following features:

Invented technical solution

A pipeline-based intra-frame prediction mode block coding acceleration method, which divides the intra-frame coding process into four sub-processes: prediction, DCT transformation and quantization, inverse quantization, inverse DCT transformation and reconstruction. Data dependency, adjust the sub-block intra-coding order from left to right and from top to bottom, so that there is no data correlation between sub-blocks and subsequent sub-blocks in the coding order, so that sub-block intra-coded sub-blocks The pipeline operation is formed between the processes, and the sub-process of the subsequent sub-block does not need to wait for the completion of all the sub-processes of the previous sub-block. Without increasing resource consumption, the DCT transformation and quantization sub-process of the previous sub-block can be compared with The prediction sub-process of subsequent sub-blocks is carried out simultaneously, the sub-process of inverse quantization and inverse DCT transformation can be carried out simultaneously with the sub-process of DCT transformation and quantization of subsequent sub-blocks, and the sub-process of reconstruction can be carried out together with the sub-process of inverse quantization and inverse DCT transformation of subsequent sub-blocks Simultaneously, and so on.

Description of drawings

Fig. 1 is a sequence diagram of encoding 4*4 blocks in an MPEG-4AVC/H.264 frame.

FIG. 2 is a diagram of MPEG-4AVC/H.264 prediction reference points.

Fig. 3 is a schematic diagram of an intra-frame encoding pipeline.

Figure 4 is a sequential execution sequence diagram.

Figure 5 is an ideal pipeline execution sequence diagram.

Fig. 6 is a sequence diagram of pipeline execution under actual conditions.

Specific Embodiments of the Invention

In Figure 1, take MPEG-4AVC/H.264 intra-frame prediction as an example:

MPEG-4AVC/H.264 divides the video frame into 16*16 macroblocks, and then divides the macroblock into 4*4 subblocks, and predicts and codes each subblock separately in the intra prediction mode. Figure 1 shows the coding sequence,

Figure 2 is the reference point required for prediction.

As shown in Figure 3, the intra-frame 4x4 block encoding process can be divided into four sub-processes: prediction, DCT transformation and quantization, inverse quantization, inverse DCT transformation and reconstruction. The time required for the four sub-processes is respectively T ₁ , T ₂ , T ₃ , T ₄ , then the total time required to execute the intra-frame coding sequence of 16 sub-blocks of a macroblock

T _seq ＝16*(T ₁ +T ₂ +T ₃ +T ₄ )

The execution sequence is shown in Figure 4.

It can be noticed that only one of the four sub-processes of prediction, DCT transformation and quantization, inverse quantization and inverse DCT transformation and reconstruction is executed at any time, resulting in waste of resources and prolongation of calculation time, so pipeline technology can be used to make full use of calculation resources and reduce computing time. As shown in Figure 5, under ideal conditions, the execution time of the 16 sub-block intra-frame coding pipelines of a macroblock

T _{pipeline_ideal} ＝T ₁ +max(T ₁ +T ₂ )+max((T ₁ +T ₂ +T ₃ )

+max(T ₁ +T ₂ +T ₃ +T ₄ )*13

+max(T ₂ +T ₃ +T ₄ )+max(T ₃ +T ₄ )+T ₄

However, due to the data correlation between sub-blocks, the ideal state cannot be achieved. For example, the prediction of sub-block 1 needs the reconstruction data of block 0, and the prediction of sub-block 2 needs the reconstruction data of sub-block 0 and sub-block 0. According to the data correlation, the sub-block encoding order is adjusted to fully utilize the pipeline efficiency, and the encoding order is adjusted as follows:

0, 1, 4, 2, 5, 3, 6, 8, 7, 9, 12, 10, 13, 11, 14, 15 are shown in Figure 6.

Total time required to perform intra coding of 16 subblocks of a macroblock

T _{pipeline_real} = (T ₁ +T ₂ +T ₃ +T ₄ )*4+{T ₁ +T ₄ +[max(T ₁ , T ₂ )+max(T ₂ ,

T ₃ )+max(T ₃ , T ₄ )+max(T ₄ , T ₁ )]*2}*3

Speedup ratio λ=T _seq /T _{pipeline_real}

In the FPGA reference hardware implementation, T ₁ =20cycle, T ₂ =T ₃ =16cycle, T ₄ =18cycle, it can be obtained that the acceleration ratio is 1.3365, and the performance is improved by 33.65% without increasing the consumption of hardware resources.

Claims (1)

1. intra prediction mode block encoding accelerated method based on streamline, the intraframe coding process is divided into prediction, dct transform and quantification, inverse quantization and anti-dct transform and four subprocess of reconstruction, data dependence according to the intraframe coding of macro block neutron piece, will be from left to right, sub-piece intraframe coding is from top to bottom adjusted in proper order, make and do not have data dependence between coded sequence neutron piece and subsequent sub-block, thereby make between the subprocess of sub-piece intraframe coding and form pile line operation, do not need to wait for that whole subprocess of last sub-piece finish just can carry out the subprocess of subsequent sub-block, under the situation that does not increase resource consumption, the dct transform of last sub-piece and quantification subprocess can carry out simultaneously with the predictor process of subsequent sub-block, inverse quantization and anti-dct transform subprocess can carry out simultaneously with the dct transform and the quantification subprocess of subsequent sub-block, rebuilding subprocess can carry out simultaneously with the inverse quantization and the anti-dct transform subprocess of subsequent sub-block, and the like.

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