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CN1229857C - Solder bump and wire bonding with infrared heating - Google Patents

Solder bump and wire bonding with infrared heating Download PDF

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Publication number
CN1229857C
CN1229857C CNB008196419A CN00819641A CN1229857C CN 1229857 C CN1229857 C CN 1229857C CN B008196419 A CNB008196419 A CN B008196419A CN 00819641 A CN00819641 A CN 00819641A CN 1229857 C CN1229857 C CN 1229857C
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CN
China
Prior art keywords
substrate
chip
bonding
infrared
die
Prior art date
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Expired - Fee Related
Application number
CNB008196419A
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Chinese (zh)
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CN1454393A (en
Inventor
P·C·翁
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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Publication of CN1229857C publication Critical patent/CN1229857C/en
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    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy

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Abstract

本发明提供一种可靠地加热堆栈式裸晶组件或倒装芯片组件的基板及/或裸晶的接合区，以确保高品质焊料或引线接合在基板与裸晶之间的方法与装置。实施方案包含在引线接合前及引线接合过程期间利用红外线灯或红外线枪照射裸晶的上表面，以加热堆栈式裸晶封装的裸晶的引线接合区，或利用红外线灯或红外线枪的照射来加热倒装芯片所安装的基板的上表面的接合片，以使其到达到所需温度，接着将倒装片接合至基板上，使用红外线照射直接加热该裸晶及/或基板的上表面，确保在必须时间周期内焊接区个别加热到适当温度，因此，使线路焊接或裸晶焊接的高品质成为可能，同时增加了产率。

Figure 00819641

The present invention provides a method and device for reliably heating the substrate and/or die bonding area of a stacked die assembly or flip-chip assembly to ensure high-quality solder or wire bonding between the substrate and the die. Embodiments include irradiating the top surface of the die with an infrared lamp or an infrared gun to heat the wire bond area of the die in a stacked die package before and during the wire bonding process, or using irradiation from an infrared lamp or an infrared gun to Heating the bonding pad on the upper surface of the substrate on which the flip chip is mounted so that it reaches the required temperature, then bonding the flip chip to the substrate, and directly heating the bare crystal and/or the upper surface of the substrate using infrared radiation, Ensures that the bonding pads are individually heated to the proper temperature within the necessary time period, thus enabling high quality wire bonding or bare die bonding while increasing productivity.

Figure 00819641

Description

用红外线加热的焊锡凸块和引线接合Solder bump and wire bonding with infrared heating

技术领域technical field

本发明涉及一种在组装操作中，加热半导体组件及电路板的方法与装置，特别应用于堆栈式芯片组件的引线接合及倒装芯片焊接上。The invention relates to a method and device for heating semiconductor components and circuit boards during assembly operations, especially for wire bonding and flip-chip welding of stacked chip components.

背景技术Background technique

在已知的堆栈式芯片(die)封装技术中，第一芯片通过环氧树脂(epoxy)、聚酰亚胺(polyimide)糊或薄胶带来附着于例如金属引线架或层压塑料或陶瓷电路板的基板上，且第二芯片也通过环氧树脂、聚酰亚胺糊或薄胶带来附着于该第一芯片的上表面。接着是引线接合操作的完成，其中金制或铜制的引线熔接在基板及芯片上表面的接合片(bonding pads)上，典型的作法是利用超声波及加热。为了将基板及芯片加热到适当温度以利引线接合，典型的作法是以约摄氏190度的温度，利用加热器块的传导，从基板的底部开始预热。换言之，虽然引线接合(即引线端点的焊接)发生在基板及芯片的上表面，但它们仍是由底部开始加热的。In known stacked die packaging techniques, the first die is attached to, for example, a metal lead frame or a laminated plastic or ceramic circuit by means of epoxy, polyimide paste or thin adhesive tape. The substrate of the board, and the second chip is also attached to the upper surface of the first chip by epoxy, polyimide paste or thin adhesive tape. This is followed by the completion of the wire bonding operation, in which gold or copper wires are welded to the substrate and bonding pads on the upper surface of the chip, typically using ultrasound and heat. In order to heat the substrate and chip to an appropriate temperature for wire bonding, a typical method is to preheat from the bottom of the substrate by using the conduction of the heater block at a temperature of about 190 degrees Celsius. In other words, although the wire bonding (that is, the bonding of the wire terminals) occurs on the top surface of the substrate and chip, they are still heated from the bottom.

当基板为具有良好热传导率的薄金属引线架时，例如铜引线架，则使用加热器块自底部预热基板可获得令人满意的结果，但是此种习用方法用于其它型式的基板是有问题的。特别是对于厚的层压塑料或陶瓷基板来说，在有效的预热时间周期内(例如，约4秒或少于4秒的时间，这要依引线焊接器的速度及每一芯片组的引线数而定)使用加热器块加热是很慢的，无法升高至适当温度以进行引线接合。而且，因为芯片与基板底部相隔很远，以致其接合区的加温比基板更慢，所以使用加热器块不可能加温到较佳的引线接合温度，必然对引线接合品质及制造产率有不利影响。Using a heater block to preheat the substrate from the bottom gives satisfactory results when the substrate is a thin metal lead frame with good thermal conductivity, such as a copper lead frame, but this conventional method is useful for other types of substrates. questionable. Especially for thick laminated plastic or ceramic substrates, within an effective preheat time period (e.g., about 4 seconds or less, depending on the speed of the wire bonder and the Depending on the number of leads) heating with a heater block is slow and does not bring it up to the proper temperature for wire bonding. Moreover, because the chip is far away from the bottom of the substrate, the heating of the bonding area is slower than that of the substrate, so it is impossible to heat up to a better wire bonding temperature using a heater block, which will inevitably affect the quality of wire bonding and manufacturing yield. Negative Effects.

类似的问题也存在于习用倒装芯片组装法其中半导体芯片系直接焊接在基板的上表面上，该基板以塑料或陶瓷电路板为代表。该基板上的接合片涂布有焊料，且焊料系以「焊锡凸块」(solder bumps)的方式来处理，在组装前附着于芯片上。利用热与压力来熔化基板及芯片上的焊料，以将芯片接合至基板上。典型的倒装芯片组装技术是利用上述的加热器块，对基板预热以部份熔化焊锡凸块。然而在堆栈式芯片组装时，加热器块无法足够快速升高基板上表面及焊锡凸块的温度以确保在芯片与基板间的高品质连接，因此反而影响产率及可靠度。Similar problems also exist in the conventional flip-chip assembly method in which semiconductor chips are directly soldered on the upper surface of a substrate typified by a plastic or ceramic circuit board. The bonding pads on the substrate are coated with solder, and the solder is processed in the form of "solder bumps," which are attached to the chip prior to assembly. Heat and pressure are used to melt the solder on the substrate and chip to bond the chip to the substrate. A typical flip-chip assembly technique utilizes the aforementioned heater blocks to preheat the substrate to partially melt the solder bumps. However, during stacked chip assembly, the heater block cannot raise the temperature of the upper surface of the substrate and the solder bumps fast enough to ensure a high-quality connection between the chip and the substrate, thereby affecting the yield and reliability.

在此，需要一种方法确保倒装芯片、芯片与基板引线接合的适当加热，藉以改善制造产率及降低成本。Here, there is a need for a method to ensure proper heating of flip-chip, chip-to-substrate wire bonding, thereby improving manufacturing yield and reducing cost.

发明内容Contents of the invention

本发明的优点是提供一种方法与装置，以可靠加热基板及/或芯片上的接合区，以确保该基板与芯片间的焊料或引线接合具有高品质。An advantage of the present invention is to provide a method and apparatus for reliably heating a bonding area on a substrate and/or chip to ensure high quality solder or wire bonding between the substrate and chip.

本发明的额外优点及其它特征将在下列叙述中提出，使得本领域普通技术人员能通过审查本发明的下列实施例而明白，或可以从本发明的施行上了解。在所附的权利要求中特别指出的本发明的优点将可以实现与获得。Additional advantages and other features of the present invention will be set forth in the following description, so that those of ordinary skill in the art can understand the following embodiments of the present invention, or can be learned from the practice of the present invention. The advantages of the invention may be realized and attained as particularly pointed out in the appended claims.

依据本发明，为达到前述及其它优点，利用加热半导体芯片上表面接合区以附着于基板的方法，该方法包括以红外线直接照射芯片上表面以加热接合区。According to the present invention, in order to achieve the foregoing and other advantages, a method of heating the bonding area on the upper surface of the semiconductor chip for attachment to the substrate is utilized, the method includes directly irradiating the upper surface of the chip with infrared rays to heat the bonding area.

本发明的另一方面，是用于实现上述方法的装置。Another aspect of the present invention is an apparatus for implementing the above method.

通过以下的详细叙述，本发明的额外优点对于本领域普通技术人员而言，将变成极为显著的，其中通过考虑实现本发明的最佳模式的说明方式，本发明仅显示及描述较佳实施例。将可以了解的是，本发明可有其它及不同的实施例，并且该发明的各目的细节能够修正于各种不同的明显方面，均不脱离本发明的范围内，因此，附图及叙述仅用来说明，而不是对本发明加以限定。Additional advantages of this invention will become readily apparent to those of ordinary skill in the art from the following detailed description, wherein the invention is shown and described only as a preferred embodiment by way of illustration of the best mode for carrying out the invention. example. As will be realized, the invention is capable of other and different embodiments, and its various object details are capable of modification in various obvious respects, all without departing from the scope of the invention, and therefore the drawings and description only It is used to illustrate, not to limit the invention.

附图说明Description of drawings

参照下列附图，其中相同的图式标号代表相同的组件，其中：Referring to the following drawings, in which like drawing numbers represent like components, in which:

图1为依据本发明实施方案的装置的侧视图。Figure 1 is a side view of an apparatus according to an embodiment of the present invention.

图2A、2B为依据本发明实施方案的方法连续过程的示意说明图。Figures 2A, 2B are schematic illustrations of the continuum of the process according to an embodiment of the present invention.

具体实施方式Detailed ways

用以将引线焊接在堆栈式芯片封装与组装倒装芯片封装的习用方法，无法可靠加热基板及/或芯片上的接合区至适当温度，以形成高品质的焊料接点或引线接合，因此降低制造产率。本发明提出并解决源自习用制造工艺中的问题。Conventional methods for bonding wires to stacked die packages and assembling flip chip packages do not reliably heat the bonding pads on the substrate and/or die to the proper temperature to form high quality solder joints or wire bonds, thereby reducing manufacturing Yield. The present invention addresses and solves problems arising from conventional manufacturing processes.

依本发明的实施方案的方法，其中堆栈式芯片封装的各芯片的引线接合区以红外线照射来加热，即在引线接合处理之前及处理期间以习用红外线灯或红外线枪直接照射该芯片的上表面。此外，该基板的接合区也可透过上述红外线照射来加热，而基板的底部可以习用传导加热器块来预热。以本发明的红外线照射来加热芯片与基板上的上表面，可确保在所需时间周期内，如4秒或少于4秒，它们个别的引线焊接区加热至适当引线焊接温度(即，约摄氏190度)；藉此，使高品质的引线焊接成为可能，并增加引线焊接产率。The method according to an embodiment of the present invention, wherein the wire bonding area of each chip of the stacked die package is heated by infrared radiation, that is, the upper surface of the chip is directly irradiated with a conventional infrared lamp or an infrared gun before and during the wire bonding process . In addition, the bonding area of the substrate can also be heated by the above-mentioned infrared radiation, and the bottom of the substrate can be preheated by a conventional conduction heater block. Using the infrared radiation of the present invention to heat the upper surface of the chip and the substrate ensures that their individual wire bonding regions are heated to the proper wire bonding temperature (i.e., about 190 degrees Celsius); thereby, high-quality wire bonding becomes possible and increases the productivity of wire bonding.

依本发明的另一实施方案，倒装芯片所安装的基板上表面的接合片区经上述红外线灯或红外线枪照射，加热至所需温度约摄氏200度，该倒装芯片随后以压力及红外线加热来接合。此外，该基板底部可以习用传导加热器块来预热。所以，本发明确保该基板上的焊料在适当温度，以在接合操作前及接合操作期间进行倒装芯片接合。结果，本发明改善位于该倒装芯片与基板间的焊料接合的品质。According to another embodiment of the present invention, the bonding pad area on the upper surface of the substrate on which the flip-chip is mounted is irradiated by the above-mentioned infrared lamp or infrared gun, and heated to a required temperature of about 200 degrees Celsius. The flip-chip is then heated with pressure and infrared rays. to join. Additionally, the bottom of the substrate can be preheated conventionally using a conduction heater block. Therefore, the present invention ensures that the solder on the substrate is at the proper temperature for flip chip bonding before and during the bonding operation. As a result, the invention improves the quality of the solder joint between the flip chip and the substrate.

本发明的较佳实施例如图1所示。用以引线接合的发明装置100，基于习用引线焊接器，如Willow Grove，PA的Kulicke & SoffaIndustries，Inc.所产的8028型引线焊接器，包括习用传导加热器块110、习用引线接合头120及红外线加热器130。习用堆栈式芯片封装结构利用本发明的方法及装置来进行引线接合，其中包括基板140，如陶瓷或层压塑料电路板；下半导体芯片150及上半导体芯片160，典型是以环氧树脂黏着剂来使该两芯片结合(未图标)。A preferred embodiment of the present invention is shown in FIG. 1 . The inventive apparatus 100 for wire bonding is based on a conventional wire bonder, such as the Model 8028 wire bonder produced by Kulicke & Soffa Industries, Inc. of Willow Grove, PA, and includes a conventional conduction heater block 110, a conventional wire bond head 120 and Infrared heater 130. The conventional stacked chip package structure utilizes the method and apparatus of the present invention for wire bonding, which includes a substrate 140, such as a ceramic or laminated plastic circuit board; a lower semiconductor chip 150 and an upper semiconductor chip 160, typically with an epoxy adhesive To make the two chips combined (not shown).

红外线加热器130设置于即将进行引线接合的封装结构上方，以加热芯片150的上表面150a、芯片160的上表面160a，其中每个芯片包括接合片BP及基板140的「接合区域」；亦即，基板140的上表面140a的部分具有接合片BP。加热器130为习用红外线灯或红外线枪，或是经特别设计的最佳化红外线加热器，用以在引线接合器100上可获得的有限空间内进行操作。例如，挠性光纤管线可用来将红外线导向基板140及芯片150、160。The infrared heater 130 is arranged above the packaging structure to be wire-bonded to heat the upper surface 150a of the chip 150 and the upper surface 160a of the chip 160, wherein each chip includes a bonding pad BP and a "bonding area" of the substrate 140; that is , a portion of the upper surface 140a of the substrate 140 has bonding pads BP. The heater 130 is a conventional IR lamp or IR gun, or a specially designed and optimized IR heater to operate within the limited space available on the wire bonder 100 . For example, flexible fiber optic tubing may be used to direct infrared light to the substrate 140 and chips 150,160.

红外线加热器130的强度及波长可指定使用，强度最好使所需温度曲线能实现；例如，芯片上表面150a、160a及基板140的接合区的温度能达到引线接合温度，约在4秒或少于4秒的时间内上升至摄氏190度，这要依照引线接合器100的速度及所需产量而定。红外线放射的波长以欲加热的材料而定，因为有些红外线波长不被某些材料吸收(即该波长无法加热那些材料)。所以，有必要且必须提供不同波长的红外线照射来加热芯片150、160(主要为硅所制成)及基板140(以塑料或陶瓷制成)。The intensity and the wavelength of the infrared heater 130 can be used by appointment, and the intensity is preferably to enable the desired temperature curve to be realized; for example, the temperature of the bonding area of the chip upper surface 150a, 160a and the substrate 140 can reach the wire bonding temperature, about 4 seconds or so. The ramp to 190 degrees Celsius takes less than 4 seconds, depending on the speed of the wire bonder 100 and the required throughput. The wavelength of infrared radiation depends on the material to be heated, because some infrared wavelengths are not absorbed by certain materials (ie, the wavelength cannot heat those materials). Therefore, it is necessary and necessary to provide infrared radiation of different wavelengths to heat the chips 150 , 160 (mainly made of silicon) and the substrate 140 (made of plastic or ceramics).

传导加热器110可用来与红外线加热器130搭配，使得依堆栈式芯片封装而定的所需引线接合温度及温度曲线更容易实现，例如，若引线接合的堆栈式芯片封装100包括陶瓷或塑料基板140，则最好使用传导加热器110以预热封装，而如同上述的红外线加热器130则用来加热基板140及芯片150、160的接合区。然而，若堆栈式芯片封装100包括金属引线架基板140，则红外线加热器130就可以用来直接加热芯片表面150a、160a，但是不需要加热基板表面140a，因为单以传导加热器110就可以适当加热薄金属基板。The conductive heater 110 can be used in conjunction with the infrared heater 130 to make it easier to achieve the desired wire bonding temperature and temperature profile depending on the stacked die package, for example, if the wire bonded stacked die package 100 includes a ceramic or plastic substrate 140, the conductive heater 110 is preferably used to preheat the package, while the infrared heater 130 as described above is used to heat the substrate 140 and the bonding area of the chips 150,160. However, if the stacked die package 100 includes a metal lead frame substrate 140, the infrared heater 130 can be used to directly heat the chip surfaces 150a, 160a, but the substrate surface 140a need not be heated since the conduction heater 110 alone is adequate. Thin metal substrates are heated.

在操作时，堆栈式芯片封装以传导加热器110预热，例如当其它封装要进行引线接合时，将其移至引线接合头120下方位置。当引线接合头120连结引线170至接合片BP时，红外线加热器130接着对包括接合片BP的基板140及芯片150、160的区域加热至约摄氏190度。因为接合片BP由传导加热器110及/或红外线加热器130适当加热，故引线170可确实焊接到接合片BP上。In operation, the stacked die package is preheated with the conductive heater 110 , eg, moved to a position under the wire bond head 120 when other packages are to be wire bonded. When the wire bond head 120 connects the wire 170 to the bonding pad BP, the infrared heater 130 then heats the area of the substrate 140 including the bonding pad BP and the chips 150 , 160 to about 190 degrees Celsius. Since the bonding pad BP is properly heated by the conduction heater 110 and/or the infrared heater 130, the lead wire 170 can be reliably soldered to the bonding pad BP.

本发明的其它实施例如图2A、2B所示。用于倒装芯片接合的本发明装置200，是基于习用倒装芯片芯片接合器，如瑞士ESEC公司所产的Micron2型，包括习用传导加热器210、习用接合头220及红外线加热器230。已知的倒装芯片基板240接合倒装芯片芯片250则显示于芯片接合器200上，如陶瓷或层压塑料电路板。Other embodiments of the present invention are shown in Figures 2A and 2B. The device 200 of the present invention for flip-chip bonding is based on a conventional flip-chip chip bonder, such as the Micron2 type produced by the Swiss company ESEC, which includes a conventional conductive heater 210 , a conventional bonding head 220 and an infrared heater 230 . A known flip-chip substrate 240 bonded to a flip-chip chip 250 is shown on the die bonder 200 , such as a ceramic or laminated plastic circuit board.

在将芯片250加压至基板240上之前，红外线加热器230设置于包含覆盖有焊料240c的接合片240b的基板240上方，以加热基板240的上表面240a。在上述实施方案中，加热器230为习用红外线灯或红外线枪，或可为特别设计的最佳化红外线加热器，以在芯片接合器200的可获得的有限空间中操作。如先前所述红外线加热器230的强度及波长须指定，如此才可达到所需温度曲线，例如在0.66秒的时间内，基板上表面240a的温度上升到达约摄氏200度的接合温度，依芯片接合器200的速度及所需产量而定，而红外线放射的波长以基板240的材质而定。传导加热器210可用来与红外线加热器230搭配，使得所需芯片接合温度及温度曲线更容易实现。Before pressing the chip 250 onto the substrate 240 , the infrared heater 230 is disposed above the substrate 240 including the bonding pad 240 b covered with solder 240 c to heat the upper surface 240 a of the substrate 240 . In the above embodiments, the heater 230 is a conventional infrared lamp or infrared gun, or may be an optimized infrared heater specially designed to operate in the limited space available in the die bonder 200 . As previously mentioned, the intensity and wavelength of the infrared heater 230 must be specified, so that the required temperature profile can be achieved. For example, within 0.66 seconds, the temperature of the upper surface 240a of the substrate rises to a bonding temperature of about 200 degrees Celsius, depending on the chip. The speed of the bonder 200 depends on the required output, and the wavelength of the infrared radiation depends on the material of the substrate 240 . The conduction heater 210 can be used in conjunction with the infrared heater 230 to make the required die bonding temperature and temperature profile easier to achieve.

现在参照图2A，在操作时，基板240由传导加热器210预热，例如当其它组件进行芯片接合时，接着将该芯片移至运载倒装芯片250的芯片接合头220的下方，该倒装芯片250包括有对应接合片240b的焊锡凸块260。接着操作红外线加热器230以加热包含接合片240b的基板上表面240a至约摄氏200度，以至少部分熔化在接合片240b上的焊料240c。接着，芯片接合头220降下(如图2B所示)并将接合片240b压向焊锡凸块260。该焊锡凸块260接着与覆盖于接合片240b上的焊料240c一起熔化，以将倒装片250接合至基板240上。因为接合片240b在芯片接合前，由传导加热器210及红外线加热器130适当加热，故倒装芯片250与接合片240b间的连接品质很高，结果改善了制造产率及可靠度。Referring now to FIG. 2A , in operation, substrate 240 is preheated by conduction heater 210 , such as when other components are die bonded, and the die is then moved under die bond head 220 carrying a flip chip 250 , which flip chip Chip 250 includes solder bumps 260 corresponding to pads 240b. The infrared heater 230 is then operated to heat the upper surface 240a of the substrate including the bonding pad 240b to about 200 degrees Celsius to at least partially melt the solder 240c on the bonding pad 240b. Next, the die bond head 220 is lowered (as shown in FIG. 2B ) and presses the bonding pad 240 b against the solder bump 260 . The solder bumps 260 are then melted together with the solder 240c covering the bonding pad 240b to bond the flip chip 250 to the substrate 240 . Because the bonding pad 240b is properly heated by the conductive heater 210 and the infrared heater 130 before chip bonding, the connection quality between the flip chip 250 and the bonding pad 240b is high, resulting in improved manufacturing yield and reliability.

本发明可应用习用材料、方法及设备来实施。因此，这些材料、设备及方法的细节并未在此详细提出。为了使能完全了解本发明，在前述说明中，提出了许多特定的细节，如特定的材料、结构、化学制品及过程等。然而，本发明并不仅限于以上述特定细节来实施。在其它实例方面，为了不使不必要地遮掩了本发明的特征，故众所周知的工艺架构并未详细叙述。The present invention can be practiced using conventional materials, methods and equipment. Accordingly, the details of such materials, equipment, and methods are not presented here in detail. In the foregoing descriptions, numerous specific details are set forth, such as particular materials, structures, chemicals and processes, in order to provide a thorough understanding of the invention. However, the invention is not limited to practice with the specific details described above. In other instances, well known process architectures have not been described in detail in order not to unnecessarily obscure features of the present invention.

在此仅揭露本发明的较佳实施例及一些多用途的范例，如此可了解本发明在其它不同组合及环境下均可实施，且任何可行的变化及修正均在于此陈述的本发明概念的范围之内。Only preferred embodiments of the present invention and some multi-purpose examples are disclosed here, so that it can be understood that the present invention can be implemented in other different combinations and environments, and any possible changes and modifications lie within the concepts of the present invention stated herein within range.

Claims (8)

1. a heating is attached to the method for bonding land of the upper surface of the semiconductor chip on the substrate, and this method comprises the upper surface with this chip of infrared radiation, with at 4 seconds or be less than in time of 4 seconds, heats this bonding land to 190 degree centigrade.
2. the method for claim 1 comprises the bonding land with this upper surface of base plate of infrared radiation.
3. the method for claim 1 comprises when infrared ray shines the upper surface of this chip lead-in wire being attached to this bonding land.
4. one kind is assembled in the method for substrate with flip-chip, comprises the upper surface with this substrate of infrared radiation, to heat the bonding land of this upper surface of base plate; And
Deposit secondary heater, be used to heat the basal surface of this substrate.
5. method as claimed in claim 4, wherein this bonding land comprises scolder, this method comprises:
The flip-chip that will contain scolder is placed in this bonding land; And
This flip-chip pressurization is attached on this substrate with the scolder of fused joint and flip-chip and with flip-chip.
6. the device of the bonding land of the upper surface of a semiconductor chip that is attached to substrate in order to heating, this device comprises infrared heater, in order to heat this bonding land with this chip upper surface of infrared radiation; And
Secondary heater is used to heat the basal surface of this substrate;
Wherein this infrared heater and this secondary heater are used at 4 seconds or are less than in time of 4 seconds, heat this land to 190 degree centigrade.
7. device as claimed in claim 6, wherein this infrared heater also can heat the bonding land of this upper surface of base plate.
8. device as claimed in claim 6, wherein this infrared heater comprises infrared lamp or infrared ray rifle.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102456588A (en) * 2010-11-05 2012-05-16 三星电子株式会社 Wire bonding apparatus and method of using the same
CN103111698A (en) * 2011-11-16 2013-05-22 台湾积体电路制造股份有限公司 Methods for performing reflow in bonding processes

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10147789B4 (en) * 2001-09-27 2004-04-15 Infineon Technologies Ag Device for soldering contacts on semiconductor chips
US7288472B2 (en) * 2004-12-21 2007-10-30 Intel Corporation Method and system for performing die attach using a flame
JP2006261519A (en) * 2005-03-18 2006-09-28 Sharp Corp Semiconductor device and its manufacturing method
US7677432B2 (en) * 2005-05-03 2010-03-16 Texas Instruments Incorporated Spot heat wirebonding
US20080152829A1 (en) * 2006-12-20 2008-06-26 Dean Roy E Coating compositions, coatings formed therefrom and methods of making the same
SG155779A1 (en) * 2008-03-10 2009-10-29 Micron Technology Inc Apparatus and methods of forming wire bonds
CN102054658B (en) * 2009-10-30 2013-03-27 日月光封装测试(上海)有限公司 Heating fixture of packaging lineup process and method thereof
US7871860B1 (en) * 2009-11-17 2011-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor packaging
US8533936B1 (en) 2011-01-26 2013-09-17 Western Digital (Fremont), Llc Systems and methods for pre-heating adjacent bond pads for soldering
CN102915933A (en) * 2012-09-11 2013-02-06 厦门锐迅达电子有限公司 Surface mounting welding process for wafer-level chip
WO2019168902A1 (en) * 2018-02-28 2019-09-06 Raytheon Company A system and method for reworking a flip chip mounted on an electronic device using a mill to remove the chip and replacing the chip with a new chip in the milled area
CN109003969A (en) * 2018-08-21 2018-12-14 佛山市国星光电股份有限公司 A kind of COB packaging method shown based on high density, system and COB device
US11410961B2 (en) 2020-03-17 2022-08-09 Micron Technology, Inc. Methods and apparatus for temperature modification in bonding stacked microelectronic components and related substrates and assemblies
US11804467B2 (en) * 2020-06-25 2023-10-31 Micron Technology, Inc. Radiative heat collective bonder and gangbonder

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4170326A (en) * 1978-01-09 1979-10-09 Gte Automatic Electric Laboratories Incorporated Method and holding fixture for soldering lead frames to hybrid substrates
JPS5565443A (en) * 1978-11-10 1980-05-16 Mitsubishi Electric Corp Manufacture of semiconductor device
US4915565A (en) * 1984-03-22 1990-04-10 Sgs-Thomson Microelectronics, Inc. Manipulation and handling of integrated circuit dice
JPS61168233A (en) 1985-01-21 1986-07-29 Hitachi Ltd Repairing method of semiconductor device
JPS62188233A (en) * 1986-02-13 1987-08-17 Matsushima Kogyo Co Ltd Semiconductor bonding unit
JPH0238046B2 (en) * 1986-12-27 1990-08-28 Sakamoto Tetsukosho Jugen KANJOZAINOSENKOSOCHI
JPS63232438A (en) * 1987-03-20 1988-09-28 Matsushita Electric Ind Co Ltd Wire bonding method
JPH0296394A (en) * 1988-09-30 1990-04-09 Matsushita Electric Ind Co Ltd Soldering reflow method
JPH02310939A (en) 1989-05-25 1990-12-26 Toshiba Corp Wire bonding
GB2244374B (en) 1990-05-22 1994-10-05 Stc Plc Improvements in hybrid circuits
JPH04151844A (en) 1990-09-05 1992-05-25 Nec Corp Outer lead bonding equipment
JPH05109811A (en) * 1991-10-15 1993-04-30 Mitsubishi Electric Corp Wire bonder
JPH05243722A (en) * 1992-02-28 1993-09-21 Nec Corp Mounting method of semiconductor device
JP2813507B2 (en) 1992-04-23 1998-10-22 三菱電機株式会社 Bonding method and bonding apparatus
JP3195970B2 (en) 1992-05-29 2001-08-06 澁谷工業株式会社 Chip heating mechanism in semiconductor chip bonder
US5346857A (en) 1992-09-28 1994-09-13 Motorola, Inc. Method for forming a flip-chip bond from a gold-tin eutectic
JP3583462B2 (en) * 1993-04-05 2004-11-04 フォード モーター カンパニー Micro soldering apparatus and method for electronic components
US6041994A (en) * 1994-06-07 2000-03-28 Texas Instruments Incorporated Rapid and selective heating method in integrated circuit package assembly by means of tungsten halogen light source
US5783025A (en) * 1994-06-07 1998-07-21 Texas Instruments Incorporated Optical diebonding for semiconductor devices
JPH1050766A (en) * 1996-08-02 1998-02-20 Toshiba Corp Method and apparatus for face down bonding
JPH10189643A (en) * 1996-12-18 1998-07-21 Texas Instr Inc <Ti> High-speed and selective heating of integrated circuit package assembly using tungsten halogen light source
JPH118270A (en) * 1997-06-16 1999-01-12 Tokai Rika Co Ltd Method for mounting semiconductor chip, method for manufacturing chip-on-chip structure, and method for manufacturing chip-on-board structure
JP3344289B2 (en) * 1997-07-18 2002-11-11 松下電器産業株式会社 Mounting method of work with bump

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102456588A (en) * 2010-11-05 2012-05-16 三星电子株式会社 Wire bonding apparatus and method of using the same
CN102456588B (en) * 2010-11-05 2016-06-22 三星电子株式会社 Wire bonding tools and the method using this equipment
CN103111698A (en) * 2011-11-16 2013-05-22 台湾积体电路制造股份有限公司 Methods for performing reflow in bonding processes
CN103111698B (en) * 2011-11-16 2016-08-03 台湾积体电路制造股份有限公司 For the method forming semiconductor package part

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WO2001097278A1 (en) 2001-12-20
TW529111B (en) 2003-04-21
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US6384366B1 (en) 2002-05-07
CN1454393A (en) 2003-11-05

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