CN1215541C - Chip type package and manufacturing method thereof - Google Patents

Abstract

Grinding the back of a wafer by a grinding device; a glass attached to the back of the wafer, suitable materials including but not limited to epoxy, the glass can be attached by conventional attachment techniques, and then the wafer is etched to separate the ICs using a photoresist with a specific pattern as an etch mask; an insulating material is coated on the second surface of the wafer; a grinding process may optionally be used to grind the epoxy on the surface of the wafer on the side having the circuitry; a plurality of openings are formed in the adhesive and correspond to pads on the die, and then the circuitry is redistributed on the surface of the epoxy with portions of the circuitry contacting the pads to establish electrical connection; a solder paste shield as an insulation, the solder paste shield exposing a specific area of the circuit, the exposed area of the circuit being an area where the conductor balls are intended to be placed; a printing process for applying solder paste on the specific region; then the solder paste is changed into a solder ball by a thermal welding process.

Description

Chip type package and manufacturing method thereof

technical field

The present invention relates to a semiconductor process method, in particular to a chip type package and a manufacturing method thereof.

Background technique

With the rapid evolution of semiconductor technology, driven by the trend of thin, light, small and multi-functional electronic products, the number of I/Os of IC semiconductors is not only increasing but also increasing in density, making the number of pins of package components As more and more components are used, the speed requirements are also getting faster and faster, resulting in higher and higher power consumption of components. Therefore, it is becoming more and more important to improve the heat dissipation effect of the package. Semiconductor chips are usually individually packaged in plastic or ceramic packages. The structure of the package must be able to protect the chip and dissipate the heat generated during the operation of the chip. The traditional package is also used for chip function testing. At present, the packaging is getting smaller and smaller to meet the current trend, and the packaging of high-quantity I/O has also made breakthroughs with the development of ball grid array packaging technology (ball grid array; hereinafter referred to as BGA packaging). Therefore, IC Semiconductor carrier packaging tends to utilize ball grid array packaging technology (BGA). The characteristic of BGA packaging is that the pins responsible for I/O are ball-shaped and the distance is shorter than the slender pins of lead frame packaging components, and it is not easy to be damaged and deformed. The electrical transmission distance of the packaging components is short and fast, which can meet the current requirements. and the speed requirements of future digital systems.

At present, there are many different types of semiconductor packages. Regardless of the type of package, most of the packages are cut into individual components before being packaged. However, chip-type packaging is a trend of semiconductor packaging, and one technique will be described below. Referring to FIG. 1 , a plurality of dies 4 are formed on the surface of a semiconductor wafer 2 , and a glass 8 is attached to the surface of the wafer 2 with an adhesive 6 . Then, the side without the core will be ground to reduce its thickness, commonly known as backgrinding, as shown in Figure 2. Next, the wafer is etched to separate the ICs and part of the adhesive 6 will be exposed, see FIG. 3 . Referring to FIG. 4 , another glass 12 is attached to the side opposite to the crystal core by using an adhesive 10 . The next step is shown in Fig. 5, a film layer (compliant layer) 14 is formed on the first glass 8, and then the first glass 8 and the part etched into the adhesive 8, 10 are etched, as shown in Fig. 6, commonly referred to as It is a notch process, so a groove 16 is formed in the glass 8 and the adhesive 6, 10, and solder balls will be formed on the film layer 14 in the subsequent process.

A film layer 18 made of lead will be patterned on the surface of the first glass 8 and along the surface of the groove 16 to provide electrical connection. The film layer 18 also covers the film layer 14, as shown in FIG. 7 Show. Referring to FIG. 8, a solder paste shield 20 is then formed on the surface of the lead film layer 18 and the glass 8 to expose the surface corresponding to the film layer 14. Referring to FIGS. Planted on the surface of the lead film layer 18 exposed by the solder paste mask 20, the next step is to perform a dicing process to etch the adhesive 10 through the glass 12 through the trench 14 to separate the die, as is known in the art. Technology, before this step is implemented, a dicing tape is first attached to the second glass.

However, the above-mentioned process is too complicated, and it needs a notching process and a step of cutting the second glass to separate the die cores. In addition, it includes forming a steep trench slope, and the lead formed thereon will not easily adhere to cause an open circuit, so The quality performance of the components will thus be reduced.

Contents of the invention

The object of the present invention is to provide a package with real chip size.

Another object of the present invention is to provide a low manufacturing cost and disclose a chip type package and its process.

Another object of the present invention is to provide a chip type package suitable for chip type testing, so as to facilitate chip type chipping test and other tests.

The backside of a wafer is firstly ground by a grinding device. Before this step, the wafer tape is attached to the front side of the wafer and removed after grinding. A glass is attached to the backside of the wafer. Suitable materials include, but are not limited to, epoxy. The glass can be attached using known attachment techniques. Then, a patterned photoresist is used as an etch mask , etch the above-mentioned wafer to separate the IC. Optimally, the photoresist opening corresponds to the scribeline on the wafer to expose the scribeline. An adhesive has a thickness of 1-2mil and is coated on the second side of the wafer, preferably using a vacuum coating process. The adhesive can be epoxy (epoxy). This step is similar to the principle of the existing adhesive tape. Its modification is applied as a protective layer on the surface of the wafer. This vacuum coating process can prevent bubbles from forming in it, and epoxy resin (epoxy) will fill in the groove. A curing step may utilize ultraviolet radiation or heat treatment to harden the above-mentioned epoxy resin (epoxy). A lapping process may optionally be used to lap the epoxy on the surface of the wafer on the side with the circuitry. A plurality of openings are formed in the adhesive and correspond to the pads on the die. Then, the circuit is redistributed on the surface of the epoxy, and part of the circuit contacts the pads to establish electrical contact. sexual connection. A solder paste mask acts as an insulation. The solder paste mask exposes specific areas of the circuit where the circuit is exposed where the conductor balls are intended to be placed. A printing process is used to apply solder paste on the above-mentioned specific areas. The solder paste is then turned into solder balls using a thermal soldering process.

The chip type package of the present invention comprises: a chip having a plurality of dies formed thereon, wherein the chip has grooves formed on the dicing lines, a material is attached to the back side of the chip using a first adhesive material, The second adhesive material is located on the plurality of dies and fills the grooves, the plurality of dies have a plurality of bonding pads formed thereon, a circuit layout is formed on the second adhesive material, and connects the plurality of dies. Solder pads, a solder ball shield covering the circuit layout and the second adhesive material, and the exposed portion of the circuit layout and solder balls are formed on the exposed portion and connected to the circuit layout.

Description of drawings

1 to 10 are cross-sectional views of conventional technologies;

Figure 11 shows the sectional view of the semiconductor wafer of the present invention attaching a glass to the back of the wafer and etching the wafer;

Figure 12 shows the cross-sectional view of the semiconductor wafer of the step of vacuum coating epoxy resin (epoxy) on the wafer according to the present invention;

Fig. 13 is shown as the cross-sectional view of the semiconductor wafer in the step of radiation opening pad opening (pad open) according to the present invention;

Figure 14 is a cross-sectional view of a semiconductor wafer showing a step of thermally soldering paste;

FIG. 15 shows a cross-sectional view of a semiconductor wafer in the steps of attaching a glass to the back of the wafer and etching the wafer according to the present invention.

Description of figure number:

1 glass 3 epoxy resin (epoxy)

5 wafers 7 dicing lanes

9 grooves 11 epoxy resin (epoxy)

13 Pads 15 Holes

17 circuit 19 solder paste shielding

21 solder balls

2 wafers 4 crystal cores

6 epoxy resin (epoxy) 8 glass

10 epoxy resin (epoxy) 12 glass

14 film layers 16 grooves

18 lead film layer 20 solder paste shield

22 solder balls

Detailed ways

The present invention discloses a chip-type package and a method for manufacturing a chip-type package. The detailed description is as follows. The preferred embodiment described is only an illustration and is not intended to limit the present invention. Referring to FIG. 1, a backside of a chip (or the first One side) is firstly ground by a grinding device. Before this step, the wafer tape is attached to the front side of the wafer 5, and a material such as glass is attached and then removed. In a preferred embodiment, the thickness of the wafer 5 after grinding is about 6-8 mil. Next, a material 3 such as glass is attached to the back of the wafer with a plurality of crystal cores formed thereon. Suitable materials include, but are not limited to, epoxy resin (epoxy). The glass 1 can be attached using known techniques. For attachment, the thickness of the glass 1 is preferably about 1-2 mil, and the actual thickness is related to other parameters of the process. Quartz or ceramic can replace glass1. The material selected in the attaching process has a thermal expansion coefficient close to that of the wafer. Usually, the thermal expansion coefficient of silicon is 3 cm/cm/°C, and the thermal expansion coefficient of glass is 3-5 cm/cm/°C.

Then, using a patterned photoresist (not shown) as an etching mask, the wafer is etched to separate the ICs. Optimally, the photoresist opening corresponds to the scribeline on the wafer, so as to expose the scribeline 7 . The wafer is then etched by wet etching so that the grooves formed by this step have slopes, which can be obtained by controlling the etching recipe using conventional etching techniques.

Referring to Fig. 11 to Fig. 13, an insulating material 11 has the thickness of 1-2mil and is coated on the second face of wafer 5, preferably utilizes vacuum coating process, and insulating material 11 can be epoxy resin (epoxy) or use BCB This material can prevent air bubbles and improve performance. This vacuum coating process can prevent bubbles from forming therein, and epoxy will be filled in the trench 9 . A curing step may utilize ultraviolet radiation or heat treatment to harden the above-mentioned epoxy resin (epoxy). A lapping process may optionally be used to lap the insulating material 11 on the wafer surface on the circuit side.

A plurality of openings 15 are formed in the insulating material 11 and correspond to the metal pads (pad) 13 on the core. Of course, these metal pads 13 will be exposed. It must be noted that epoxy resin (epoxy) The material is transparent to radiation, so the alignment marks on the scribe lines will not be covered by epoxy. In other words, the alignment marks are visible to subsequent alignment devices. Furthermore, the insulating material 11 must be flowable and resistant to moisture. A conductive layer ( 13 a ) is then formed on the metal pad 13 by electroplating as a protection layer for the metal pad 13 . (pad protection layer), in terms of a preferred embodiment, zinc (Zn)/nickel (Ni) or chromium (Cr) can be selected as the material of the above-mentioned protective layer.

Then, the conductive channel pattern or commonly called pad circuit is redistributed on the surface of epoxy 11 as shown in FIG. 14 . The circuit 17 can be made of conductive material such as metal or alloy, preferably Cr-Cu alloy. Part of the circuit 17 contacts the pad 13 to establish an electrical connection. For example, a copper seed layer is first formed on the surface of the above-mentioned structure and formed along the surface of the opening. In this step, the copper seed layer can be formed on the film layer by means of electroless Cu plating. on the surface. Next, a photoresist pattern is coated on the copper seed layer to define the pattern distribution of the wires. Finally, use the photoresist pattern as a barrier to grow metal wires. For example, electroplating can be used to form copper material on the copper seed layer not covered by the photoresist pattern to complete the distribution of wires. After completion, the photoresist pattern is removed. The above steps may be referred to as conductive channel layout or generally known as circuit redistribution.

Still referring to FIG. 14 , a solder paste shield 19 covers the circuit 17 as an insulation and the solder paste shield 19 exposes specific areas of the circuit 17 , which are intended to place conductor balls. A printing process is used to coat the solder paste 21 on the above-mentioned specific areas. Then use the heat soldering process to turn the solder paste into solder balls. The temperature of this heat soldering can use the known process temperature, see Figure 15. The semiconductor die 5 will be coupled to the above-mentioned solder balls 21. The solder balls can be made by using known BGA technology. Preferably, the solder balls are arranged in an array, and the solder balls are connected to the above-mentioned circuits to establish an electrical connection.

Then, the wafer is sent to a wafer type testing device for wafer type testing, such as a burn-in test. After the wafer type testing is completed, the wafer is then diced to separate individual dies. The dicing process mainly cuts along the dicing line to obtain a chip scale package (CSP). The following table compares wafer level CSP and chip level CSP.

Table I

Chip Type CSP Chip Type CSP Whole wafer packaging (Whole wafer packaging) from the largest size to the junction of the core (Max size extends to die street) each pin is about 0.1 to 0.5 cents per pin (Economy of scale0.1 to 0.5cent/lead) Individual chip packaging (Individual chip packaging) maximum size: die size + twenty percent (Max size: die size + 20percentage) each pin is about 1 to 5 cents per pin (Costly1 to 5cent/lead)

Table 2 shows the comparison between the chip type package of the present invention and other technologies.

Table II Chip Type CSP Tessera (micro-BGA) Rigid laminate Cost (USD cents/pin) Chip type; multi-group process is less than 0.5 cents/pin Individual chip packages; greater than 1 cent per pin Individual chip packages; greater than 1 cent per pin product design The initial investment is less than 10k US dollars; flexible transformation; transformation cycle: within one day The initial investment is more than 50k US dollars; the conversion cost is expensive; the conversion period: several months The initial investment is more than 30k US dollars; the conversion cost is expensive; the conversion period: several months entry cost Moderate: Wafer fab equipment can be utilized medium Low

Reliability "Real" package with resistance to humidity, temperature and baking, cye. Silicon exposed on one side Glob top on flex composition BGA BGA BGA elasticity Only change mask New design and production are necessary Large new design and production are necessary size Die size larger than die size More than twenty percent of die size Die Shrink Available, layout to border (30u) Limited by space, its layout is 300u from the boundary Due to limited space, miniaturization is sacrificed for wire bonding craft Wafer factory process + others TAB/lead bond Wire bond/Flip chip application Memory, logic, ASIC, IPC, smartmedia, analog, RF Memory, logic Memory, Logic Number of pins less than 200pins less than 200pins no limit Center pads special super not easy passable

The present invention is described as above with preferred embodiments, and those who are familiar with the art in this field can make some changes and modifications without departing from the spirit of the present invention. Depends on the equivalent field.

Claims (22)

1. A method for manufacturing a chip type package, the process comprising: providing a wafer having a plurality of dies formed thereon; grinding the backside of the wafer; attaching a material to the backside of the wafer using an adhesive; etching dicing lines on the wafer to separate the plurality of dies; coating an insulating material on the etched wafer; performing a metal pad opening step to expose the multi-metal pad on the polycrystalline core; Forming a metal pad protective layer on the metal pad, the material of the above protective layer can be selected from zinc and nickel or chromium; performing a circuit redistribution step to place a circuit on the insulating material; forming a solder paste mask on the second adhesive to expose a predetermined area on the circuit; performing a solder paste printing step to form solder paste on the predetermined area; and Heat solder the solder paste. 2 . The method for manufacturing a chip type package according to claim 1 , wherein the attached material includes glass. 3 . 3. The manufacturing method of a chip type package according to claim 1, wherein the attached material includes ceramics. 4. The manufacturing method of a wafer type package according to claim 1, wherein the attached material includes quartz. 5. The manufacturing method of a chip type package according to claim 1, wherein the adhesive material comprises epoxy resin. 6. The manufacturing method of chip type package according to claim 1, wherein the insulating material comprises epoxy resin or phencyclobutene. 7 . The manufacturing method of chip type package according to claim 1 , further comprising pasting an adhesive tape on the chip before grinding the backside of the chip. 8 . 8 . The manufacturing method of chip type package according to claim 7 , further comprising removing the adhesive tape after attaching the material on the backside of the chip. 9 . 9. The manufacturing method of a chip type package according to claim 1, further comprising: curing the insulating material after coating the insulating material. 10 . The method for manufacturing a chip-type package according to claim 9 , wherein the curing is by ultraviolet irradiation. 11 . 11. The manufacturing method of chip type package according to claim 1, further comprising grinding the insulating material before performing the step of opening the pad. 12 . The method for manufacturing a wafer type package according to claim 1 , wherein the pad openings are formed by radiation. 13 . 13 . The method for manufacturing a chip-type package according to claim 1 , further comprising testing the chip after performing the thermal welding step. 14 . 14. The manufacturing method of the wafer type package according to claim 13, further comprising: cutting the wafer along the dicing line after performing the test. 15. A chip type package, comprising: a wafer having a plurality of dies formed thereon, wherein the wafer has grooves formed on the scribe lines; A material is attached to the backside of the wafer using an adhesive material; an insulating material is located on the plurality of dies and fills the trenches, the plurality of die cores have a plurality of bonding pads formed thereon; A circuit layout is formed on the insulating material and connected to the plurality of pads; a solder ball shield covering the circuit layout and the insulating material, and exposed portions of the circuit layout; and Solder balls are formed on the exposed portion and connect to the circuit layout. 16. The chip type package according to claim 15, wherein the attached material comprises glass. 17. The chip type package according to claim 15, wherein the attached material comprises ceramics. 18. The chip type package as claimed in claim 15, wherein the attached material comprises quartz. 19. The chip type package as claimed in claim 15, wherein the adhesive comprises epoxy resin. 20. The chip type package according to claim 15, wherein the insulating material comprises epoxy resin or phencyclobutene. 21. The chip type package as claimed in claim 15, wherein a protection layer comprising a metal pad is located on the metal pad. 22. The chip type package according to claim 15, wherein the material of the protective layer can be zinc, nickel or chromium.

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