CN1205656C - Intermetallic dielectric structure and fabrication method thereof - Google Patents

Abstract

An inter-metal dielectric structure is formed on a semiconductor substrate surface. The semiconductor substrate includes on its surface: a plurality of metal layers, an inter-metal dielectric layer covering the metal layers and the surface of the semiconductor substrate to a predetermined height, and an oxide cap layer with high compressive stress covering the surface of the inter-metal dielectric layer. The total value of the compressive stress of the inter-metal dielectric layer and the oxide cap layer is close to the tensile stress of the metal layer, so as to prevent the crack phenomenon caused by the overlarge stress difference between the metal layer and the dielectric layer. The invention forms the oxide cover layer by using a high density plasma-source radio frequency (HDP-SRF) method, can greatly improve the compressive stress of the oxide cover layer so as to solve the common crack defects and the bubble problems, and can ensure that the oxide cover layer has more dangling bonds (dangling bonds) inside to sufficiently intercept the diffused fluorine ions.

Description

Intermetallic dielectric structure and fabrication method thereof

technical field

The present invention relates to an oxide capping layer of a metal interlayer dielectric structure, in particular to an oxide capping layer produced by a high-density plasma-source radio frequency (HDP-SRF) chemical vapor deposition method, The method can solve the problem that the excessive tensile stress of the metal layer causes crack defects in the oxide cover layer.

technical background

In the ultra-large-scale integration (ULSI) process, the multi-metal interconnection structure is to make many metal wires in different layers to improve the circuit performance of components and the functional complexity of the circuit. The early development of inter-metal dielectric (inter-metaldielectric, IMD) focused on the improvement of gap filling and planarization, and with the improvement of high density plasma chemical vapor deposition (high density plasma CVD, HDPCVD) Various methods such as chemical mechanical polishing (CMP) and chemical mechanical polishing (CMP) have been proposed, and the above problems have been gradually overcome. Therefore, the current development focuses on how to reduce the dielectric coefficient of the IMD layer to increase the overall operation speed of the circuit.

For semiconductor devices with a size greater than 0.4 μm, the RC time delay of the circuit is determined by the front-end process, which includes the CMOS drive capacitor and load resistance. However, as the device size shrinks below 0.35 μm, the RC time delay of the front-end process will decrease, while the RC time delay caused by the back-end process will increase accordingly. In order to improve this problem, one way is to replace the traditional aluminum wire with copper wire to reduce the resistance value of the metal layer, and another way is to use a low dielectric constant dielectric material to make the IMD layer, which can effectively reduce the capacitance value. At present, in the CMOS circuit process below 0.35μm, the low dielectric constant dielectric material that has been integrated and used is fluorine-doped silicon dioxide (fluorinatedSiO ₂ , FSG), and its overall dielectric constant is about 3.5, which can Fill the gap between metal lines below 0.35 micron by HDPCVD or PECVD process. However, the stability of the fluorine ions in the FSG is poor, so an oxide capping layer is deposited on the surface of the FSG layer to prevent the problems of high plug resistance and wire corrosion caused by the diffusion of fluorine ions.

Please refer to FIG. 1 , which shows a schematic cross-sectional view of a general IMD structure. After the pre-production process is completed, a semiconductor silicon substrate 10 includes components and circuits not shown, and is covered with a dielectric layer 12 . In the back-end process, a plurality of first metal layers 14I are defined and formed on the surface of the dielectric layer 12. The material of the first metal layer 14I can be AlCu, which can be used as the first layer of interconnecting wires. Then uniformly cover a silicon-rich oxide (silicon-rich oxide, SRO) layer 16 on the entire surface of the dielectric layer 12 and the first metal layer 14I, and then utilize a HDPCVD method to deposit a HDP-FSG layer 18, which can be filled Fill the space between the first metal layer 14I. Next, a PE-FSG layer 20 is deposited by PECVD, which can compensate the unevenness of the protrusions and depressions on the surface of the HDP-FSG layer 18 . Finally, the surface of the PE-FSG layer 20 is planarized by CMP until it reaches the required thickness of the IMD structure, and then an oxide capping layer 22 is deposited on the surface of the PE-FSG layer 20 by PECVD process, and the IMD structure is roughly completed. . Subsequently, a plurality of second metal layers 14II can be formed on the flat surface of the IMD structure to serve as second-layer interconnection wires.

However, in the above IMD structure, the metal layer 14 has a very high tensile stress (tensile stress), about +3-5E9dyne/cm ² , while the compressive stress of the HDP-FSG layer 18 is only up to 8E8dyne/cm ² , PE- The compressive stress of the FSG layer 20 is only -1.5E9 dyne/cm ² , and the compressive stress of the oxide capping layer 22 is only -7E8 dyne/cm ² . It can be seen that the total compressive stress of the stacked oxide structure in the IMD structure is much smaller than the tensile stress of the metal layer 14, so it is very easy to generate cracks in the oxide capping layer 22, especially in the metal layer 14 with small gaps. Nearby, the above-mentioned oxide layers (16, 18, 20, 22) are more prone to cracking. Moreover, as the number of stacked IMD structures on the surface of the semiconductor silicon substrate 10 increases, and the number of stacked layers of interconnecting wires also increases, the cumulative value of the tensile stress produced by all metal layers 14 will be much greater than that of all oxide layers. (16, 18, 20, 22) of compressive stress cumulative value, and such a net stress increasing slowly layer by layer, will eventually lead to serious oxide layer cracking problems.

In view of this, in order to improve the crack defects of the oxide layer, a known method is to use _SiH4 as the reaction gas PECVD process to make the oxide capping layer 22, which can increase the compressive stress of the oxide capping layer 22 to -1.83 E9dyne/cm ² , but crack defects could not be improved. Another method is to use TEOS as the reactive gas PECVD process to make the oxide cap layer 22, which can increase the compressive stress of the oxide cap layer 22 to -2.87E9dyne/cm ² , which can improve the crack phenomenon, but it will The bubble problem occurs due to the fluorine diffusion phenomenon in the dielectric layer 12 .

Contents of the invention

The object of the present invention is to propose an oxide capping layer of an inter-metal dielectric structure, which can make the total compressive stress value of the oxide capping layer and the inter-metal dielectric layer equal to the tensile stress value of the metal layer, to solve the common Crack defects and air bubbles.

The present invention is an inter-metal dielectric structure, characterized in that it includes:

A plurality of metal layers are defined to be formed on the surface of a semiconductor substrate; an inter-metal dielectric layer covers the metal layer and the surface of the semiconductor substrate to a predetermined height; and is formed by a high-density plasma-source radio frequency process An oxide capping layer covers the surface of the inter-metal dielectric layer.

In the inter-metal dielectric structure, the metal layer is made of AlCu material.

The inter-metal dielectric structure, wherein the inter-metal dielectric layer includes:

a first fluorine-doped silicon dioxide (HDP-FSG) layer formed by high-density plasma chemical vapor deposition, covering the metal layer and the surface of the semiconductor substrate to a predetermined height; and

A second fluorine-doped silicon dioxide (PE-FSG) layer formed by plasma enhanced chemical vapor deposition method covers the first fluorine-doped silicon dioxide layer to a predetermined height.

In the inter-metal dielectric structure, the compressive stress of the oxide capping layer can reach -4E9--3E9 dyne/cm ² .

The inter-metal dielectric structure further includes a silicon-rich oxide (SRO) layer covering the plurality of metal layers and the surface of the semiconductor substrate.

The inter-metal dielectric structure, wherein the oxide capping layer has a lot of dangling bonds inside, enough to trap the diffused fluorine ions, and make the oxide capping layer have extremely high compressive stress, Sufficient to prevent crack defects as well as bubble problems.

The present invention also provides a method for fabricating an inter-metal dielectric structure, comprising the following steps:

Define forming a plurality of metal layers on the surface of a semiconductor substrate; forming an intermetal dielectric layer to cover the metal layer and the surface of the semiconductor substrate to a predetermined height; and forming a An oxide capping layer covers the surface of the inter-metal dielectric layer.

The step of forming the intermetallic dielectric layer includes: forming a first fluorine-doped silicon dioxide layer by a high-density plasma chemical vapor deposition method, covering the metal layer and the surface of the semiconductor substrate to a predetermined height; And a second fluorine-doped silicon dioxide layer formed by plasma enhanced chemical vapor deposition method, covering the first fluorine-doped silicon dioxide layer to a predetermined height.

The fabrication method of the oxide covering is to carry out the high-density plasma-source radio frequency process in a high-density plasma chemical vapor deposition equipment, and its power source only uses a source radio frequency generator.

The power of the source radio frequency generator of the high density plasma-source radio frequency is 1300-3100W.

The high density plasma-source RF gas source SiH ₄ has a flow rate of 82-15 sccm.

The gas source _O2 flow rate of the high density plasma-source radio frequency is 150-27 sccm.

The compressive stress of the oxide capping layer can reach -4E9--3E9dyne/cm ² .

The manufacturing method of the inter-metal dielectric structure further includes forming a silicon-rich oxide layer to cover the plurality of metal layers and the surface of the semiconductor substrate.

The oxide capping layer has more suspended bonds inside, which is enough to trap the diffused fluorine ions, and can make the oxide capping layer have extremely high compressive stress, which is enough to prevent problems such as crack defects and air bubbles.

The present invention uses the high-density plasma-source radio frequency (HDP-SRF) method to form the oxide capping layer. Compared with a feature of various oxide capping layers in the past, the compressive stress of the oxide capping layer can be greatly improved to solve the common Crack defects and air bubbles.

The present invention uses the high-density plasma-source radio frequency (HDP-SRF) method to form the oxide capping layer. Compared with another feature of the previous various oxide capping layers, the oxide capping layer can have more suspended bonds inside. (dangling bond), sufficient to trap diffused fluoride ions.

Description of drawings

1 is a schematic cross-sectional view of a general IMD structure;

Fig. 2 is a schematic cross-sectional view of an IMD structure of the present invention;

FIG. 3 is a schematic diagram of HDPCVD equipment used in the HDP-SRF process of the present invention.

Symbol Description

Semiconductor silicon substrate 10;

Dielectric layer 12;

first metal layer 14I;

SRO layer 16;

HDP-FSG layer 18;

PE-FSG layer 20;

oxide capping layer 22;

second metal layer 14II;

The technology of the present invention:

Semiconductor silicon substrate 30;

Dielectric layer 32;

first metal layer 34I;

SRO layer 36;

HDP-FSG layer 38;

PE-FSG layer 40;

Detailed ways

Please refer to FIG. 2 , which shows a schematic cross-sectional view of the IMD structure of the present invention. After the pre-production process is completed, a semiconductor silicon substrate 30 includes components and circuits not shown, and is covered with a dielectric layer 32 . In the later stage of the process, a plurality of first metal layers 34I are defined and formed on the surface of the dielectric layer 32, and the material thereof can be AlCu, which can be used as the first layer of interconnecting wires. Then, a silicon-rich oxide (silicon-rich oxide, SRO) layer 36 is uniformly covered on the entire surface of the dielectric layer 32 and the first metal layer 34I, and then a HDP-FSG layer 38 is deposited by HDPCVD, which can be The gaps between the first metal layers 34I are filled. Next, a PE-FSG layer 40 is deposited by PECVD, which can compensate the unevenness of the protrusions and depressions on the surface of the HDP-FSG layer 38 and provide the required thickness for the IMD structure. Subsequently, the surface of the PE-FSG layer 40 can be planarized by using a CMP process. Finally, a high-density plasma-source radio frequency (HDP-SRF) process is performed in an HDPCVD equipment, and an oxide capping layer 42 with high compressive stress is deposited on the surface of the PE-FSG layer 40, and the IMD structure is roughly completed. Subsequently, a plurality of second metal layers 34II can be formed on the flat surface of the IMD structure to serve as second-layer interconnection wires.

Please refer to FIG. 3 , which shows a schematic diagram of the HDPCVD equipment used in the HDP-SRF process of the present invention. A HDPCVD device 50 includes a reaction chamber 52, a gas delivery system 54, an exhaust system 56, a process control system 58, a bias radio frequency (BRF) generator 60, and a source radio frequency (source radio frequency, SRF) generator 62. When carrying out the HDP-SRF process, close the bias screen generator 60, and only open the source radio frequency generator 62. The process conditions in a preferred embodiment are: the power of the source radio frequency generator 62 is 1300-3100w, and the gas source The flow rate of SiH4 is 82-15 sccm and the flow rate of gas source _O2 is 150-27 sccm. According to the experimental results, when the flow rate of the gas source SiH ₄ in the HDP-SRF process is 76-86 sccm, the compressive stress of the oxide capping layer 42 can reach -4E9--3E9dyne/cm ² , which can make the oxide capping layer 42 There are more dangling bonds inside, enough to trap the diffused fluorine ions, and the oxide capping layer 42 can have extremely high compressive stress, enough to prevent problems such as crack defects and air bubbles.

The above description is only a preferred embodiment of the present invention, but it is not intended to limit the present invention. Any changes or substitutions that can be easily imagined by anyone familiar with the art within the technical scope disclosed in the present invention shall be covered. Within the protection of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (15)

1. dielectric structure between metal layers is characterized in that including:

A plurality of metal levels, definition is formed on the semiconductor substrate surface; One dielectric layer between metal layers covers this metal level and the surface at this semiconductor-based end predetermined altitude; And, cover the surface of this dielectric layer between metal layers by the monoxide cap rock that high-density electric slurry-source radio frequency processing procedure forms.

2. dielectric structure between metal layers as claimed in claim 1, wherein this metal level is made of the AlCu material.

3. dielectric structure between metal layers as claimed in claim 1, wherein this dielectric layer between metal layers includes:

The one first fluorine doped silica layer that is formed by the high density plasma enhanced chemical vapor deposition method covers this metal level and the surface at this semiconductor-based end predetermined altitude; And

The one second fluorine doped silica layer that is formed by electricity slurry reinforcement formula chemical gaseous phase depositing process covers this first fluorine doped silica layer to a predetermined altitude.

4. dielectric structure between metal layers as claimed in claim 1, wherein the compression stress of this oxide cap can reach-4E9--3E9dyne/cm ²

5. dielectric structure between metal layers as claimed in claim 1, other includes one and is rich in silicon oxide layer, covers the surface at these a plurality of metal levels and this semiconductor-based end.

6. dielectric structure between metal layers as claimed in claim 1, wherein the inside of this oxide cap has many suspension keys, be enough to hold back the fluorine ion of diffusion, and can make this oxide cap have high compression stress, be enough to prevent rift defect and air bubble problem.

7. the manufacture method of a dielectric structure between metal layers comprises the following steps:

Definition forms a plurality of metal levels on the semiconductor substrate surface;

Form a metal intermetallic dielectric layer and cover this metal level and the surface at this semiconductor-based end predetermined altitude; And

By the monoxide cap rock that high-density electric slurry-source radio frequency processing procedure forms, cover the surface of this dielectric layer between metal layers.

8. the manufacture method of dielectric structure between metal layers as claimed in claim 7, the step that wherein forms this metal intermetallic dielectric layer comprises:

One first fluorine doped silica layer by the high density plasma enhanced chemical vapor deposition method forms covers this metal level and the surface at this semiconductor-based end predetermined altitude; And

One second fluorine doped silica layer by electricity slurry reinforcement formula chemical gaseous phase depositing process forms covers this first fluorine doped silica layer to a predetermined altitude.

9. the manufacture method of dielectric structure between metal layers as claimed in claim 7, wherein the manufacture method of this oxide covering is to carry out this high-density electric slurry-source radio frequency processing procedure in a high density plasma enhanced chemical vapor deposition equipment, and its power supply only adopts the source r-f generator.

10. the manufacture method of dielectric structure between metal layers as claimed in claim 9, wherein the power of the source r-f generator of this high-density electric slurry-source radio frequency is 1300-3100W.

11. the manufacture method of dielectric structure between metal layers as claimed in claim 9, wherein the gas source SiH of this high-density electric slurry-source radio frequency ₄Flow be 82-15sccm.

12. the manufacture method of dielectric structure between metal layers as claimed in claim 9, wherein the gas source O of this high-density electric slurry-source radio frequency ₂Flow be 150-27sccm.

13. the manufacture method of dielectric structure between metal layers as claimed in claim 7, wherein the compression stress of this oxide cap can reach-4E9--3E9dyne/cm ²

14. the manufacture method of dielectric structure between metal layers as claimed in claim 7 more comprises and forms one and be rich in silicon oxide layer and cover the surface at these a plurality of metal levels and this semiconductor-based end.

15. the manufacture method of dielectric structure between metal layers as claimed in claim 7, wherein the inside of this oxide cap has more suspension key, foot has been held back the fluorine ion of diffusion, and can make this oxide cap have high compression stress, and foot has prevented rift defect and air bubble problem.