CN1237598C - Method for forming metal capacitors in damascene process - Google Patents

Abstract

A method for forming metal capacitor in damascene process. Before forming the metal thin film capacitor, the copper damascene process is used to fabricate the interconnect underneath. The bottom electrode of the capacitor is formed in a damascene process, which is also used to form the conductive line and plug. And forming an anti-reflection layer on the insulating layer for isolating the dual damascene structure, wherein the anti-reflection layer can also be used as a hard mask layer, a grinding stop layer and an etching stop layer, and then the anti-reflection layer is connected on the anti-reflection layer, another insulating layer and a metal layer are sequentially formed, and photoetching is carried out to form an upper electrode and a capacitor insulating layer. After the capacitor is completed, the copper damascene process is continued to fabricate the interconnect thereon. The method has the advantages of reducing the photoetching steps and manufacturing cost of the integrated circuit with the built-in capacitor, reducing the integrated circuit with the built-in capacitor, easily controlling the manufacturing process of the integrated circuit with the built-in capacitor and manufacturing the integrated circuit with the built-in capacitor by using a copper process so as to reduce the RC delay.

Description

Method for forming metal capacitors in damascene process

technical field

The present invention relates to forming integrated circuits with built-in capacitors, and more particularly to a method of forming metal capacitors in a damascene process.

Background technique

It is well known that capacitors can be integrated with various integrated circuits. For example, they can be used as decoupling capacitors to improve voltage regulation and provide noise immunity for power distribution. It can also be applied in analog/logic circuit, analog-digital converter, mixed signal (mixedsignal), or radio frequency (radio frequency) circuit operation, etc.

As shown in FIGS. 1-4, it is a traditional method of manufacturing a semiconductor element containing a capacitor 20. As shown in FIG. 1, an aluminum metal layer is deposited on the insulating layer 12, followed by a photolithographic etching process, and patterned into an aluminum metal layer 14a and 14b. The insulating layer 12 includes some elements (not shown) formed on and in the silicon substrate. Next, an insulating layer 16 is formed on the aluminum metal layers 14 a and 14 b and the insulating layer 12 , and a tungsten plug (tungsten plug; W-plug) 18 is formed in the insulating layer 16 to be electrically connected to the aluminum metal layer 14 a. Afterwards, a metal layer/dielectric layer/metal layer is sequentially deposited on the tungsten plug 18 and the insulating layer 16, and after photolithographic etching, the first conductive plate 21, the dielectric layer 22 and the second conductive plate 23 are formed, A capacitor 20 is thus constituted, as shown in FIG. 2 . Wherein, the first conductive plate 21 (ie, the lower electrode) is connected to the aluminum metal layer 14a via the tungsten plug 18 . Continue to deposit another insulating layer 26 over the capacitor 20 and the insulating layer 16 , and simultaneously form tungsten plugs 28 a and 28 b in the insulating layer 26 and the insulating layer 16 below it, as shown in FIG. 3 . Continue to deposit another aluminum metal layer on the insulating layer 26 and the tungsten plugs 28 a and 28 b, and perform photolithography and etching process to form aluminum metal layers 34 a and 34 b, as shown in FIG. 4 . The aluminum metal layer 34a is electrically connected to the first conductive plate 23 (ie, the upper electrode) through the tungsten plug 28a, and the aluminum metal layer 34b is electrically connected to the lower aluminum metal layer 14b through the tungsten plug 28b. Its main flaws are:

In the above process, an additional photolithography step is required to form the capacitor 20 to integrate the capacitor 20 into an integrated circuit, thus increasing the cost of the entire semiconductor process.

However, the integration of the interconnection process and the capacitor process with aluminum metal has gradually failed to meet the current requirements for increasing component integration and data transmission speed. Therefore, it is a current development trend to reduce RC delay (RC delay) by using metal copper with high conductivity as a wire. However, copper metal cannot be used to define patterns by dry etching. The reason is that the copper chloride (CuCl ₂ ) produced by the reaction of copper metal with chlorine plasma gas has a very high boiling point (about 1500 ° C), so the production of copper wires requires It is performed by a dama scene process.

Contents of the invention

The main object of the present invention is to provide a method for forming a metal capacitor in a damascene process, by forming a first copper wire and a second copper wire in a first insulating layer before forming a film capacitor, and at least less than the first and second copper wires A first sealing layer is formed on the two copper wires. Then, the second insulating layer and the anti-reflection layer are sequentially formed on the first sealing layer. When forming a metal capacitor, only one additional photolithography and etching step is required, which overcomes the disadvantages of the existing technology and achieves the reduction in the production of integrated circuits with built-in capacitors. The photolithographic etching steps and the purpose of reducing manufacturing costs.

A second object of the present invention is to provide a method for forming metal capacitors in a damascene process, so as to achieve the purpose of forming integrated circuits containing capacitors with fewer photolithography and etching steps.

A third object of the present invention is to provide a method for forming metal capacitors in a damascene process, so as to achieve the purpose of reducing the number of integrated circuits containing capacitors.

A fourth object of the present invention is to provide a method for forming metal capacitors in a damascene process, so as to achieve the purpose of easily controllable manufacturing process of integrated circuits containing capacitors.

A fifth object of the present invention is to provide a method for forming metal capacitors in a damascene process, so as to achieve the purpose of using a copper process to manufacture integrated circuits containing capacitors and reduce RC delay.

The purpose of the present invention is achieved in that a method for forming a metal capacitor in a damascene process is characterized in that it at least includes the following steps:

(1) providing a first insulating layer;

(2) forming a first copper wire and a second copper wire in the first insulating layer;

(3) forming a first sealing layer at least on the first and second copper wires;

(4) forming a second insulating layer on the first sealing layer;

(5) forming an anti-reflection layer on the second insulating layer;

(6) forming a dual damascene structure comprising a first copper plug, a second copper plug, a third copper wire and a fourth copper wire in the antireflection layer, the second insulating layer and the first sealing layer, wherein The first copper plug is used for connecting the third copper wire and the first copper wire, and the second copper plug is used for connecting the fourth copper wire and the second copper wire;

(7) forming a third insulating layer on the anti-reflection layer, the third copper wire and the fourth copper wire;

(8) forming a metal layer on the third insulating layer;

(9) patterning the metal layer and the third insulating layer on the anti-reflective layer as an etching stop layer, so as to form an upper electrode and a capacitor insulating layer corresponding to the third copper wire;

(10) forming a fourth insulating layer on the antireflection layer and the upper electrode;

(11) Forming a dual damascene structure comprising a third copper plug, a fourth copper plug, a fifth copper wire and a sixth copper wire in the fourth insulating layer, wherein the third copper plug is used to connect the first Five copper wires and an upper electrode, the fourth copper plug is used to connect the sixth copper wire and the fourth copper wire;

(12) Forming a second sealing layer on at least the fifth and sixth copper wires.

The material of the anti-reflection layer is at least one selected from silicon oxynitride or silicon carbide. The material of the third insulating layer is at least one selected from silicon nitride, silicon oxynitride, silicon carbide, tantalum oxide, zirconium oxide, hafnium oxide or aluminum oxide. The thickness of the third insulating layer is between 100 angstroms and 1200 angstroms. The material of the metal layer is at least one selected from titanium, titanium nitride, tantalum, tantalum nitride, aluminum or aluminum-copper alloy. The thickness of the metal layer is between 100 angstroms and 2000 angstroms.

Another method for forming a metal capacitor in a damascene process is characterized in that it at least includes the following steps:

(1) providing a first insulating layer;

(2) forming a first copper wire and a second copper wire in the first insulating layer;

(3) forming a first sealing layer at least on the first and second copper wires;

(4) forming a second insulating layer on the first sealing layer;

(5) forming an anti-reflection layer on the second insulating layer;

(6) Forming a dual damascene structure including a first copper plug, a second copper plug, a third copper wire, and a fourth copper wire in the antireflection layer, the second insulating layer, and the first sealing layer, wherein the first copper plug a copper plug is used for connecting the third copper wire and the first copper wire, and the second copper plug is used for connecting the fourth copper wire and the second copper wire;

(7) forming a second sealing layer on the anti-reflection layer, the third copper wire and the fourth copper wire;

(8) forming a third insulating layer on the second sealing layer;

(9) forming a metal layer on the third insulating layer;

(10) On the second sealing layer as an etch stop layer, pattern the metal layer and the third insulating layer to form an upper electrode and a capacitor insulating layer corresponding to the third copper wire, wherein the A portion of the second sealing layer also serves as the capacitor insulating layer;

(11) forming a fourth insulating layer on the second sealing layer and the upper electrode;

(12) Forming a dual damascene structure including a third copper plug, a fourth copper plug, a fifth copper wire, and a sixth copper wire in the fourth insulating layer and the second sealing layer, wherein the third copper plug The plug is used to connect the fifth copper wire and the upper electrode, and the fourth copper plug is used to connect the sixth copper wire and the fourth copper wire;

(13) A third sealing layer is formed on at least the fifth and sixth copper wires.

The following describes in detail in conjunction with preferred embodiments and accompanying drawings.

Description of drawings

1 to 4 are schematic cross-sectional views of the traditional process of integrating capacitors into integrated circuits.

5-12 are schematic cross-sectional views of the process of forming a metal capacitor in a damascene process according to Embodiment 1 of the present invention.

13-20 are schematic cross-sectional views of the process of forming a metal capacitor in a damascene process according to Embodiment 2 of the present invention.

Detailed ways

Example 1

Referring to FIGS. 5-12 , a method for forming a metal capacitor in a damascene process according to a first preferred embodiment of the present invention will be described in detail.

Referring to FIG. 5, another insulating layer 106 is formed on the insulating layer 102, wherein the insulating layer 102 may include other interconnection lines, and the insulating layer 102 includes elements formed on and in the substrate. In order to clearly describe this Invention, these underlying circuit elements are not shown in the drawings. Copper wires 104 a and 104 b are formed in the insulating layer 106 with a thickness of about 2000 to 6000 angstroms by using a damascene process. For example, after trenches are formed in the insulating layer 106, a compliant barrier layer (not shown) is formed, copper is filled, and then chemical mechanical polishing is performed to remove excess copper and barrier layers. barrier layer. Then at least the sealing layer 108 is formed on the copper wires 104a and 104b. In the figure, the comprehensive sealing layer 108 is taken as an example, its thickness is about 100-400 angstroms, and its material can be silicon nitride (SiN) or Silicon carbide (SiC)

Next, an insulating layer 110 and an anti-reflection layer 112 are sequentially formed on the sealing layer 108 . When forming a dual damascene structure, the anti-reflection layer 112 can be used as a hard mask, when forming copper wires, the anti-reflection layer 112 can be used as a grinding stop layer; when forming the upper electrode of a metal capacitor, the anti-reflection layer 112 can be used as an etching stop layer. The material used to form the anti-reflection layer 112 may be silicon oxynitride (SiON) or silicon carbide (SiC). The thickness of the anti-reflection layer 112 is about 100-600 angstroms.

A dual damascene pattern is formed in the anti-reflective layer 112, the insulating layer 110 and the sealing layer 108. The pattern is composed of vias 114a and 114b and trenches 116a and 116b, wherein the via 114b exposes the copper wire 104b The surface of the copper wire 104a is exposed by the via hole 114a.

Referring to FIG. 6 , a conformable barrier layer (not shown) is formed on the surface of the anti-reflective layer 112 , the via holes 114 a and 114 b , and the trenches 116 a and 116 b. Copper metal is deposited on the barrier layer and filled in vias 114a and 114b and trenches 116a and 116b. A chemical mechanical polishing process is used to remove excess parts, and the anti-reflective layer 112 is used as a polishing stop layer to form a dual damascene structure composed of copper plugs 120a and 120b and copper wires 122a and 122b. Wherein, the copper wire 122a is used as the lower electrode of the metal capacitor.

The aforementioned dual damascene process is not only used to form the copper plugs 120a and 120b and the copper wire 122b, but also used to form the bottom electrode 122a. Therefore, no additional photolithographic etching process is required to form the lower electrode 122a, moreover, the lower electrode 122a is located on the same plane as the copper wire 122b.

Next, an insulating layer 124 is formed on the anti-reflection layer 112 and the copper wires 122a and 122b, and the insulating layer 124 is a capacitor insulating layer as a metal capacitor. The thickness of the insulating layer 124 is about 100-1200 angstroms, but the actual thickness depends on the application of the capacitor and its required capacitance. The insulating layer 124 can be made of silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), silicon carbide (SiC), tantalum oxide (TaO ₂ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ). , aluminum oxide (Al ₂ O ₃ ), or other materials with high dielectric constant.

Referring to FIG. 7, a metal layer 126 is formed on the insulating layer 124. The metal layer 126 is used to form the upper electrode of the metal capacitor, and its thickness is about 100-2000 angstroms. The material of the above metal layer 126 can be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum, aluminum copper alloy (AlCu) and the like.

Referring next to FIG. 8 , the metal layer 126 and the insulating layer 124 are defined to form the upper electrode 126 and the capacitor insulating layer 124 by performing a photolithographic etching process until the anti-reflection layer 112 serving as an etching stop layer is exposed.

According to the above-mentioned steps, when forming the metal capacitor 128 , only one additional photolithography and etching step is required. Therefore, it is possible to reduce photolithography and etching steps for manufacturing integrated circuits containing capacitors, and also reduce manufacturing costs.

The area of the formed lower electrode 122 a roughly corresponds to the area of the upper electrode 126 , and the area of the upper electrode 126 needs to be greater than or equal to the area of the lower electrode 122 a. The lower electrode 122 a , the insulating layer 124 and the upper electrode 126 form a capacitor 128 .

Referring next to FIG. 9 , a blanket sacrificial insulating layer 130 is formed on the anti-reflection layer 112 and the metal capacitor 128 . Then carry out a planarization process on the sacrificial insulating layer 130, such as a chemical mechanical polishing process, so that the surface of the insulating layer 130 will not be affected by the topographical fluctuations caused by the capacitor 128 below it, and become flat as shown in FIG. The insulating layer 130' on the surface facilitates the subsequent process.

Referring to FIGS. 11 and 12 , another dual damascene process is then performed to form a dual damascene pattern in the insulating layer 130', which is composed of trenches 134a and 134b and via holes 132a and 132b. Wherein, the via hole 132b exposes the surface of the wire 122b to be electrically contacted, and the via hole 132a exposes the surface of the upper electrode 126 to be electrically contacted.

As shown in FIG. 12 , a compliant barrier layer (not shown) is formed on the surfaces of the insulating layer 130', the trenches 134a and 134b, and the via holes 132a and 132b. Copper metal is deposited on the barrier layer and filled into the trenches 134a and 134b and the vias I32a and 132b. CMP is then performed to remove excess copper metal and barrier layer to form copper traces 138a and 138b and copper plugs 136a and 136b in the dual damascene pattern. After that, a sealing layer 140 is covered on the copper wires 138a and 138b and the insulating layer 130', and its material can be silicon nitride or silicon carbide. Therefore, the upper electrode 126 is electrically connected to the copper wire 138a through the copper plug 136a, and the copper wire 122b is electrically connected to the copper wire 138b through the copper plug 136b.

Subsequent copper manufacturing process continues until the manufacture of the entire interconnection is completed. Since it is prior art, it will not be restated.

The material of the above-mentioned insulating layers 102, 106, 110 and 130 can be an insulating material with a low dielectric constant, such as doped or undoped silicon oxide, a spin-coated polymer with a low dielectric constant, and a chemical vapor deposition method. Low dielectric constant material.

Example 2

Referring to FIG. 13-FIG. 20, it is used to illustrate a method of forming a metal capacitor in a damascene process according to the preferred embodiment 2 of the present invention.

Referring first to FIG. 13, another insulating layer 206 is formed on the insulating layer 202, wherein the insulating layer 202 may include other interconnection lines, and the insulating layer 202 includes elements formed on and in the substrate, for clarity of description In the context of the present invention, these underlying circuit elements are not shown in the drawings. Copper wires 204a and 204b are formed in the insulating layer 206 with a thickness of approximately 2000-6000 angstroms by using a damascene process. For example, after trenches are formed in the insulating layer 206, a compliant barrier layer (not shown) is formed, copper is filled, and then chemical mechanical polishing is performed to remove excess copper and barriers. barrier layer. Then at least the sealing layer 208 is formed on the copper wires 204a and 204b. In the figure, it is taken to form a comprehensive sealing layer 208 as an example, its thickness is about 100-400 angstroms, and its material can be silicon nitride (SiN) or Silicon carbide (SiC).

Next, an insulating layer 210 and an anti-reflection layer 212 are sequentially formed on the sealing layer 208 . When forming a dual damascene structure, the anti-reflection layer 212 can be used as a hard mask; when forming copper wires, the anti-reflection layer 212 can be used as a polishing stop layer. The material used to form the antireflection layer 212 may be silicon oxynitride (SiON) or silicon carbide (SiC). The thickness of the anti-reflection layer 212 is about 100-600 angstroms.

A dual damascene pattern is formed in the anti-reflection layer 212, the insulating layer 210, and the sealing layer 208. The pattern is composed of vias 214a and 214b and trenches 216a and 216b, wherein the via 214b exposes the copper wire 204b The surface of the copper wire 204a is exposed by the via hole 214a.

Referring next to FIG. 14 , a compliant barrier layer (not shown) is formed on the surface of the anti-reflection layer 212 , the via holes and 214 b , and the trenches 216 a and 216 b. Copper metal is deposited on the barrier layer and filled in vias 214a and 214b and trenches 216a and 216b. A chemical mechanical polishing process is used to remove excess parts, and the anti-reflection layer 212 is used as a polishing stop layer to form a dual damascene structure composed of copper plugs 220a and 220b and copper wires 222a and 222b. Wherein, the copper wire 222a is used as the lower electrode of the metal capacitor.

The aforementioned dual damascene process is not only used to form the copper plugs 220a and 220b and the copper wire 222b, but also used to form the bottom electrode 222a. Therefore, no additional photolithographic etching process is required to form the lower electrode 222a. Furthermore, the lower electrode 222a is located on the same plane as the copper wire 222b.

Next, a sealing layer 223 is formed on the anti-reflection layer 212 and the copper wires 222a and 222b, with a thickness of about 100-400 angstroms. The sealing layer 223 is used as a diffusion barrier layer to avoid the migration of copper atoms; the sealing layer 223 can also be used as an etching stop layer when forming the upper electrode; it can also be used as a part of the capacitor insulating layer. Its material can be silicon nitride or silicon carbide.

Continue to form an insulating layer 224 with a high dielectric constant on the sealing layer 223 . Here, the sealing layer 223 can improve the adhesion between the insulating layer 224 and the lower electrode 222a. The insulating layer 224 is a capacitor insulating layer as another part. The thickness of the insulating layer 224 is about 100-1200 angstroms, but the actual thickness depends on the application of the capacitor and its required capacitance. The insulating layer 224 can be made of silicon nitride, silicon oxynitride, silicon carbide (SiC), tantalum oxide (TaO ₂ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ). or other materials with a high dielectric constant.

Referring to FIG. 15, a metal layer 226 is formed on the insulating layer 224. The metal layer 226 is used to form the upper electrode of the metal capacitor, and its thickness is about 100-2000 angstroms. The material of the above metal layer 226 can be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum, aluminum copper alloy (AlCu) and the like.

Referring next to FIG. 16, the metal layer 226 and the insulating layer 224 are defined to form the upper electrode 226 and a part of the capacitor insulating layer 225. The method is to perform a photolithographic etching process until the anti-reflection layer 223 as an etching stop layer is exposed.

According to the above steps, when forming the metal capacitor 228 , only one additional photolithographic etching step is required. Therefore, the photolithography and etching steps for manufacturing the integrated circuit containing the capacitor 228 can be reduced, and the manufacturing cost can also be reduced.

The capacitor insulating layer 225 includes an insulating layer 224 and a sealing layer 223 . The formed area of the lower electrode 222 a roughly corresponds to the area of the upper electrode 226 , and the capacitance of the metal capacitor 228 is also controlled by the overlapping area of the lower electrode 222 a and the upper electrode 226 . The lower electrode 222 a , the insulating layer 225 and the upper electrode 226 form a capacitor 228 .

Referring to FIG. 17 , a blanket sacrificial insulating layer 230 is formed over the sealing layer 223 and the metal capacitor 228 . Then planarize the sacrificial insulating layer 230, such as a chemical mechanical polishing process, so that the insulating layer 230 becomes the insulating layer 230' with a flat surface as shown in FIG. 18, so as to facilitate subsequent processes.

Referring to FIGS. 19 and 20, another dual damascene process is then performed to form a dual damascene pattern in the insulating layer 230' and the sealing layer 223. This pattern is composed of trenches 234a and 234b and via holes 232a and 232b. Wherein, the via hole 232b exposes the surface of the wire 222b to be electrically contacted, and the via hole 232a exposes the surface of the upper electrode 226 to be electrically contacted.

As shown in FIG. 20 , a compliant barrier layer (not shown) is formed on the surfaces of the insulating layer 230', the trenches 234a and 234b, and the via holes 232a and 232b. Copper metal is deposited on the barrier layer and filled into the trenches 234a and 234b and the via holes 232a and 232b. Chemical mechanical polishing is then performed to remove excess copper metal and barrier layer to form copper traces 238a and 238b and copper plugs 236a and 236b in the dual damascene pattern. After that, a sealing layer 240 is covered on the copper wires 238a and 238b and the insulating layer 230', and its material can be silicon nitride or silicon carbide. Therefore, the upper electrode 226 is electrically connected to the copper wire 238a through the copper plug 236a, and the copper wire 222b is electrically connected to the copper wire 238b through the copper plug 236b.

Subsequent copper manufacturing process continues until the manufacture of the entire interconnection is completed.

The above insulating layers 202, 206, 210 and 230 can be made of low dielectric constant insulating material (such as doped or undoped silicon oxide), low dielectric constant spin-on polymer, and chemical vapor deposition Type low dielectric constant material, etc.

Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention belong to the present invention. within the scope of protection.

Claims (12)

1. A method for forming a metal capacitor in a damascene process, characterized in that it at least comprises the following steps: (1) providing a first insulating layer; (2) forming a first copper wire and a second copper wire in the first insulating layer; (3) forming a first sealing layer at least on the first and second copper wires; (4) forming a second insulating layer on the first sealing layer; (5) forming an anti-reflection layer on the second insulating layer; (6) forming a dual damascene structure comprising a first copper plug, a second copper plug, a third copper wire and a fourth copper wire in the antireflection layer, the second insulating layer and the first sealing layer, wherein The first copper plug is used for connecting the third copper wire and the first copper wire, and the second copper plug is used for connecting the fourth copper wire and the second copper wire; (7) forming a third insulating layer on the anti-reflection layer, the third copper wire and the fourth copper wire; (8) forming a metal layer on the third insulating layer; (9) patterning the metal layer and the third insulating layer on the anti-reflective layer as an etching stop layer, so as to form an upper electrode and a capacitor insulating layer corresponding to the third copper wire; (10) forming a fourth insulating layer on the antireflection layer and the upper electrode; (11) Forming a dual damascene structure comprising a third copper plug, a fourth copper plug, a fifth copper wire and a sixth copper wire in the fourth insulating layer, wherein the third copper plug is used to connect the first Five copper wires and an upper electrode, the fourth copper plug is used to connect the sixth copper wire and the fourth copper wire; (12) Forming a second sealing layer on at least the fifth and sixth copper wires. 2. The method for forming a metal capacitor in a damascene process according to claim 1, wherein the material of the anti-reflection layer is at least one selected from silicon oxynitride or silicon carbide. 3. The method for forming a metal capacitor in a damascene process according to claim 1, wherein the material of the third insulating layer is selected from silicon nitride, silicon oxynitride, silicon carbide, tantalum oxide, zirconium oxide, At least one of hafnium oxide or aluminum oxide. 4. The method for forming a metal capacitor in a damascene process according to claim 1, wherein the thickness of the third insulating layer is between 100 angstroms and 1200 angstroms. 5. The method for forming a metal capacitor in a damascene process according to claim 1, wherein the material of the metal layer is selected from titanium, titanium nitride, tantalum, tantalum nitride, aluminum or aluminum-copper alloy at least one. 6. The method for forming a metal capacitor in a damascene process according to claim 1, wherein the thickness of the metal layer is between 100 angstroms and 2000 angstroms. 7. A method for forming a metal capacitor in a damascene process, characterized in that it at least includes the following steps: (1) providing a first insulating layer; (2) forming a first copper wire and a second copper wire in the first insulating layer; (3) forming a first sealing layer at least on the first and second copper wires; (4) forming a second insulating layer on the first sealing layer; (5) forming an anti-reflection layer on the second insulating layer; (6) Forming a dual damascene structure including a first copper plug, a second copper plug, a third copper wire, and a fourth copper wire in the antireflection layer, the second insulating layer, and the first sealing layer, wherein the first copper plug a copper plug is used for connecting the third copper wire and the first copper wire, and the second copper plug is used for connecting the fourth copper wire and the second copper wire; (7) forming a second sealing layer on the anti-reflection layer, the third copper wire and the fourth copper wire; (8) forming a third insulating layer on the second sealing layer; (9) forming a metal layer on the third insulating layer; (10) On the second sealing layer as an etch stop layer, pattern the metal layer and the third insulating layer to form an upper electrode and a capacitor insulating layer corresponding to the third copper wire, wherein the A portion of the second sealing layer also serves as the capacitor insulating layer; (11) forming a fourth insulating layer on the second sealing layer and the upper electrode; (12) Forming a dual damascene structure including a third copper plug, a fourth copper plug, a fifth copper wire, and a sixth copper wire in the fourth insulating layer and the second sealing layer, wherein the third copper plug The plug is used to connect the fifth copper wire and the upper electrode, and the fourth copper plug is used to connect the sixth copper wire and the fourth copper wire; (13) A third sealing layer is formed on at least the fifth and sixth copper wires. 8. The method for forming a metal capacitor in a damascene process according to claim 7, wherein the material of the anti-reflection layer is at least one selected from silicon oxynitride or silicon carbide. 9. The method for forming a metal capacitor in a damascene process according to claim 7, wherein the material of the third insulating layer is selected from silicon nitride, silicon oxynitride, silicon carbide, tantalum oxide, zirconium oxide, At least one of hafnium oxide or aluminum oxide. 10. The method for forming a metal capacitor in a damascene process according to claim 7, wherein the thickness of the third insulating layer is between 100 angstroms and 1200 angstroms. 11. The method for forming a metal capacitor in a damascene process according to claim 7, wherein the material of the metal layer is selected from titanium, titanium nitride, tantalum, tantalum nitride, aluminum or aluminum-copper alloy at least one. 12. The method for forming a metal capacitor in a damascene process according to claim 7, wherein the thickness of the metal layer is between 100 angstroms and 2000 angstroms.

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